coreboot-gerrit November 2021

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Change in coreboot[master]: amd/i2c: Remove the weak function
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58771 ) Change subject: amd/i2c: Remove the weak function ...................................................................... amd/i2c: Remove the weak function BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/i2c/i2c.c M src/soc/amd/stoneyridge/i2c.c 2 files changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index ff9ec90..d2e0473 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -78,11 +78,6 @@ return -1; } -void __weak soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) -{ - /* Nothing by default. */ -} - static void dw_i2c_soc_init(bool is_early_init) { unsigned int bus; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 6a6d776..e589b04 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -5,6 +5,7 @@ #include <soc/iomap.h> #include <soc/i2c.h> #include "chip.h" +#include <drivers/i2c/designware/dw_i2c.h> static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" }, @@ -26,3 +27,8 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + /* Do nothing. */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Gerrit-Change-Number: 58771 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Set Gen3 default for all PCIe devices
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58799 ) Change subject: mb/google/guybrush: Set Gen3 default for all PCIe devices ...................................................................... mb/google/guybrush: Set Gen3 default for all PCIe devices Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index a98983b..af06e7f 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,6 +14,7 @@ .port_present = true, .start_logical_lane = 0, .end_logical_lane = 0, + .link_speed_capability = 3, .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_aspm = ASPM_L1, @@ -28,6 +29,7 @@ .port_present = true, .start_logical_lane = 1, .end_logical_lane = 1, + .link_speed_capability = 3, .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, @@ -43,6 +45,7 @@ .port_present = true, .start_logical_lane = 2, .end_logical_lane = 2, + .link_speed_capability = 3, .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_aspm = ASPM_L1, @@ -57,6 +60,7 @@ .port_present = true, .start_logical_lane = 4, .end_logical_lane = 7, + .link_speed_capability = 3, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_aspm = ASPM_L1, -- To view, visit https://review.coreboot.org/c/coreboot/+/58799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Gerrit-Change-Number: 58799 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: Update GPIO table for speak and dmic
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58877 ) Change subject: mb/google/brya/var/kano: Update GPIO table for speak and dmic ...................................................................... mb/google/brya/var/kano: Update GPIO table for speak and dmic Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: CT Lin <ctlin0(a)nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/fw_config.c M src/mainboard/google/brya/variants/kano/gpio.c 2 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved CT Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index 55a6fad..631a908 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -8,8 +8,8 @@ static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ }; static const struct pad_config dmic_disable_pads[] = { @@ -24,10 +24,10 @@ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ }; static const struct pad_config i2s_disable_pads[] = { diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f40da1..898c87c 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -82,18 +82,18 @@ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/58877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Gerrit-Change-Number: 58877 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: CT Lin <ctlin0(a)nuvoton.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google: Add OEM product names for various boards
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57392 ) Change subject: mb/google: Add OEM product names for various boards ...................................................................... mb/google: Add OEM product names for various boards All of these names came from public sources. Signed-off-by: Martin Roth <martin(a)coreboot.org> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/kahlee/Kconfig.name M src/mainboard/google/kukui/Kconfig.name M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/poppy/Kconfig.name M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/zork/Kconfig.name 8 files changed, 68 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index ea6f35c..d15c3d2 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -1,7 +1,7 @@ comment "Dedede" config BOARD_GOOGLE_BOTEN - bool "-> Boten" + bool "-> Boten (Lenovo 500e Chromebook Gen 3)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -20,6 +20,11 @@ select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + help + The Drawcia board supports the following devices: + - HP Chromebook x360 11 G4 EE (Drawcia) + - HP Chromebook 11 G9 EE (Drawlat) + - HP Chromebook 14 G7 (Drawman) config BOARD_GOOGLE_HABOKI bool "-> HABOKI" @@ -88,7 +93,7 @@ select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_SASUKE - bool "-> Sasuke" + bool "-> Sasuke (Samsung Galaxy Chromebook Go)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A @@ -96,7 +101,7 @@ select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_STORO - bool "-> Storo" + bool "-> Storo (Asus Chromebook CR1100)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e92f584..9102d03 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -1,11 +1,11 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI - bool "-> Akemi" + bool "-> Akemi (IdeaPad Flex 5/5i Chromebook)" select BOARD_GOOGLE_BASEBOARD_HATCH config BOARD_GOOGLE_DRATINI - bool "-> Dratini" + bool "-> Dratini (HP Pro c640 Chromebook)" select BOARD_GOOGLE_BASEBOARD_HATCH config BOARD_GOOGLE_DUFFY_LEGACY @@ -14,11 +14,11 @@ select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_DUFFY - bool "-> Duffy" + bool "-> Duffy (ASUS Chromebox 4)" select BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_FAFFY - bool "-> Faffy" + bool "-> Faffy (ASUS Fanless Chromebox)" select BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_HATCH @@ -27,7 +27,7 @@ select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_JINLON - bool "-> Jinlon" + bool "-> Jinlon (HP Elite c1030 Chromebook)" select BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_GFX_GENERIC @@ -37,20 +37,20 @@ select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_KAISA - bool "-> Kaisa" + bool "-> Kaisa (Acer Chromebox CXI4)" select BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_KOHAKU - bool "-> Kohaku" + bool "-> Kohaku (Samsung Galaxy Chromebook)" select BOARD_GOOGLE_BASEBOARD_HATCH config BOARD_GOOGLE_KINDRED - bool "-> Kindred" + bool "-> Kindred (Acer Chromebook 712)" select BOARD_GOOGLE_BASEBOARD_HATCH select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS - bool "-> Helios" + bool "-> Helios (ASUS Chromebook Flip C436FA)" select BOARD_GOOGLE_BASEBOARD_HATCH select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 @@ -66,13 +66,13 @@ select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_NIGHTFURY - bool "-> Nightfury" + bool "-> Nightfury (Samsung Galaxy Chromebook 2)" select BOARD_GOOGLE_BASEBOARD_HATCH select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_NOIBAT - bool "-> Noibat" + bool "-> Noibat (HP Chromebox G3)" select BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_PUFF @@ -91,7 +91,7 @@ select BOARD_GOOGLE_BASEBOARD_HATCH config BOARD_GOOGLE_WYVERN - bool "-> Wyvern" + bool "-> Wyvern (CTL Chromebox CBx2)" select BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_DOOLY diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index d040f31..1fa8217 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -1,20 +1,25 @@ comment "Kahlee" config BOARD_GOOGLE_ALEENA - bool "-> Aleena" + bool "-> Aleena/Kasumi (Acer Chromebook 315 (CB315-2H), 311 (C721) / Spin 311 (R721T))" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_CAREENA - bool "-> Careena" + bool "-> Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6)" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_GRUNT bool "-> Grunt" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_LIARA - bool "-> Liara" + bool "-> Liara (Lenovo 14e Chromebook, Chromebook S345-14)" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_NUWANI bool "-> Nuwani" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_TREEYA - bool "-> Treeya" + bool "-> Treeya (Lenovo 100e/300e Gen2 AMD)" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 3d5f309..d4d3a65 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -5,11 +5,11 @@ select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KRANE - bool "-> Krane" + bool "-> Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)" select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KODAMA - bool "-> Kodama" + bool "-> Kodama (Lenovo 10e Chromebook Tablet)" select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KAKADU @@ -31,7 +31,7 @@ select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_JUNIPER - bool "-> Juniper" + bool "-> Juniper (Acer Chromebook Spin 311 (CP311-3H))" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_KAPPA @@ -39,7 +39,7 @@ select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_DAMU - bool "-> Damu" + bool "-> Damu (ASUS Chromebook Flip CM3 (CM3200))" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_CERISE @@ -55,11 +55,11 @@ select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_ESCHE - bool "-> Esche" + bool "-> Esche (HP Chromebook 11MK G9 EE)" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_BURNET - bool "-> Burnet" + bool "-> Burnet (HP Chromebook x360 11MK G3 EE)" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_FENNEL diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 41932d7..f5cb536 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -12,53 +12,53 @@ select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_PHASER - bool "-> Phaser" + bool "-> Phaser (Lenovo 100e/300e/500e Chromebook 2nd Gen (Intel))" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_LICK - bool "-> Lick" + bool "-> Lick (Ideapad 3 Chromebook)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_FLEEX - bool "-> Fleex" + bool "-> Fleex (Dell Chromebook 3100)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_BOBBA - bool "-> Bobba" + bool "-> Bobba (Acer Chromebook 311 / Spin 511)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP - bool "-> Meep" + bool "-> Meep (HP Chromebook x360 11 G2 EE)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_AMPTON - bool "-> Ampton" + bool "-> Ampton (ASUS Chromebook Flip C214)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_CASTA - bool "-> Casta" + bool "-> Bluebird/Casta (Samsung Chromebook 4, 4+)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_BLOOG - bool "-> Bloog" + bool "-> Bloog (HP Chromebook x360 12b, 14a, x360 14b)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index 9ecdb44..fe0dd17 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -14,9 +14,16 @@ bool "-> Nami" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_NAMI + help + The Nami board supports the following devices: + - Acer Chromebook 13 / Spin 13 (Akali) + - Lenovo Yoga Chromebook C630 (Pantheon) + - HP Chromebook x360 14 (Sona) + - HP Chromebook 15 G1 (Syndra) + - Dell Inspiron Chromebook 14 (7460) (Vayne) config BOARD_GOOGLE_NAUTILUS - bool "-> Nautilus (Samsung Chromebook Plus (V2 / LTE))" + bool "-> Nautilus (Samsung Chromebook Plus V2, V2 LTE)" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_NAUTILUS @@ -26,9 +33,13 @@ select VARIANT_SPECIFIC_OPTIONS_NOCTURNE config BOARD_GOOGLE_RAMMUS - bool "-> Rammus (Asus Chromebook C425, Flip C433, Flip C434)" + bool "-> Rammus" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_RAMMUS + help + The Rammus board supports the following devices: + - Asus Chromebook C425 (Leona) + - Asus Chromebook Flip C433/C434 (Shyvana) config BOARD_GOOGLE_SORAKA bool "-> Soraka (HP Chromebook x2)" diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 295675a..84b6c8b 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,7 +1,7 @@ comment "Volteer" config BOARD_GOOGLE_DELBIN - bool "-> Delbin" + bool "-> Delbin (ASUS Chromebook Flip CX5)" select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 @@ -66,13 +66,13 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_VOXEL - bool "-> Voxel" + bool "-> Voxel (Acer Chromebook Spin 713 (CP713-3W))" select BOARD_GOOGLE_BASEBOARD_VOLTEER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_ELEMI - bool "-> Elemi" + bool "-> Elemi (HP Pro c640 G2 Chromebook)" select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_VOEMA @@ -81,13 +81,13 @@ select VARIANT_HAS_MIPI_CAMERA config BOARD_GOOGLE_DROBIT - bool "-> Drobit" + bool "-> Drobit (ASUS Chromebook CX9400)" select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_COPANO - bool "-> Copano" + bool "-> Copano (ASUS Chromebook Flip CX5400)" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 8bc69ab..bac7ee4 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -5,15 +5,15 @@ select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_VILBOZ - bool "-> Vilboz" + bool "-> Vilboz (Lenovo 100e/300e Gen3 AMD)" select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_EZKINIL - bool "-> Ezkinil" + bool "-> Ezkinil (Acer Chromebook Spin 514)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_MORPHIUS - bool "-> Morphius" + bool "-> Morphius (Lenovo ThinkPad C13 Yoga Chromebook)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_TREMBYLE @@ -21,15 +21,15 @@ select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_BERKNIP - bool "-> Berknip" + bool "-> Berknip (HP Pro c645 Chromebook Enterprise)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_WOOMAX - bool "-> Woomax" + bool "-> Woomax (ASUS Chromebook Flip CM5)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_DIRINBOZ - bool "-> Dirinboz" + bool "-> Dirinboz (HP Chromebook 14a-nd0097nr)" select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_SHUBOZ @@ -37,5 +37,5 @@ select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_GUMBOZ - bool "-> Gumboz" + bool "-> Gumboz (HP Chromebook x360 14a)" select BOARD_GOOGLE_BASEBOARD_DALBOZ -- To view, visit https://review.coreboot.org/c/coreboot/+/57392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Gerrit-Change-Number: 57392 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google: Add OEM product names for various boards
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Felix Singer, Matt DeVillier, Tim Wawrzynczak, Nick Vaccaro. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57392 ) Change subject: mb/google: Add OEM product names for various boards ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Gerrit-Change-Number: 57392 Gerrit-PatchSet: 8 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:29:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries Introduce the `smbios_dev_info` devicetree keyword to specify the instance ID and RefDes (Reference Designation) of onboard devices. Example syntax: device pci 1c.0 on # PCIe Port #1 device pci 00.0 on smbios_dev_info 6 end end device pci 1c.1 on # PCIe Port #2 device pci 00.0 on smbios_dev_info 42 "PCIe-PCI Time Machine" end end The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using this syntax to control the generated Type 41 entries. When this option is enabled, Type 41 entries are only autogenerated for devices with a defined instance ID. This avoids having to keep track of which instance IDs have been used for every device class. Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not enabled will result in a build-time error, as the syntax is meaningless in this case. This is done with preprocessor guards around the Type 41 members in `struct device` and the code which uses the guarded members. Although the preprocessor usage isn't particularly elegant, adjusting the devicetree syntax and/or grammar depending on a Kconfig option is probably even worse. Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/Kconfig M src/arch/x86/smbios.c M src/include/device/device.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 10 files changed, 492 insertions(+), 386 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index be269b6..e4ddf0c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -785,6 +785,21 @@ If unsure, say Y. +config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE + bool + depends on ARCH_X86 + help + If enabled, only generate SMBIOS Type 41 entries for PCI devices in + the devicetree for which Type 41 information is provided, e.g. with + the `smbios_dev_info` devicetree syntax. This is useful to manually + assign specific instance IDs to onboard devices irrespective of the + device traversal order. It is assumed that instance IDs for devices + of the same class are unique. + When disabled, coreboot autogenerates SMBIOS Type 41 entries for all + appropriate PCI devices in the devicetree. Instance IDs are assigned + successive numbers from a monotonically increasing counter, with one + counter for each device class. + config SMBIOS_PROVIDED_BY_MOBO bool default n diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index ea42971..c05f905 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1177,30 +1177,55 @@ } } +static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id) +{ +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + *instance_id = dev->smbios_instance_id; + return dev->smbios_instance_id_valid; +#else + static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; + + if (device_type == SMBIOS_DEVICE_TYPE_OTHER || + device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + return false; + + if (device_type > SMBIOS_DEVICE_TYPE_COUNT) + return false; + + *instance_id = type41_inst_cnt[device_type]++; + return true; +#endif +} + +static const char *smbios_get_type41_refdes(struct device *dev) +{ +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + if (dev->smbios_refdes) + return dev->smbios_refdes; +#endif + return get_pci_subclass_name(dev); +} + static int smbios_generate_type41_from_devtree(struct device *dev, int *handle, unsigned long *current) { - static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; - if (dev->path.type != DEVICE_PATH_PCI) return 0; if (!dev->on_mainboard) return 0; - u8 device_type = smbios_get_device_type_from_dev(dev); + const u8 device_type = smbios_get_device_type_from_dev(dev); - if (device_type == SMBIOS_DEVICE_TYPE_OTHER || - device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + u8 instance_id; + + if (!smbios_get_type41_instance_id(dev, device_type, &instance_id)) return 0; - if (device_type > SMBIOS_DEVICE_TYPE_COUNT) - return 0; - - const char *name = get_pci_subclass_name(dev); + const char *name = smbios_get_type41_refdes(dev); return smbios_write_type41(current, handle, name, // name - type41_inst_cnt[device_type]++, // inst + instance_id, // inst 0, // segment dev->bus->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device diff --git a/src/include/device/device.h b/src/include/device/device.h index 8610e0a..237d836 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -148,6 +148,17 @@ u8 smbios_slot_data_width; u8 smbios_slot_length; const char *smbios_slot_designation; + +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + /* + * These fields are intentionally guarded so that attempts to use + * the corresponding devicetree syntax without selecting the Kconfig + * option result in build-time errors. Smaller size is a side effect. + */ + bool smbios_instance_id_valid; + u8 smbios_instance_id; + const char *smbios_refdes; +#endif #endif #endif DEVTREE_CONST void *chip_info; diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 07cb64b..647ec3d 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 49 -#define YY_END_OF_BUFFER 50 +#define YY_NUM_RULES 50 +#define YY_END_OF_BUFFER 51 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,31 +358,31 @@ flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[202] = +static const flex_int16_t yy_accept[210] = { 0, - 0, 0, 50, 48, 1, 3, 48, 48, 48, 43, - 43, 40, 44, 48, 44, 44, 44, 44, 44, 48, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 41, - 48, 1, 3, 48, 0, 48, 48, 0, 2, 43, - 44, 48, 48, 48, 9, 48, 48, 44, 48, 48, - 48, 48, 48, 48, 48, 48, 48, 48, 34, 48, - 48, 48, 48, 48, 15, 48, 48, 48, 48, 48, - 48, 48, 48, 48, 47, 47, 48, 0, 42, 48, - 48, 48, 25, 48, 48, 33, 38, 48, 48, 48, - 48, 48, 22, 48, 48, 32, 48, 48, 48, 16, + 0, 0, 51, 49, 1, 3, 49, 49, 49, 44, + 44, 41, 45, 49, 45, 45, 45, 45, 45, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 42, + 49, 1, 3, 49, 0, 49, 49, 0, 2, 44, + 45, 49, 49, 49, 9, 49, 49, 45, 49, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 34, 49, + 49, 49, 49, 49, 15, 49, 49, 49, 49, 49, + 49, 49, 49, 49, 48, 48, 49, 0, 43, 49, + 49, 49, 25, 49, 49, 33, 38, 49, 49, 49, + 49, 49, 22, 49, 49, 32, 49, 49, 49, 16, - 48, 19, 21, 48, 8, 48, 48, 29, 48, 30, - 7, 48, 0, 45, 48, 4, 48, 48, 48, 48, - 48, 48, 31, 48, 48, 48, 48, 48, 28, 48, - 48, 48, 48, 48, 46, 46, 6, 48, 48, 48, - 12, 48, 48, 48, 48, 48, 23, 48, 48, 14, - 48, 48, 48, 48, 5, 26, 48, 48, 17, 48, - 20, 48, 13, 48, 48, 48, 48, 48, 27, 36, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 10, - 48, 48, 48, 11, 48, 18, 48, 48, 48, 35, - 48, 48, 24, 48, 37, 48, 48, 48, 48, 39, + 49, 19, 21, 49, 8, 49, 49, 29, 49, 30, + 7, 49, 0, 46, 49, 4, 49, 49, 49, 49, + 49, 49, 31, 49, 49, 49, 49, 49, 28, 49, + 49, 49, 49, 49, 47, 47, 6, 49, 49, 49, + 12, 49, 49, 49, 49, 49, 23, 49, 49, 14, + 49, 49, 49, 49, 5, 26, 49, 49, 17, 49, + 20, 49, 13, 49, 49, 49, 49, 49, 27, 36, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 10, + 49, 49, 49, 49, 11, 49, 18, 49, 49, 49, + 49, 35, 49, 49, 49, 24, 49, 49, 37, 49, - 0 + 49, 49, 49, 49, 49, 40, 49, 39, 0 } ; static const YY_CHAR yy_ec[256] = @@ -425,136 +425,140 @@ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[209] = +static const flex_int16_t yy_base[217] = { 0, - 0, 0, 274, 0, 271, 275, 269, 39, 43, 40, - 233, 0, 46, 256, 56, 60, 64, 67, 72, 56, - 244, 74, 251, 39, 70, 59, 246, 77, 233, 0, - 0, 263, 275, 108, 259, 112, 116, 260, 275, 0, - 113, 116, 247, 236, 0, 235, 224, 122, 231, 226, - 236, 234, 238, 225, 227, 231, 231, 225, 231, 216, - 216, 217, 219, 221, 0, 208, 216, 210, 210, 117, - 220, 212, 218, 87, 0, 275, 139, 230, 0, 223, - 216, 202, 215, 205, 212, 0, 0, 202, 208, 205, - 196, 204, 0, 202, 192, 0, 196, 200, 190, 0, + 0, 0, 282, 0, 279, 283, 277, 39, 43, 40, + 241, 0, 46, 264, 56, 60, 64, 67, 72, 56, + 252, 74, 259, 39, 70, 59, 254, 77, 241, 0, + 0, 271, 283, 108, 267, 112, 116, 268, 283, 0, + 113, 116, 255, 244, 0, 243, 232, 122, 239, 234, + 244, 242, 246, 233, 235, 239, 239, 233, 239, 224, + 224, 225, 227, 229, 0, 216, 224, 218, 218, 117, + 228, 220, 226, 87, 0, 283, 139, 238, 0, 231, + 224, 210, 223, 213, 220, 0, 0, 210, 216, 213, + 204, 212, 0, 210, 200, 0, 204, 208, 198, 0, - 193, 0, 0, 199, 0, 191, 190, 0, 181, 0, - 0, 208, 207, 0, 178, 0, 191, 190, 183, 187, - 177, 173, 0, 183, 171, 177, 182, 183, 0, 170, - 177, 164, 167, 156, 0, 275, 0, 168, 172, 164, - 0, 163, 165, 161, 163, 168, 0, 152, 157, 0, - 150, 150, 149, 146, 0, 0, 158, 160, 0, 144, - 161, 147, 0, 154, 158, 139, 139, 146, 0, 0, - 132, 124, 123, 121, 132, 118, 128, 118, 110, 0, - 122, 120, 125, 0, 114, 0, 114, 107, 94, 0, - 82, 81, 0, 83, 0, 74, 67, 37, 31, 0, + 201, 0, 0, 207, 0, 199, 198, 0, 189, 0, + 0, 216, 215, 0, 186, 0, 199, 198, 191, 195, + 185, 181, 0, 191, 179, 185, 190, 191, 0, 178, + 185, 172, 175, 164, 0, 283, 0, 176, 180, 172, + 0, 171, 173, 169, 171, 176, 0, 160, 165, 0, + 158, 158, 157, 154, 0, 0, 166, 168, 0, 152, + 169, 155, 0, 162, 166, 147, 147, 154, 0, 0, + 153, 145, 144, 68, 154, 140, 150, 140, 132, 0, + 136, 130, 128, 133, 0, 122, 0, 116, 122, 125, + 117, 0, 132, 113, 126, 0, 120, 127, 0, 104, - 275, 42, 158, 160, 162, 164, 166, 168 + 106, 94, 78, 65, 37, 0, 31, 0, 283, 42, + 158, 160, 162, 164, 166, 168 } ; -static const flex_int16_t yy_def[209] = +static const flex_int16_t yy_def[217] = { 0, - 201, 1, 201, 202, 201, 201, 202, 203, 204, 202, - 10, 202, 10, 202, 10, 10, 10, 10, 10, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 201, 201, 203, 205, 206, 204, 207, 201, 10, - 10, 10, 202, 202, 202, 202, 202, 10, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 206, 208, 42, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 209, 1, 209, 210, 209, 209, 210, 211, 212, 210, + 10, 210, 10, 210, 10, 10, 10, 10, 10, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 209, 209, 211, 213, 214, 212, 215, 209, 10, + 10, 10, 210, 210, 210, 210, 210, 10, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 209, 214, 216, 42, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 201, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 209, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 209, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, - 0, 201, 201, 201, 201, 201, 201, 201 + 210, 210, 210, 210, 210, 210, 210, 210, 0, 209, + 209, 209, 209, 209, 209, 209 } ; -static const flex_int16_t yy_nxt[316] = +static const flex_int16_t yy_nxt[324] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 15, 13, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4, 25, 26, 4, 27, 28, 4, 29, 4, 4, 4, 4, 30, - 35, 35, 31, 36, 38, 39, 40, 40, 40, 200, + 35, 35, 31, 36, 38, 39, 40, 40, 40, 208, 41, 41, 41, 41, 41, 62, 41, 41, 41, 41, - 41, 41, 41, 41, 41, 63, 41, 41, 41, 199, + 41, 41, 41, 41, 41, 63, 41, 41, 41, 207, 41, 41, 41, 41, 41, 41, 54, 67, 41, 41, - 41, 44, 57, 46, 48, 55, 68, 198, 45, 47, - 69, 64, 49, 197, 51, 50, 52, 65, 196, 66, + 41, 44, 57, 46, 48, 55, 68, 181, 45, 47, + 69, 64, 49, 206, 51, 50, 52, 65, 205, 66, - 195, 58, 59, 71, 110, 60, 72, 111, 53, 35, - 35, 73, 75, 78, 78, 194, 31, 38, 39, 41, - 41, 41, 79, 79, 79, 193, 79, 79, 41, 41, - 41, 192, 79, 79, 79, 79, 79, 79, 105, 106, - 78, 78, 191, 112, 190, 189, 188, 187, 186, 185, - 184, 183, 182, 181, 180, 179, 178, 84, 34, 34, + 182, 58, 59, 71, 110, 60, 72, 111, 53, 35, + 35, 73, 75, 78, 78, 204, 31, 38, 39, 41, + 41, 41, 79, 79, 79, 203, 79, 79, 41, 41, + 41, 202, 79, 79, 79, 79, 79, 79, 105, 106, + 78, 78, 201, 112, 200, 199, 198, 197, 196, 195, + 194, 193, 192, 191, 190, 189, 188, 84, 34, 34, 37, 37, 35, 35, 77, 77, 38, 38, 78, 78, - 177, 176, 175, 174, 173, 172, 171, 170, 169, 168, - 167, 166, 165, 164, 163, 162, 161, 160, 159, 158, - 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, + 187, 186, 185, 184, 183, 180, 179, 178, 177, 176, + 175, 174, 173, 172, 171, 170, 169, 168, 167, 166, + 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, - 147, 146, 145, 144, 143, 142, 141, 140, 139, 138, - 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, - 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, - 117, 116, 115, 114, 113, 109, 108, 107, 104, 103, - 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, - 92, 91, 90, 89, 88, 87, 86, 85, 83, 82, - 81, 80, 39, 76, 32, 74, 70, 61, 56, 43, - 42, 33, 32, 201, 3, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, + 145, 144, 143, 142, 141, 140, 139, 138, 137, 136, + 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, + 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, + 115, 114, 113, 109, 108, 107, 104, 103, 102, 101, + 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, + 90, 89, 88, 87, 86, 85, 83, 82, 81, 80, + 39, 76, 32, 74, 70, 61, 56, 43, 42, 33, + 32, 209, 3, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201 + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209 } ; -static const flex_int16_t yy_chk[316] = +static const flex_int16_t yy_chk[324] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 8, 8, 202, 8, 9, 9, 10, 10, 10, 199, + 8, 8, 210, 8, 9, 9, 10, 10, 10, 207, 10, 10, 13, 13, 13, 24, 10, 10, 10, 10, - 10, 10, 15, 15, 15, 24, 16, 16, 16, 198, + 10, 10, 15, 15, 15, 24, 16, 16, 16, 205, 17, 17, 17, 18, 18, 18, 20, 26, 19, 19, - 19, 15, 22, 16, 17, 20, 26, 197, 15, 16, - 26, 25, 17, 196, 18, 17, 19, 25, 194, 25, + 19, 15, 22, 16, 17, 20, 26, 174, 15, 16, + 26, 25, 17, 204, 18, 17, 19, 25, 203, 25, - 192, 22, 22, 28, 74, 22, 28, 74, 19, 34, - 34, 28, 34, 36, 36, 191, 36, 37, 37, 41, - 41, 41, 42, 42, 42, 189, 42, 42, 48, 48, - 48, 188, 42, 42, 42, 42, 42, 42, 70, 70, - 77, 77, 187, 77, 185, 183, 182, 181, 179, 178, - 177, 176, 175, 174, 173, 172, 171, 48, 203, 203, - 204, 204, 205, 205, 206, 206, 207, 207, 208, 208, - 168, 167, 166, 165, 164, 162, 161, 160, 158, 157, - 154, 153, 152, 151, 149, 148, 146, 145, 144, 143, - 142, 140, 139, 138, 134, 133, 132, 131, 130, 128, + 174, 22, 22, 28, 74, 22, 28, 74, 19, 34, + 34, 28, 34, 36, 36, 202, 36, 37, 37, 41, + 41, 41, 42, 42, 42, 201, 42, 42, 48, 48, + 48, 200, 42, 42, 42, 42, 42, 42, 70, 70, + 77, 77, 198, 77, 197, 195, 194, 193, 191, 190, + 189, 188, 186, 184, 183, 182, 181, 48, 211, 211, + 212, 212, 213, 213, 214, 214, 215, 215, 216, 216, + 179, 178, 177, 176, 175, 173, 172, 171, 168, 167, + 166, 165, 164, 162, 161, 160, 158, 157, 154, 153, + 152, 151, 149, 148, 146, 145, 144, 143, 142, 140, - 127, 126, 125, 124, 122, 121, 120, 119, 118, 117, - 115, 113, 112, 109, 107, 106, 104, 101, 99, 98, - 97, 95, 94, 92, 91, 90, 89, 88, 85, 84, - 83, 82, 81, 80, 78, 73, 72, 71, 69, 68, - 67, 66, 64, 63, 62, 61, 60, 59, 58, 57, - 56, 55, 54, 53, 52, 51, 50, 49, 47, 46, - 44, 43, 38, 35, 32, 29, 27, 23, 21, 14, - 11, 7, 5, 3, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 139, 138, 134, 133, 132, 131, 130, 128, 127, 126, + 125, 124, 122, 121, 120, 119, 118, 117, 115, 113, + 112, 109, 107, 106, 104, 101, 99, 98, 97, 95, + 94, 92, 91, 90, 89, 88, 85, 84, 83, 82, + 81, 80, 78, 73, 72, 71, 69, 68, 67, 66, + 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, + 54, 53, 52, 51, 50, 49, 47, 46, 44, 43, + 38, 35, 32, 29, 27, 23, 21, 14, 11, 7, + 5, 3, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201 + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209 } ; static yy_state_type yy_last_accepting_state; @@ -819,13 +823,13 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 275 ); + while ( yy_base[yy_current_state] != 283 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -1009,15 +1013,15 @@ YY_BREAK case 40: YY_RULE_SETUP -{return(EQUALS);} +{return(SMBIOS_DEV_INFO);} YY_BREAK case 41: YY_RULE_SETUP -{return(PIPE);} +{return(EQUALS);} YY_BREAK case 42: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(PIPE);} YY_BREAK case 43: YY_RULE_SETUP @@ -1029,12 +1033,11 @@ YY_BREAK case 45: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 46: -/* rule 46 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 47: /* rule 47 can match eol */ @@ -1042,10 +1045,15 @@ {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 48: +/* rule 48 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 49: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 49: +case 50: YY_RULE_SETUP ECHO; YY_BREAK @@ -1345,7 +1353,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1373,11 +1381,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 201); + yy_is_jam = (yy_current_state == 209); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 685da9d..1de98d4 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1023,6 +1023,25 @@ dev->smbios_slot_designation = designation; } +void add_smbios_dev_info(struct bus *bus, long instance_id, const char *refdes) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'dev_info' only allowed for PCI devices\n"); + exit(1); + } + + if (instance_id < 0 || instance_id > UINT8_MAX) { + printf("ERROR: SMBIOS dev info instance ID '%ld' out of range\n", instance_id); + exit(1); + } + + dev->smbios_instance_id_valid = 1; + dev->smbios_instance_id = (unsigned int)instance_id; + dev->smbios_refdes = refdes; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -1135,6 +1154,14 @@ fprintf(fil, "\t.smbios_slot_length = %s,\n", ptr->smbios_slot_length); + /* Fill in SMBIOS type41 fields */ + if (ptr->smbios_instance_id_valid) { + fprintf(fil, "\t.smbios_instance_id_valid = true,\n"); + fprintf(fil, "\t.smbios_instance_id = %u,\n", ptr->smbios_instance_id); + if (ptr->smbios_refdes) + fprintf(fil, "\t.smbios_refdes = \"%s\",\n", ptr->smbios_refdes); + } + fprintf(fil, "#endif\n"); fprintf(fil, "#endif\n"); } diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index e6bd5aa..5b50cc0 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -177,6 +177,11 @@ /* SMBIOS slot length */ char *smbios_slot_length; + /* SMBIOS type41 fields */ + int smbios_instance_id_valid; + unsigned int smbios_instance_id; + const char *smbios_refdes; + /* List of field+option to probe. */ struct fw_config_probe *probe; }; @@ -203,6 +208,8 @@ void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, char *data_width); +void add_smbios_dev_info(struct bus *bus, long instance_id, const char *refdes); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 1111267..0997ff6 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -47,6 +47,7 @@ subsystemid {return(SUBSYSTEMID);} end {return(END);} smbios_slot_desc {return(SLOT_DESC);} +smbios_dev_info {return(SMBIOS_DEV_INFO);} = {return(EQUALS);} \| {return(PIPE);} 0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index b07adcb..c319a79 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.7.6. */ +/* A Bison parser, made by GNU Bison 3.8.1. */ /* Bison implementation for Yacc-like parsers in C @@ -46,10 +46,10 @@ USER NAME SPACE" below. */ /* Identify Bison output, and Bison version. */ -#define YYBISON 30706 +#define YYBISON 30801 /* Bison version string. */ -#define YYBISON_VERSION "3.7.6" +#define YYBISON_VERSION "3.8.1" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -138,54 +138,56 @@ YYSYMBOL_IRQ = 25, /* IRQ */ YYSYMBOL_DRQ = 26, /* DRQ */ YYSYMBOL_SLOT_DESC = 27, /* SLOT_DESC */ - YYSYMBOL_IO = 28, /* IO */ - YYSYMBOL_NUMBER = 29, /* NUMBER */ - YYSYMBOL_SUBSYSTEMID = 30, /* SUBSYSTEMID */ - YYSYMBOL_INHERIT = 31, /* INHERIT */ - YYSYMBOL_IOAPIC_IRQ = 32, /* IOAPIC_IRQ */ - YYSYMBOL_IOAPIC = 33, /* IOAPIC */ - YYSYMBOL_PCIINT = 34, /* PCIINT */ - YYSYMBOL_GENERIC = 35, /* GENERIC */ - YYSYMBOL_SPI = 36, /* SPI */ - YYSYMBOL_USB = 37, /* USB */ - YYSYMBOL_MMIO = 38, /* MMIO */ - YYSYMBOL_GPIO = 39, /* GPIO */ - YYSYMBOL_FW_CONFIG_TABLE = 40, /* FW_CONFIG_TABLE */ - YYSYMBOL_FW_CONFIG_FIELD = 41, /* FW_CONFIG_FIELD */ - YYSYMBOL_FW_CONFIG_OPTION = 42, /* FW_CONFIG_OPTION */ - YYSYMBOL_FW_CONFIG_PROBE = 43, /* FW_CONFIG_PROBE */ - YYSYMBOL_PIPE = 44, /* PIPE */ - YYSYMBOL_YYACCEPT = 45, /* $accept */ - YYSYMBOL_devtree = 46, /* devtree */ - YYSYMBOL_chipchild_nondev = 47, /* chipchild_nondev */ - YYSYMBOL_chipchild = 48, /* chipchild */ - YYSYMBOL_chipchildren = 49, /* chipchildren */ - YYSYMBOL_chipchildren_dev = 50, /* chipchildren_dev */ - YYSYMBOL_devicechildren = 51, /* devicechildren */ - YYSYMBOL_chip = 52, /* chip */ - YYSYMBOL_53_1 = 53, /* @1 */ - YYSYMBOL_device = 54, /* device */ - YYSYMBOL_55_2 = 55, /* @2 */ - YYSYMBOL_56_3 = 56, /* @3 */ - YYSYMBOL_alias = 57, /* alias */ - YYSYMBOL_status = 58, /* status */ - YYSYMBOL_resource = 59, /* resource */ - YYSYMBOL_reference = 60, /* reference */ - YYSYMBOL_registers = 61, /* registers */ - YYSYMBOL_subsystemid = 62, /* subsystemid */ - YYSYMBOL_ioapic_irq = 63, /* ioapic_irq */ - YYSYMBOL_smbios_slot_desc = 64, /* smbios_slot_desc */ - YYSYMBOL_fw_config_table = 65, /* fw_config_table */ - YYSYMBOL_fw_config_table_children = 66, /* fw_config_table_children */ - YYSYMBOL_fw_config_field_children = 67, /* fw_config_field_children */ - YYSYMBOL_fw_config_field_bits = 68, /* fw_config_field_bits */ - YYSYMBOL_fw_config_field_bits_repeating = 69, /* fw_config_field_bits_repeating */ - YYSYMBOL_fw_config_field = 70, /* fw_config_field */ - YYSYMBOL_71_4 = 71, /* $@4 */ - YYSYMBOL_72_5 = 72, /* $@5 */ - YYSYMBOL_73_6 = 73, /* $@6 */ - YYSYMBOL_fw_config_option = 74, /* fw_config_option */ - YYSYMBOL_fw_config_probe = 75 /* fw_config_probe */ + YYSYMBOL_SMBIOS_DEV_INFO = 28, /* SMBIOS_DEV_INFO */ + YYSYMBOL_IO = 29, /* IO */ + YYSYMBOL_NUMBER = 30, /* NUMBER */ + YYSYMBOL_SUBSYSTEMID = 31, /* SUBSYSTEMID */ + YYSYMBOL_INHERIT = 32, /* INHERIT */ + YYSYMBOL_IOAPIC_IRQ = 33, /* IOAPIC_IRQ */ + YYSYMBOL_IOAPIC = 34, /* IOAPIC */ + YYSYMBOL_PCIINT = 35, /* PCIINT */ + YYSYMBOL_GENERIC = 36, /* GENERIC */ + YYSYMBOL_SPI = 37, /* SPI */ + YYSYMBOL_USB = 38, /* USB */ + YYSYMBOL_MMIO = 39, /* MMIO */ + YYSYMBOL_GPIO = 40, /* GPIO */ + YYSYMBOL_FW_CONFIG_TABLE = 41, /* FW_CONFIG_TABLE */ + YYSYMBOL_FW_CONFIG_FIELD = 42, /* FW_CONFIG_FIELD */ + YYSYMBOL_FW_CONFIG_OPTION = 43, /* FW_CONFIG_OPTION */ + YYSYMBOL_FW_CONFIG_PROBE = 44, /* FW_CONFIG_PROBE */ + YYSYMBOL_PIPE = 45, /* PIPE */ + YYSYMBOL_YYACCEPT = 46, /* $accept */ + YYSYMBOL_devtree = 47, /* devtree */ + YYSYMBOL_chipchild_nondev = 48, /* chipchild_nondev */ + YYSYMBOL_chipchild = 49, /* chipchild */ + YYSYMBOL_chipchildren = 50, /* chipchildren */ + YYSYMBOL_chipchildren_dev = 51, /* chipchildren_dev */ + YYSYMBOL_devicechildren = 52, /* devicechildren */ + YYSYMBOL_chip = 53, /* chip */ + YYSYMBOL_54_1 = 54, /* @1 */ + YYSYMBOL_device = 55, /* device */ + YYSYMBOL_56_2 = 56, /* @2 */ + YYSYMBOL_57_3 = 57, /* @3 */ + YYSYMBOL_alias = 58, /* alias */ + YYSYMBOL_status = 59, /* status */ + YYSYMBOL_resource = 60, /* resource */ + YYSYMBOL_reference = 61, /* reference */ + YYSYMBOL_registers = 62, /* registers */ + YYSYMBOL_subsystemid = 63, /* subsystemid */ + YYSYMBOL_ioapic_irq = 64, /* ioapic_irq */ + YYSYMBOL_smbios_slot_desc = 65, /* smbios_slot_desc */ + YYSYMBOL_smbios_dev_info = 66, /* smbios_dev_info */ + YYSYMBOL_fw_config_table = 67, /* fw_config_table */ + YYSYMBOL_fw_config_table_children = 68, /* fw_config_table_children */ + YYSYMBOL_fw_config_field_children = 69, /* fw_config_field_children */ + YYSYMBOL_fw_config_field_bits = 70, /* fw_config_field_bits */ + YYSYMBOL_fw_config_field_bits_repeating = 71, /* fw_config_field_bits_repeating */ + YYSYMBOL_fw_config_field = 72, /* fw_config_field */ + YYSYMBOL_73_4 = 73, /* $@4 */ + YYSYMBOL_74_5 = 74, /* $@5 */ + YYSYMBOL_75_6 = 75, /* $@6 */ + YYSYMBOL_fw_config_option = 76, /* fw_config_option */ + YYSYMBOL_fw_config_probe = 77 /* fw_config_probe */ }; typedef enum yysymbol_kind_t yysymbol_kind_t; @@ -343,12 +345,18 @@ # define YY_USE(E) /* empty */ #endif -#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ /* Suppress an incorrect diagnostic about yylval being uninitialized. */ -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ +#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ +# if __GNUC__ * 100 + __GNUC_MINOR__ < 407 +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") +# else +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") +# endif # define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else @@ -507,19 +515,19 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 90 +#define YYLAST 98 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 45 +#define YYNTOKENS 46 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 31 +#define YYNNTS 32 /* YYNRULES -- Number of rules. */ -#define YYNRULES 57 +#define YYNRULES 60 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 101 +#define YYNSTATES 105 /* YYMAXUTOK -- Last valid token kind. */ -#define YYMAXUTOK 299 +#define YYMAXUTOK 300 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -562,19 +570,21 @@ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37, 38, 39, 40, 41, 42, 43, 44 + 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, + 45 }; #if YYDEBUG - /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ +/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { 0, 26, 26, 26, 26, 29, 29, 29, 30, 30, 31, 31, 32, 32, 34, 34, 34, 34, 34, 34, - 34, 34, 34, 36, 36, 45, 45, 53, 53, 61, - 63, 67, 67, 69, 72, 75, 78, 81, 84, 87, - 90, 93, 97, 100, 100, 103, 103, 106, 112, 112, - 115, 114, 119, 119, 127, 127, 133, 137 + 34, 34, 34, 34, 36, 36, 45, 45, 53, 53, + 61, 63, 67, 67, 69, 72, 75, 78, 81, 84, + 87, 90, 93, 96, 99, 103, 106, 106, 109, 109, + 112, 118, 118, 121, 120, 125, 125, 133, 133, 139, + 143 }; #endif @@ -594,17 +604,18 @@ "REGISTER", "ALIAS", "REFERENCE", "ASSOCIATION", "BOOL", "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", - "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", - "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "GPIO", - "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", + "SLOT_DESC", "SMBIOS_DEV_INFO", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", + "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", + "GPIO", "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", "FW_CONFIG_PROBE", "PIPE", "$accept", "devtree", "chipchild_nondev", "chipchild", "chipchildren", "chipchildren_dev", "devicechildren", "chip", "@1", "device", "@2", "@3", "alias", "status", "resource", "reference", "registers", "subsystemid", "ioapic_irq", - "smbios_slot_desc", "fw_config_table", "fw_config_table_children", - "fw_config_field_children", "fw_config_field_bits", - "fw_config_field_bits_repeating", "fw_config_field", "$@4", "$@5", "$@6", - "fw_config_option", "fw_config_probe", YY_NULLPTR + "smbios_slot_desc", "smbios_dev_info", "fw_config_table", + "fw_config_table_children", "fw_config_field_children", + "fw_config_field_bits", "fw_config_field_bits_repeating", + "fw_config_field", "$@4", "$@5", "$@6", "fw_config_option", + "fw_config_probe", YY_NULLPTR }; static const char * @@ -614,20 +625,7 @@ } #endif -#ifdef YYPRINT -/* YYTOKNUM[NUM] -- (External) token number corresponding to the - (internal) symbol number NUM (which must be that of a token). */ -static const yytype_int16 yytoknum[] = -{ - 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, - 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, - 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, - 295, 296, 297, 298, 299 -}; -#endif - -#define YYPACT_NINF (-61) +#define YYPACT_NINF (-45) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -637,127 +635,129 @@ #define yytable_value_is_error(Yyn) \ 0 - /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing - STATE-NUM. */ +/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ static const yytype_int8 yypact[] = { - -61, 12, -61, -7, -61, -61, -61, -61, -12, 46, - -61, 8, -61, 14, 11, 18, 46, 23, -61, -61, - -61, -61, 16, 24, 17, 25, 34, -61, -61, 46, - 26, 10, -61, 13, 51, 41, 42, -61, -61, -61, - -61, -61, 31, -61, -3, -61, -61, -61, 44, 13, - -61, -61, 2, 26, 10, -61, -61, 45, -61, -61, - -61, -61, -61, -61, 6, 35, 0, -61, -61, -61, - 37, -61, 50, 39, 40, 53, -61, -61, -61, -61, - -61, -61, -61, -61, 4, 48, 54, 43, 47, 56, - -61, 49, 57, 55, 58, -61, -61, 59, -61, -61, - -61 + -45, 6, -45, 4, -45, -45, -45, -45, -12, 45, + -45, 15, -45, 11, 17, 18, 45, -3, -45, -45, + -45, -45, 16, 34, 23, 14, 46, -45, -45, 45, + 25, 19, -45, 10, 51, 42, 43, -45, -45, -45, + -45, -45, 31, -45, -7, -45, -45, -45, 49, 10, + -45, -45, -6, 25, 19, -45, -45, 50, -45, -45, + -45, -45, -45, -45, -2, 32, 0, -45, -45, -45, + 33, -45, 52, 38, 40, 41, 55, -45, -45, -45, + -45, -45, -45, -45, -45, -45, 12, 58, 57, 59, + 47, 44, 61, -45, 53, 63, -45, 54, 60, -45, + -45, 64, -45, -45, -45 }; - /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. - Performed when YYTABLE does not specify something else to do. Zero - means the default is an error. */ +/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE does not specify something else to do. Zero + means the default is an error. */ static const yytype_int8 yydefact[] = { - 2, 0, 1, 0, 44, 3, 4, 23, 0, 0, - 42, 0, 43, 0, 0, 0, 0, 0, 5, 11, - 7, 6, 54, 0, 0, 0, 0, 13, 24, 12, - 52, 49, 46, 0, 29, 0, 0, 9, 10, 8, - 47, 46, 0, 50, 0, 31, 32, 27, 0, 0, - 35, 34, 0, 0, 49, 46, 55, 0, 45, 22, - 30, 25, 53, 48, 0, 0, 0, 22, 51, 56, - 0, 28, 0, 0, 0, 0, 15, 14, 16, 20, - 17, 18, 19, 21, 0, 0, 0, 0, 0, 0, - 26, 0, 41, 36, 0, 57, 33, 40, 37, 38, - 39 + 2, 0, 1, 0, 47, 3, 4, 24, 0, 0, + 45, 0, 46, 0, 0, 0, 0, 0, 5, 11, + 7, 6, 57, 0, 0, 0, 0, 13, 25, 12, + 55, 52, 49, 0, 30, 0, 0, 9, 10, 8, + 50, 49, 0, 53, 0, 32, 33, 28, 0, 0, + 36, 35, 0, 0, 52, 49, 58, 0, 48, 23, + 31, 26, 56, 51, 0, 0, 0, 23, 54, 59, + 0, 29, 0, 0, 0, 0, 0, 15, 14, 16, + 21, 17, 18, 19, 20, 22, 0, 0, 0, 44, + 0, 0, 0, 27, 0, 42, 43, 37, 0, 60, + 34, 41, 38, 39, 40 }; - /* YYPGOTO[NTERM-NUM]. */ +/* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -61, -61, 60, -61, -61, 61, 15, -1, -61, -28, - -61, -61, -61, 30, -61, -61, -60, -61, -61, -61, - -61, -61, -22, 33, 36, -61, -61, -61, -61, -61, - -61 + -45, -45, 62, -45, -45, 66, 8, -1, -45, -28, + -45, -45, -45, 35, -45, -45, -44, -45, -45, -45, + -45, -45, -45, -31, 56, 39, -45, -45, -45, -45, + -45, -45 }; - /* YYDEFGOTO[NTERM-NUM]. */ +/* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { 0, 1, 16, 38, 29, 17, 66, 18, 9, 19, - 67, 59, 49, 47, 78, 20, 21, 80, 81, 82, - 6, 8, 44, 31, 43, 12, 55, 41, 32, 58, - 83 + 67, 59, 49, 47, 79, 20, 21, 81, 82, 83, + 84, 6, 8, 44, 31, 43, 12, 55, 41, 32, + 58, 85 }; - /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If - positive, shift that token. If negative, reduce the rule whose - number is the opposite. If YYTABLE_NINF, syntax error. */ +/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule whose + number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 5, 39, 10, 3, 13, 14, 79, 3, 13, 14, - 7, 56, 2, 70, 71, 3, 62, 70, 90, 52, - 68, 23, 45, 46, 79, 22, 24, 72, 25, 11, - 73, 72, 74, 64, 73, 26, 74, 28, 77, 57, - 35, 33, 36, 75, 57, 30, 34, 75, 57, 3, - 13, 14, 4, 15, 42, 40, 77, 48, 50, 51, - 53, 60, 65, 91, 69, 76, 85, 86, 87, 88, - 89, 92, 93, 95, 97, 54, 100, 27, 96, 61, - 0, 94, 84, 76, 0, 0, 98, 99, 0, 37, - 63 + 5, 39, 10, 3, 13, 14, 2, 56, 62, 3, + 52, 28, 68, 70, 71, 3, 13, 14, 23, 45, + 46, 7, 80, 24, 64, 70, 93, 72, 73, 35, + 11, 74, 22, 75, 25, 26, 57, 57, 78, 72, + 73, 57, 80, 74, 76, 75, 30, 4, 3, 13, + 14, 33, 15, 34, 36, 40, 76, 48, 78, 50, + 51, 53, 69, 87, 42, 77, 60, 65, 89, 88, + 90, 91, 92, 94, 95, 86, 96, 97, 99, 98, + 101, 104, 27, 100, 61, 77, 102, 0, 0, 0, + 103, 37, 0, 63, 0, 0, 0, 0, 54 }; static const yytype_int8 yycheck[] = { - 1, 29, 14, 3, 4, 5, 66, 3, 4, 5, - 17, 14, 0, 13, 14, 3, 14, 13, 14, 41, - 14, 7, 9, 10, 84, 17, 12, 27, 17, 41, - 30, 27, 32, 55, 30, 17, 32, 14, 66, 42, - 15, 17, 8, 43, 42, 29, 29, 43, 42, 3, - 4, 5, 40, 7, 44, 29, 84, 6, 17, 17, - 29, 17, 17, 15, 29, 66, 29, 17, 29, 29, - 17, 17, 29, 17, 17, 42, 17, 16, 29, 49, - -1, 34, 67, 84, -1, -1, 31, 29, -1, 29, - 54 + 1, 29, 14, 3, 4, 5, 0, 14, 14, 3, + 41, 14, 14, 13, 14, 3, 4, 5, 7, 9, + 10, 17, 66, 12, 55, 13, 14, 27, 28, 15, + 42, 31, 17, 33, 17, 17, 43, 43, 66, 27, + 28, 43, 86, 31, 44, 33, 30, 41, 3, 4, + 5, 17, 7, 30, 8, 30, 44, 6, 86, 17, + 17, 30, 30, 30, 45, 66, 17, 17, 30, 17, + 30, 30, 17, 15, 17, 67, 17, 30, 17, 35, + 17, 17, 16, 30, 49, 86, 32, -1, -1, -1, + 30, 29, -1, 54, -1, -1, -1, -1, 42 }; - /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing - symbol of state STATE-NUM. */ +/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of + state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 46, 0, 3, 40, 52, 65, 17, 66, 53, - 14, 41, 70, 4, 5, 7, 47, 50, 52, 54, - 60, 61, 17, 7, 12, 17, 17, 50, 14, 49, - 29, 68, 73, 17, 29, 15, 8, 47, 48, 54, - 29, 72, 44, 69, 67, 9, 10, 58, 6, 57, - 17, 17, 67, 29, 68, 71, 14, 42, 74, 56, - 17, 58, 14, 69, 67, 17, 51, 55, 14, 29, - 13, 14, 27, 30, 32, 43, 52, 54, 59, 61, - 62, 63, 64, 75, 51, 29, 17, 29, 29, 17, - 14, 15, 17, 29, 34, 17, 29, 17, 31, 29, - 17 + 0, 47, 0, 3, 41, 53, 67, 17, 68, 54, + 14, 42, 72, 4, 5, 7, 48, 51, 53, 55, + 61, 62, 17, 7, 12, 17, 17, 51, 14, 50, + 30, 70, 75, 17, 30, 15, 8, 48, 49, 55, + 30, 74, 45, 71, 69, 9, 10, 59, 6, 58, + 17, 17, 69, 30, 70, 73, 14, 43, 76, 57, + 17, 59, 14, 71, 69, 17, 52, 56, 14, 30, + 13, 14, 27, 28, 31, 33, 44, 53, 55, 60, + 62, 63, 64, 65, 66, 77, 52, 30, 17, 30, + 30, 30, 17, 14, 15, 17, 17, 30, 35, 17, + 30, 17, 32, 30, 17 }; - /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ static const yytype_int8 yyr1[] = { - 0, 45, 46, 46, 46, 47, 47, 47, 48, 48, - 49, 49, 50, 50, 51, 51, 51, 51, 51, 51, - 51, 51, 51, 53, 52, 55, 54, 56, 54, 57, - 57, 58, 58, 59, 60, 61, 62, 62, 63, 64, - 64, 64, 65, 66, 66, 67, 67, 68, 69, 69, - 71, 70, 72, 70, 73, 70, 74, 75 + 0, 46, 47, 47, 47, 48, 48, 48, 49, 49, + 50, 50, 51, 51, 52, 52, 52, 52, 52, 52, + 52, 52, 52, 52, 54, 53, 56, 55, 57, 55, + 58, 58, 59, 59, 60, 61, 62, 63, 63, 64, + 65, 65, 65, 66, 66, 67, 68, 68, 69, 69, + 70, 71, 71, 73, 72, 74, 72, 75, 72, 76, + 77 }; - /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ +/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ static const yytype_int8 yyr2[] = { 0, 2, 0, 2, 2, 1, 1, 1, 1, 1, 2, 0, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 0, 0, 5, 0, 8, 0, 7, 0, - 2, 1, 1, 4, 4, 4, 3, 4, 4, 5, - 4, 3, 3, 2, 0, 2, 0, 2, 3, 0, - 0, 7, 0, 6, 0, 5, 3, 3 + 2, 2, 2, 0, 0, 5, 0, 8, 0, 7, + 0, 2, 1, 1, 4, 4, 4, 3, 4, 4, + 5, 4, 3, 3, 2, 3, 2, 0, 2, 0, + 2, 3, 0, 0, 7, 0, 6, 0, 5, 3, + 3 }; @@ -769,6 +769,7 @@ #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab +#define YYNOMEM goto yyexhaustedlab #define YYRECOVERING() (!!yyerrstatus) @@ -809,10 +810,7 @@ YYFPRINTF Args; \ } while (0) -/* This macro is provided for backward compatibility. */ -# ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -# endif + # define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ @@ -839,10 +837,6 @@ YY_USE (yyoutput); if (!yyvaluep) return; -# ifdef YYPRINT - if (yykind < YYNTOKENS) - YYPRINT (yyo, yytoknum[yykind], *yyvaluep); -# endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN YY_USE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END @@ -1027,6 +1021,7 @@ YYDPRINTF ((stderr, "Starting parse\n")); yychar = YYEMPTY; /* Cause a token to be read. */ + goto yysetstate; @@ -1052,7 +1047,7 @@ if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE - goto yyexhaustedlab; + YYNOMEM; #else { /* Get the current used size of the three stacks, in elements. */ @@ -1080,7 +1075,7 @@ # else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) - goto yyexhaustedlab; + YYNOMEM; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; @@ -1091,7 +1086,7 @@ YY_CAST (union yyalloc *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) - goto yyexhaustedlab; + YYNOMEM; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); # undef YYSTACK_RELOCATE @@ -1113,6 +1108,7 @@ } #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ + if (yystate == YYFINAL) YYACCEPT; @@ -1228,7 +1224,7 @@ { cur_parent = root_parent; } break; - case 23: /* @1: %empty */ + case 24: /* @1: %empty */ { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); @@ -1236,105 +1232,113 @@ } break; - case 24: /* chip: CHIP STRING @1 chipchildren_dev END */ + case 25: /* chip: CHIP STRING @1 chipchildren_dev END */ { cur_chip_instance = chip_dequeue_tail(); } break; - case 25: /* @2: %empty */ + case 26: /* @2: %empty */ { (yyval.dev) = new_device_raw(cur_parent, cur_chip_instance, (yyvsp[-3].number), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 26: /* device: DEVICE BUS NUMBER alias status @2 devicechildren END */ + case 27: /* device: DEVICE BUS NUMBER alias status @2 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 27: /* @3: %empty */ + case 28: /* @3: %empty */ { (yyval.dev) = new_device_reference(cur_parent, cur_chip_instance, (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 28: /* device: DEVICE REFERENCE STRING status @3 devicechildren END */ + case 29: /* device: DEVICE REFERENCE STRING status @3 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 29: /* alias: %empty */ + case 30: /* alias: %empty */ { (yyval.string) = NULL; } break; - case 30: /* alias: ALIAS STRING */ + case 31: /* alias: ALIAS STRING */ { (yyval.string) = (yyvsp[0].string); } break; - case 33: /* resource: RESOURCE NUMBER EQUALS NUMBER */ + case 34: /* resource: RESOURCE NUMBER EQUALS NUMBER */ { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 34: /* reference: REFERENCE STRING ASSOCIATION STRING */ + case 35: /* reference: REFERENCE STRING ASSOCIATION STRING */ { add_reference(cur_chip_instance, (yyvsp[0].string), (yyvsp[-2].string)); } break; - case 35: /* registers: REGISTER STRING EQUALS STRING */ + case 36: /* registers: REGISTER STRING EQUALS STRING */ { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 36: /* subsystemid: SUBSYSTEMID NUMBER NUMBER */ + case 37: /* subsystemid: SUBSYSTEMID NUMBER NUMBER */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 37: /* subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT */ + case 38: /* subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 38: /* ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER */ + case 39: /* ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER */ { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; - case 39: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING */ + case 40: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; - case 40: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING */ + case 41: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } break; - case 41: /* smbios_slot_desc: SLOT_DESC STRING STRING */ + case 42: /* smbios_slot_desc: SLOT_DESC STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; - case 42: /* fw_config_table: FW_CONFIG_TABLE fw_config_table_children END */ + case 43: /* smbios_dev_info: SMBIOS_DEV_INFO NUMBER STRING */ + { add_smbios_dev_info(cur_parent, strtol((yyvsp[-1].string), NULL, 0), (yyvsp[0].string)); } + break; + + case 44: /* smbios_dev_info: SMBIOS_DEV_INFO NUMBER */ + { add_smbios_dev_info(cur_parent, strtol((yyvsp[0].string), NULL, 0), NULL); } + break; + + case 45: /* fw_config_table: FW_CONFIG_TABLE fw_config_table_children END */ { } break; - case 47: /* fw_config_field_bits: NUMBER NUMBER */ + case 50: /* fw_config_field_bits: NUMBER NUMBER */ { append_fw_config_bits(&cur_bits, strtoul((yyvsp[-1].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; - case 50: /* $@4: %empty */ + case 53: /* $@4: %empty */ { cur_field = new_fw_config_field((yyvsp[-2].string), cur_bits); } break; - case 51: /* fw_config_field: FW_CONFIG_FIELD STRING fw_config_field_bits fw_config_field_bits_repeating $@4 fw_config_field_children END */ + case 54: /* fw_config_field: FW_CONFIG_FIELD STRING fw_config_field_bits fw_config_field_bits_repeating $@4 fw_config_field_children END */ { cur_bits = NULL; } break; - case 52: /* $@5: %empty */ + case 55: /* $@5: %empty */ { cur_bits = NULL; append_fw_config_bits(&cur_bits, strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); @@ -1342,25 +1346,25 @@ } break; - case 53: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER $@5 fw_config_field_children END */ + case 56: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER $@5 fw_config_field_children END */ { cur_bits = NULL; } break; - case 54: /* $@6: %empty */ + case 57: /* $@6: %empty */ { cur_field = get_fw_config_field((yyvsp[0].string)); } break; - case 55: /* fw_config_field: FW_CONFIG_FIELD STRING $@6 fw_config_field_children END */ + case 58: /* fw_config_field: FW_CONFIG_FIELD STRING $@6 fw_config_field_children END */ { cur_bits = NULL; } break; - case 56: /* fw_config_option: FW_CONFIG_OPTION STRING NUMBER */ + case 59: /* fw_config_option: FW_CONFIG_OPTION STRING NUMBER */ { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoull((yyvsp[0].string), NULL, 0)); } break; - case 57: /* fw_config_probe: FW_CONFIG_PROBE STRING STRING */ + case 60: /* fw_config_probe: FW_CONFIG_PROBE STRING STRING */ { add_fw_config_probe(cur_parent, (yyvsp[-1].string), (yyvsp[0].string)); } break; @@ -1446,6 +1450,7 @@ label yyerrorlab therefore never appears in user code. */ if (0) YYERROR; + ++yynerrs; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ @@ -1506,7 +1511,7 @@ `-------------------------------------*/ yyacceptlab: yyresult = 0; - goto yyreturn; + goto yyreturnlab; /*-----------------------------------. @@ -1514,24 +1519,22 @@ `-----------------------------------*/ yyabortlab: yyresult = 1; - goto yyreturn; + goto yyreturnlab; -#if !defined yyoverflow -/*-------------------------------------------------. -| yyexhaustedlab -- memory exhaustion comes here. | -`-------------------------------------------------*/ +/*-----------------------------------------------------------. +| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | +`-----------------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - goto yyreturn; -#endif + goto yyreturnlab; -/*-------------------------------------------------------. -| yyreturn -- parsing is finished, clean up and return. | -`-------------------------------------------------------*/ -yyreturn: +/*----------------------------------------------------------. +| yyreturnlab -- parsing is finished, clean up and return. | +`----------------------------------------------------------*/ +yyreturnlab: if (yychar != YYEMPTY) { /* Make sure we have latest lookahead translation. See comments at diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 1d96a35..fb14adc 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.7.6. */ +/* A Bison parser, made by GNU Bison 3.8.1. */ /* Bison interface for Yacc-like parsers in C @@ -35,8 +35,8 @@ especially those whose name start with YY_ or yy_. They are private implementation details that can be changed or removed. */ -#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -79,23 +79,24 @@ IRQ = 280, /* IRQ */ DRQ = 281, /* DRQ */ SLOT_DESC = 282, /* SLOT_DESC */ - IO = 283, /* IO */ - NUMBER = 284, /* NUMBER */ - SUBSYSTEMID = 285, /* SUBSYSTEMID */ - INHERIT = 286, /* INHERIT */ - IOAPIC_IRQ = 287, /* IOAPIC_IRQ */ - IOAPIC = 288, /* IOAPIC */ - PCIINT = 289, /* PCIINT */ - GENERIC = 290, /* GENERIC */ - SPI = 291, /* SPI */ - USB = 292, /* USB */ - MMIO = 293, /* MMIO */ - GPIO = 294, /* GPIO */ - FW_CONFIG_TABLE = 295, /* FW_CONFIG_TABLE */ - FW_CONFIG_FIELD = 296, /* FW_CONFIG_FIELD */ - FW_CONFIG_OPTION = 297, /* FW_CONFIG_OPTION */ - FW_CONFIG_PROBE = 298, /* FW_CONFIG_PROBE */ - PIPE = 299 /* PIPE */ + SMBIOS_DEV_INFO = 283, /* SMBIOS_DEV_INFO */ + IO = 284, /* IO */ + NUMBER = 285, /* NUMBER */ + SUBSYSTEMID = 286, /* SUBSYSTEMID */ + INHERIT = 287, /* INHERIT */ + IOAPIC_IRQ = 288, /* IOAPIC_IRQ */ + IOAPIC = 289, /* IOAPIC */ + PCIINT = 290, /* PCIINT */ + GENERIC = 291, /* GENERIC */ + SPI = 292, /* SPI */ + USB = 293, /* USB */ + MMIO = 294, /* MMIO */ + GPIO = 295, /* GPIO */ + FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ + FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ + FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ + FW_CONFIG_PROBE = 299, /* FW_CONFIG_PROBE */ + PIPE = 300 /* PIPE */ }; typedef enum yytokentype yytoken_kind_t; #endif @@ -120,6 +121,8 @@ extern YYSTYPE yylval; + int yyparse (void); -#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ + +#endif /* !YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index da6d97b..1b611e4 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -21,7 +21,7 @@ uint64_t number; } -%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO GPIO FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE PIPE +%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC SMBIOS_DEV_INFO IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO GPIO FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE PIPE %% devtree: { cur_parent = root_parent; } | devtree chip | devtree fw_config_table; @@ -31,7 +31,7 @@ chipchildren: chipchildren chipchild | /* empty */ ; chipchildren_dev: device chipchildren | chipchild_nondev chipchildren_dev; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | devicechildren fw_config_probe | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren smbios_dev_info | devicechildren registers | devicechildren fw_config_probe | /* empty */ ; chip: CHIP STRING /* == path */ { $<chip_instance>$ = new_chip_instance($<string>2); @@ -93,6 +93,12 @@ smbios_slot_desc: SLOT_DESC STRING STRING { add_slot_desc(cur_parent, $<string>2, $<string>3, NULL, NULL); }; +smbios_dev_info: SMBIOS_DEV_INFO NUMBER STRING + { add_smbios_dev_info(cur_parent, strtol($<string>2, NULL, 0), $<string>3); }; + +smbios_dev_info: SMBIOS_DEV_INFO NUMBER + { add_smbios_dev_info(cur_parent, strtol($<string>2, NULL, 0), NULL); }; + /* fw_config: firmware configuration table */ fw_config_table: FW_CONFIG_TABLE fw_config_table_children END { }; -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl: Enable Row-Hammer prevention
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58856 ) Change subject: mb/siemens/mc_ehl: Enable Row-Hammer prevention ...................................................................... mb/siemens/mc_ehl: Enable Row-Hammer prevention As a prevention of Row-Hammer attacks enable the FSP-M parameter 'RhPrevention'. Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index f93e0af..82e2090 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -33,4 +33,7 @@ } /* Initialize variant specific configurations */ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false); + + /* Enable Row-Hammer prevention */ + memupd->FspmConfig.RhPrevention = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Gerrit-Change-Number: 58856 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58855 ) Change subject: mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree ...................................................................... mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree This configures GPIO GPP_G5 as an input pin for SD card detect. Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 701efb4..0ff38d7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -92,6 +92,9 @@ register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/58855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Gerrit-Change-Number: 58855 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58853 ) Change subject: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree ...................................................................... mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 8b9e9e2..701efb4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -50,9 +50,7 @@ register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" @@ -73,17 +71,15 @@ register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[2]" = "true" - register "PcieRpLtrDisable[3]" = "true" register "PcieRpLtrDisable[4]" = "true" - register "PcieRpLtrDisable[5]" = "true" + register "PcieRpLtrDisable[6]" = "true" # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" @@ -220,9 +216,7 @@ device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.3 on end # RP4 (pcie0 single VC) device pci 1c.4 on end # RP5 (pcie1 multi VC) - device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) -- To view, visit https://review.coreboot.org/c/coreboot/+/58853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Gerrit-Change-Number: 58853 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58852 ) Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree ...................................................................... mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree On mc_ehl2 there are currently four of the six PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device. Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 451c5dd..8b9e9e2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,19 +55,19 @@ register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" -- To view, visit https://review.coreboot.org/c/coreboot/+/58852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Gerrit-Change-Number: 58852 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021