Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58853 )
Change subject: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
......................................................................
mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on
this mainboard and are not routed either, so remove them from the
devicetree completely. PCIe root port #7 (00:1c.6) is connected and
used. Add the missing settings for L1 substates and latency reporting to
disable these features for this port as well.
Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 2 insertions(+), 8 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 8b9e9e2..701efb4 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -50,9 +50,7 @@
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
@@ -73,17 +71,15 @@
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
- register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
- register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
- register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true"
- register "PcieRpLtrDisable[5]" = "true"
+ register "PcieRpLtrDisable[6]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
@@ -220,9 +216,7 @@
device pci 1c.0 on end # RP1 (pcie0 single VC)
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
- device pci 1c.3 on end # RP4 (pcie0 single VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
- device pci 1c.5 on end # RP6 (pcie2 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
--
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Gerrit-Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Gerrit-Change-Number: 58853
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Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58852 )
Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
......................................................................
mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 12 insertions(+), 12 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 451c5dd..8b9e9e2 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -55,19 +55,19 @@
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[6]" = "1"
- register "PcieClkSrcUsage[0]" = "0x00"
- register "PcieClkSrcUsage[1]" = "0x01"
- register "PcieClkSrcUsage[2]" = "0x02"
- register "PcieClkSrcUsage[3]" = "0xFF"
- register "PcieClkSrcUsage[4]" = "0xFF"
- register "PcieClkSrcUsage[5]" = "0xFF"
+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
- register "PcieClkSrcClkReq[0]" = "0xFF"
- register "PcieClkSrcClkReq[1]" = "0xFF"
- register "PcieClkSrcClkReq[2]" = "0xFF"
- register "PcieClkSrcClkReq[3]" = "0xFF"
- register "PcieClkSrcClkReq[4]" = "0xFF"
- register "PcieClkSrcClkReq[5]" = "0xFF"
+ register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
--
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58935
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
......................................................................
soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so
we have to provide an init function in SoC for the mainboard
to select right config.
TEST=boot to romstage
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337
---
M src/soc/mediatek/mt8186/include/soc/spi.h
M src/soc/mediatek/mt8186/spi.c
2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/58935/2
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58935 )
Change subject: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58935/comment/d5c01d91_04a7a7d9
PS1, Line 9: Add NOR-Flash GPIO setting in mt8186/spi.c.
What about
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so
we have to provide an init function in SoC for the mainboard
to select right config.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58934 )
Change subject: Documentation/coding_style.md: Avoid weakly linked symbols
......................................................................
Patch Set 2:
(2 comments)
File Documentation/contributing/coding_style.md:
https://review.coreboot.org/c/coreboot/+/58934/comment/b118fcc1_8e0bd5ea
PS2, Line 969: When calling functions in common code
: that might not be implemented by all platforms
If a function in common code isn't implemented by all platforms, is it still "common code"?
https://review.coreboot.org/c/coreboot/+/58934/comment/647cd8fa_5305249f
PS2, Line 971: parameter
option
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