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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57131
to look at the new patch set (#27).
Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
amdfwtool: Add support for AMD's BIOS recovery feature
The BIOS recovery feature helps recover the computer from a Power On
Self-Test (POST) or a boot failure that is caused by a corrupt
BIOS. The system in BIOS recovery mode goes a different route, uses
different FWs and different AMD FW layout. So the amdfwtool needs to
change.
Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 56 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/57131/27
--
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Gerrit-Change-Number: 57131
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58895 )
Change subject: mb/siemens/mc_ehl: Disable PMC low power modes
......................................................................
mb/siemens/mc_ehl: Disable PMC low power modes
All the mainboard variants of mc_ehl do not use the external switches
for the bypass rails. Disable the matching UPDs and all the low power
modes of the PMC.
Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index fc03115..5c8f584 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -125,6 +125,11 @@
/* Disable P-States */
params->MaxRatio = 0;
+
+ /* Disable PMC low power modes */
+ params->PmcLpmS0ixSubStateEnableMask = 0;
+ params->PmcV1p05PhyExtFetControlEn = 0;
+ params->PmcV1p05IsExtFetControlEn = 0;
}
static void mainboard_init(void *chip_info)
--
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Gerrit-Change-Number: 58895
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58894 )
Change subject: mb/siemens/mc_ehl: Disable all P-States
......................................................................
mb/siemens/mc_ehl: Disable all P-States
In order to get a reliable real-time performance disable all P-States
for all mc_ehl based mainboard.
Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index eff2d21..fc03115 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -122,6 +122,9 @@
/* Set maximum package C-state to PkgC0C1 */
params->PkgCStateLimit = 0;
+
+ /* Disable P-States */
+ params->MaxRatio = 0;
}
static void mainboard_init(void *chip_info)
--
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Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58893 )
Change subject: mb/siemens/mc_ehl: Disable C-States for CPU and package
......................................................................
mb/siemens/mc_ehl: Disable C-States for CPU and package
Disable all C-states other than C0/C1 for CPU and package.
Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
1 file changed, 10 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index e64dbda..eff2d21 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -10,6 +10,7 @@
#include <hwilib.h>
#include <i210.h>
#include <soc/gpio.h>
+#include <soc/ramstage.h>
#include <string.h>
#include <timer.h>
#include <timestamp.h>
@@ -114,6 +115,15 @@
printk(BIOS_NOTICE, "done!\n");
}
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ /* Disable CPU power states (C-states) */
+ params->Cx = 0;
+
+ /* Set maximum package C-state to PkgC0C1 */
+ params->PkgCStateLimit = 0;
+}
+
static void mainboard_init(void *chip_info)
{
const struct pad_config *pads;
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58912 )
Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()`
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Well, if it does, then CONFIG_MAX_CPUS is wrong. There's a check in `src/cpu/x86/mp_init. […]
That being said, I agree that this change in behavior should be accounted for in the commit message. `Refactor` sounds like behavior doesn't change, but this is not the case. Any alternatives? `Simplify` maybe?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58919 )
Change subject: cpu/x86/mp: Use unsigned type for CPU count
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/58919/comment/906c42d1_46592bd0
PS1, Line 1111: if (mp_state.cpu_count <= 0) {
: printk(BIOS_ERR, "Invalid cpu_count: %d\n", mp_state.cpu_count);
Revise `cpu_count` retyping consequences, or split it to a separate commit (other variables should also be retyped).
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Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()`
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> looks good to me, but might be worth mentioning that this function might now detect more than CONFIG […]
Well, if it does, then CONFIG_MAX_CPUS is wrong. There's a check in `src/cpu/x86/mp_init.c` function `allocate_cpu_devices()`. I think undercounting CPUs is more serious.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58925 )
Change subject: soc/intel: move SGX ACPI code to block/acpi
......................................................................
Patch Set 2:
(1 comment)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/58925/comment/471a46dd_b70f5363
PS2, Line 1239: void sgx_fill_ssdt(void);
Why is this function declaration in common code, and not somewhere in soc/intel?
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58887 )
Change subject: mb/siemens/mc_ehl2: Clean up devicetree
......................................................................
mb/siemens/mc_ehl2: Clean up devicetree
There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).
This commit cleans up devicetree.cb and removes all unused and disabled
devices.
Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 4 insertions(+), 64 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 0ff38d7..67ff3d0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -98,11 +98,11 @@
# LPSS Serial IO (I2C/UART/GSPI) related UPDs
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
- [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}"
@@ -110,7 +110,7 @@
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
- [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART2] = PchSerialIoPci,
}"
register "SerialIoUartDmaEnable" = "{
@@ -132,38 +132,10 @@
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 off end # SA Thermal device
- device pci 08.0 off end # GNA
- device pci 09.0 off end # CPU Intel Trace Hub
-
- device pci 10.0 off end # I2C6
- device pci 10.1 off end # I2C7
- device pci 10.5 on end # Integrated Error Handler
-
- device pci 11.0 off end # Intel PSE UART0
- device pci 11.1 off end # Intel PSE UART1
- device pci 11.2 off end # Intel PSE UART2
- device pci 11.3 off end # Intel PSE UART3
- device pci 11.4 off end # Intel PSE UART4
- device pci 11.5 off end # Intel PSE UART5
- device pci 11.6 off end # Intel PSE IS20
- device pci 11.7 off end # Intel PSE IS21
device pci 12.0 on end # GSPI2
- device pci 12.3 on end # Management Engine UMA Access
- device pci 12.4 on end # Management Engine PTT DMA Controller
- device pci 12.5 off end # UFS0
- device pci 12.7 off end # UFS1
-
- device pci 13.0 off end # Intel PSE GSPI0
- device pci 13.1 off end # Intel PSE GSPI1
- device pci 13.2 off end # Intel PSE GSPI2
- device pci 13.3 off end # Intel PSE GSPI3
- device pci 13.4 off end # Intel PSE GPIO0
- device pci 13.5 off end # Intel PSE GPIO1
device pci 14.0 on end # USB3.1 xHCI
- device pci 14.1 off end # USB3.1 xDCI (OTG)
device pci 15.0 on end # I2C0
device pci 15.1 on end # I2C1
@@ -185,36 +157,16 @@
end
device pci 15.3 on end # I2C3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 on end # Management Engine Interface 2
- device pci 16.4 on end # Management Engine Interface 3
- device pci 16.5 on end # Management Engine Interface 4
+ device pci 16.0 hidden end # Management Engine Interface 1
device pci 17.0 on end # SATA
- device pci 18.0 off end # Intel PSE I2C7
- device pci 18.1 off end # Intel PSE CAN0
- device pci 18.2 off end # Intel PSE CAN1
- device pci 18.3 off end # Intel PSE QEP0
- device pci 18.4 off end # Intel PSE QEP1
- device pci 18.5 off end # Intel PSE QEP2
- device pci 18.6 off end # Intel PSE QEP3
-
device pci 19.0 on end # I2C4
device pci 19.1 on end # I2C5
device pci 19.2 on end # UART2
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1a.3 off end # Intel Safety Island
-
- device pci 1b.0 off end # Intel PSE I2C0
- device pci 1b.1 off end # Intel PSE I2C1
- device pci 1b.2 off end # Intel PSE I2C2
- device pci 1b.3 off end # Intel PSE I2C3
- device pci 1b.4 off end # Intel PSE I2C4
- device pci 1b.5 off end # Intel PSE I2C5
- device pci 1b.6 off end # Intel PSE I2C6
device pci 1c.0 on end # RP1 (pcie0 single VC)
device pci 1c.1 on end # RP2 (pcie0 single VC)
@@ -225,30 +177,18 @@
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0
device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1
- device pci 1d.3 off end # Intel PSE DMA0
- device pci 1d.4 off end # Intel PSE DMA1
- device pci 1d.5 off end # Intel PSE DMA2
- device pci 1d.6 off end # Intel PSE PWM
- device pci 1d.7 off end # Intel PSE ADC
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1
- device pci 1e.2 off end # GSPI0
- device pci 1e.3 off end # GSPI1
device pci 1e.4 on end # PCH Time-Sensitive Networking GbE
- device pci 1e.6 on end # HPET
- device pci 1e.7 on end # IOAPIC
device pci 1f.0 on # eSPI Interface
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
- device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 off end # Intel cAVS/HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI (flash & TPM)
- device pci 1f.7 off end # PCH Intel Trace Hub
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299
Gerrit-Change-Number: 58887
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged