coreboot-gerrit November 2021

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Change in coreboot[master]: mb/prodrive/hermes: Number Ethernet devices
by Angel Pons (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Patrick Rudolph, Christian Walter, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58628 ) Change subject: mb/prodrive/hermes: Number Ethernet devices ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58628/comment/3943a95f_c53100fc PS1, Line 14: [RETEST] > This would be enp6s0 with a M.2 NVMe SSD (which uses bus 5). […] Done https://review.coreboot.org/c/coreboot/+/58628/comment/693e60ae_5c965d66 PS1, Line 20: would probably change > the names definitely change Done https://review.coreboot.org/c/coreboot/+/58628/comment/bb180b03_cc3cafb9 PS1, Line 26: [RETEST] > It works! Done Patchset: PS3: needs manual rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/58628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a527298f84172f9135006083ad7e748dcc27911 Gerrit-Change-Number: 58628 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 04 Nov 2021 13:12:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure Acoustic noise mitigation
by Chen Wisley (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58947 to review the following change. Change subject: mb/google/brya/var/redrix: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/redrix: Configure Acoustic noise mitigation Enable Acoustic noise mitigation for redrix and set slew rate to 1/8 BUG=b:204009588 TEST=build and verified by power team Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/58947/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index ce9ba37..4c424ba 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -37,6 +37,11 @@ # FIVR RFI Spread Spectrum 6% register "FivrSpreadSpectrum" = "FIVR_SS_6" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/58947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Gerrit-Change-Number: 58947 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 28: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132276): https://review.coreboot.org/c/coreboot/+/57131/comment/d57f93d5_0a4e756e PS28, Line 1846: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 28 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 04 Nov 2021 12:54:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: emulation/qemu-i440fx,q35: Split chromeos.c
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58946 ) Change subject: emulation/qemu-i440fx,q35: Split chromeos.c ...................................................................... emulation/qemu-i440fx,q35: Split chromeos.c This drops VBOOT_NO_BOARD_SUPPORT. There is little impact of always having recovery_mode_switch() implemented in bootmode.c. A weak write_protect_state() is not necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation. Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS) so the weak implementation would not be referenced. Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/bootmode.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/chromeos.c 6 files changed, 36 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/58946/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1b9edf0..8728e4e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -21,7 +21,6 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index cac74ee..ba03e1a 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -8,3 +8,6 @@ ramstage-y += fw_cfg.c ramstage-y += memmap.c ramstage-y += northbridge.c + +verstage-y += fw_cfg.c +all-y += bootmode.c diff --git a/src/mainboard/emulation/qemu-i440fx/bootmode.c b/src/mainboard/emulation/qemu-i440fx/bootmode.c new file mode 100644 index 0000000..d6a9ffd --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/bootmode.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <console/console.h> +#include "../qemu-i440fx/fw_cfg.h" + +/* + * Enable recovery mode with fw_cfg option to qemu: + * -fw_cfg name=opt/cros/recovery,string=1 + */ +int get_recovery_mode_switch(void) +{ + FWCfgFile f; + + if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { + uint8_t rec_mode; + if (f.size != 1) { + printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); + return 0; + } + fw_cfg_get(f.select, &rec_mode, f.size); + if (rec_mode == '1') { + printk(BIOS_INFO, "Recovery is enabled.\n"); + return 1; + } + } + + return 0; +} + diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 04dce28..e078aa9 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -21,7 +21,6 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 6d5c29e..43dec4e 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -16,9 +16,10 @@ ramstage-y += memmap.c ramstage-y += cpu.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c +verstage-y += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += ../qemu-i440fx/bootmode.c + smm-y += smi.c smm-y += memmap.c diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 201e1af..0c91ef3 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -2,9 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> -#include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "../qemu-i440fx/fw_cfg.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -17,35 +15,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - -/* - * Enable recovery mode with fw_cfg option to qemu: - * -fw_cfg name=opt/cros/recovery,string=1 - */ -int get_recovery_mode_switch(void) -{ - FWCfgFile f; - - if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { - uint8_t rec_mode; - if (f.size != 1) { - printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); - return 0; - } - fw_cfg_get(f.select, &rec_mode, f.size); - if (rec_mode == '1') { - printk(BIOS_INFO, "Recovery is enabled.\n"); - return 1; - } - } - - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Gerrit-Change-Number: 58946 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/guybrush: Move SPI speed override
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58945 ) Change subject: google/guybrush: Move SPI speed override ...................................................................... google/guybrush: Move SPI speed override SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/guybrush/chromeos.c A src/mainboard/google/guybrush/spi_speeds.c 3 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58945/1 diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 6bc3288..1438d86 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -16,10 +16,11 @@ ramstage-y += mainboard.c ramstage-y += ec.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += chromeos.c + +all-y += spi_speeds.c verstage-y += verstage.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index a7cc0a8..8ea360a 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <amdblocks/spi.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> @@ -24,10 +22,3 @@ }; DECLARE_CROS_GPIOS(cros_gpios); -void mainboard_spi_fast_speed_override(uint8_t *fast_speed) -{ - uint32_t board_ver = board_id(); - - if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) - *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; -} diff --git a/src/mainboard/google/guybrush/spi_speeds.c b/src/mainboard/google/guybrush/spi_speeds.c new file mode 100644 index 0000000..857e02d --- /dev/null +++ b/src/mainboard/google/guybrush/spi_speeds.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/spi.h> +#include <boardid.h> +#include <stdint.h> + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Gerrit-Change-Number: 58945 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... [test] fix indirect-include Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/google/chromeos/chromeos.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: restore

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has removed build bot (Jenkins) from this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Removed cc build bot (Jenkins). -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Chen Wisley (Code Review) 04 Nov '21

04 Nov '21

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... soc/intel/alderlake: Add Acoustic noise mitigation UPDs This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:204009588 TEST=build Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/58944/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index d259442..ec8642b 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -151,6 +151,21 @@ FIVR_SS_6 = 44, }; +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16 +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -528,6 +543,19 @@ * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. */ uint8_t FivrSpreadSpectrum; + /* + * Enable or Disable Acoustic Noise Mitigation feature + */ + uint8_t AcousticNoiseMitigation; + /* + * Disable Fast Slew Rate for Deep Package C States for VR domains + */ + uint8_t FastPkgCRampDisable; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 + */ + uint8_t SlowSlewRate; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 17edada..3a36b20 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -739,6 +739,14 @@ s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; } +static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + s_cfg->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; + s_cfg->SlowSlewRate[0] = config->SlowSlewRate; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -770,6 +778,7 @@ fill_fsps_irq_params, fill_fsps_fivr_params, fill_fsps_fivr_rfi_params, + fill_fsps_acoustic_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021