coreboot-gerrit November 2021

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Change in coreboot[master]: emulation/qemu-i440fx,q35: Split chromeos.c
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58946 ) Change subject: emulation/qemu-i440fx,q35: Split chromeos.c ...................................................................... emulation/qemu-i440fx,q35: Split chromeos.c This drops VBOOT_NO_BOARD_SUPPORT. There is little impact of always having recovery_mode_switch() implemented in bootmode.c. A weak write_protect_state() is not necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation. Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS) so the weak implementation would not be referenced. Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/bootmode.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/chromeos.c 6 files changed, 36 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/58946/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1b9edf0..8728e4e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -21,7 +21,6 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index cac74ee..ba03e1a 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -8,3 +8,6 @@ ramstage-y += fw_cfg.c ramstage-y += memmap.c ramstage-y += northbridge.c + +verstage-y += fw_cfg.c +all-y += bootmode.c diff --git a/src/mainboard/emulation/qemu-i440fx/bootmode.c b/src/mainboard/emulation/qemu-i440fx/bootmode.c new file mode 100644 index 0000000..d6a9ffd --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/bootmode.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <console/console.h> +#include "../qemu-i440fx/fw_cfg.h" + +/* + * Enable recovery mode with fw_cfg option to qemu: + * -fw_cfg name=opt/cros/recovery,string=1 + */ +int get_recovery_mode_switch(void) +{ + FWCfgFile f; + + if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { + uint8_t rec_mode; + if (f.size != 1) { + printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); + return 0; + } + fw_cfg_get(f.select, &rec_mode, f.size); + if (rec_mode == '1') { + printk(BIOS_INFO, "Recovery is enabled.\n"); + return 1; + } + } + + return 0; +} + diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 04dce28..e078aa9 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -21,7 +21,6 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 6d5c29e..43dec4e 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -16,9 +16,10 @@ ramstage-y += memmap.c ramstage-y += cpu.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c +verstage-y += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += ../qemu-i440fx/bootmode.c + smm-y += smi.c smm-y += memmap.c diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 201e1af..0c91ef3 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -2,9 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> -#include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "../qemu-i440fx/fw_cfg.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -17,35 +15,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - -/* - * Enable recovery mode with fw_cfg option to qemu: - * -fw_cfg name=opt/cros/recovery,string=1 - */ -int get_recovery_mode_switch(void) -{ - FWCfgFile f; - - if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { - uint8_t rec_mode; - if (f.size != 1) { - printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); - return 0; - } - fw_cfg_get(f.select, &rec_mode, f.size); - if (rec_mode == '1') { - printk(BIOS_INFO, "Recovery is enabled.\n"); - return 1; - } - } - - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Gerrit-Change-Number: 58946 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/guybrush: Move SPI speed override
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58945 ) Change subject: google/guybrush: Move SPI speed override ...................................................................... google/guybrush: Move SPI speed override SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/guybrush/chromeos.c A src/mainboard/google/guybrush/spi_speeds.c 3 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58945/1 diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 6bc3288..1438d86 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -16,10 +16,11 @@ ramstage-y += mainboard.c ramstage-y += ec.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += chromeos.c + +all-y += spi_speeds.c verstage-y += verstage.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index a7cc0a8..8ea360a 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <amdblocks/spi.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> @@ -24,10 +22,3 @@ }; DECLARE_CROS_GPIOS(cros_gpios); -void mainboard_spi_fast_speed_override(uint8_t *fast_speed) -{ - uint32_t board_ver = board_id(); - - if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) - *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; -} diff --git a/src/mainboard/google/guybrush/spi_speeds.c b/src/mainboard/google/guybrush/spi_speeds.c new file mode 100644 index 0000000..857e02d --- /dev/null +++ b/src/mainboard/google/guybrush/spi_speeds.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/spi.h> +#include <boardid.h> +#include <stdint.h> + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Gerrit-Change-Number: 58945 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... [test] fix indirect-include Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/google/chromeos/chromeos.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: restore

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has removed build bot (Jenkins) from this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Removed cc build bot (Jenkins). -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [test] fix indirect-include
by Kyösti Mälkki (Code Review) 04 Nov '21

04 Nov '21

Kyösti Mälkki has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/58923 ) Change subject: [test] fix indirect-include ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/58923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Gerrit-Change-Number: 58923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Chen Wisley (Code Review) 04 Nov '21

04 Nov '21

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... soc/intel/alderlake: Add Acoustic noise mitigation UPDs This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:204009588 TEST=build Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/58944/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index d259442..ec8642b 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -151,6 +151,21 @@ FIVR_SS_6 = 44, }; +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16 +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -528,6 +543,19 @@ * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. */ uint8_t FivrSpreadSpectrum; + /* + * Enable or Disable Acoustic Noise Mitigation feature + */ + uint8_t AcousticNoiseMitigation; + /* + * Disable Fast Slew Rate for Deep Package C States for VR domains + */ + uint8_t FastPkgCRampDisable; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 + */ + uint8_t SlowSlewRate; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 17edada..3a36b20 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -739,6 +739,14 @@ s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; } +static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + s_cfg->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; + s_cfg->SlowSlewRate[0] = config->SlowSlewRate; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -770,6 +778,7 @@ fill_fsps_irq_params, fill_fsps_fivr_params, fill_fsps_fivr_rfi_params, + fill_fsps_acoustic_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 27: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132264): https://review.coreboot.org/c/coreboot/+/57131/comment/76b3b73b_9d2c8850 PS27, Line 1846: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 27 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 04 Nov 2021 12:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Bao Zheng (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58555 to look at the new patch set (#6). Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... amdfwtool: Set soc name for Stoneyridge For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/58555/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/purism/librem_skl: Clean up hda_verb.c
by Angel Pons (Code Review) 04 Nov '21

04 Nov '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58903 ) Change subject: mb/purism/librem_skl: Clean up hda_verb.c ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > oh, wait, i mixed up 12AM and 12PM and submitted this patch series a bit too early. […] Don't worry, we all make mistakes sometimes 😊 I'm positive that this patch train shouldn't cause any issues: the last three commits are reproducible and the first one is a one-liner that is most likely reproducible as well (I didn't test it). There's a rule in our Gerrit guidelines [1] that allows "trivial" changes that don't affect the final binary output (there's a different rule for emergency fixes) to be submitted early if: 1. the commit message should point out how reproducibility was tested 2. the submitter must be different from the authors 3. the submitter must document their intent in the Gerrit discussion This rule isn't meant to be used frequently, just in cases where submitting a trivial change early is useful for some reason. For example, one can submit a trivial change before making a complicated patch train to avoid having to manually rebase the train after the trivial change got merged. I prefer not to use this rule. I hardly ever have a reason to use it, and post-merge discussion can be somewhat bitter in rare cases (e.g. when pushing the meaning of "trivial" to its limits). However, I find it very useful to assess accidental early submissions. In this case, I wouldn't have used this rule to *intentionally* submit these changes early, but I'm not mad, worried, upset or anything remotely similar that they were submitted early because of a confusing time format. TL;DR: Nothing to worry about, just me being highly inspired today 😄 [1]: https://doc.coreboot.org/getting_started/gerrit_guidelines.html -- To view, visit https://review.coreboot.org/c/coreboot/+/58903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f5ff9614a8f8c0b7f3a3c633a1dcdda8c5876c Gerrit-Change-Number: 58903 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 11:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2021