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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58923
to look at the new patch set (#4).
Change subject: [test] fix indirect-include
......................................................................
[test] fix indirect-include
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/auron/ec.c
M src/mainboard/google/brya/variants/anahera/gpio.c
M src/mainboard/google/brya/variants/brask/gpio.c
M src/mainboard/google/brya/variants/felwinter/gpio.c
M src/mainboard/google/brya/variants/gimble/gpio.c
M src/mainboard/google/brya/variants/kano/gpio.c
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/redrix/gpio.c
M src/mainboard/google/brya/variants/taeko/gpio.c
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/dedede/variants/blipper/gpio.c
M src/mainboard/google/dedede/variants/boten/gpio.c
M src/mainboard/google/dedede/variants/gooey/gpio.c
M src/mainboard/google/dedede/variants/metaknight/gpio.c
M src/mainboard/google/foster/mainboard.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/nyan/mainboard.c
M src/mainboard/google/nyan_big/mainboard.c
M src/mainboard/google/nyan_blaze/mainboard.c
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/veyron/mainboard.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/mainboard.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/mainboard.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/mainboard/intel/strago/ec.c
M src/vendorcode/google/chromeos/chromeos.h
28 files changed, 1 insertion(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/4
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58930 )
Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/felwinter/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/58930/comment/32bcee13_41a739f6
PS2, Line 126: #TBD, felwinter remove typeC port0
: chip ec/google/chromeec
: use conn1 as mux_conn[1]
: use conn2 as mux_conn[0]
> stale comment? also should they be ordered by conn or by mux_conn? e..g […]
This is tricky, conn2=MB port2 is correct but EC mux is 0. Ordered by conn is fine, for AP side, MB port is primary :p
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 )
Change subject: tigerlake/apci: Only use SCM for ChromeOS
......................................................................
Set Ready For Review
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58839 )
Change subject: src/lib: Add FW_CONIFG_SOURCE_VPD
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58839/comment/b75bb1b8_67341011
PS9, Line 7: CONIFG_
CONFIG
File src/lib/fw_config.c:
https://review.coreboot.org/c/coreboot/+/58839/comment/9bba9913_4fba653a
PS9, Line 49: int32_t
nit: I would prefer this type to match the type of `vpd_get_int`, which just takes an `int *`
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Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
It is boilerplate, but it's also only a few lines, and this means generating a function with a macro... I don't know if it's worth it?
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Change subject: [RFC] ChromeOS: Promote variant_cros_gpio()
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
LGTM, but again I want to test this series too
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Change subject: vc/amd/agesa: fix out-of-bounds read
......................................................................
Patch Set 5:
(1 comment)
File src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c:
https://review.coreboot.org/c/coreboot/+/58803/comment/1af5c369_df7dcbbf
PS3, Line 232: (MmioPair + i) < MMIO_REG_PAIR_NUM
> Should the check be done before accessing the table (before &&)?
Done
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Change subject: mb/google,intel: Fix indirect includes
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google: Fix indirect include bootmode.h
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Patch Set 1: Code-Review+2
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