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Change subject: ChromeOS: Add legacy mainboard_ec_running_ro()
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
hm, motivation is good, but is there a way to do it without adding another weak function?
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/58896/comment/9648bfbc_2b0a8526
PS2, Line 36: )
`void` here, also we usually keep __weak before the return type e.g.
__weak bool mainboard_ec...
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Change subject: ec/system76/ec: acpi: Add dGPU thermal reporting
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Set Ready For Review
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Change subject: ChromeOS: Remove separate gnvs.asl
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Patch Set 3: Code-Review+2
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Change subject: ChromeOS: Create pseudo-device ACPI NVS
......................................................................
Patch Set 10: Code-Review+1
(2 comments)
Patchset:
PS10:
Thanks Kyosti, this looks really nice 😊 I'd like to boot this series once to make sure everything still works on the other end though; I'm OOO the rest of this week, will attempt that early next week
File src/lib/hardwaremain.c:
https://review.coreboot.org/c/coreboot/+/55502/comment/79a06a05_2e9a9aa2
PS8, Line 467:
> Yeah I think that would work
Ack
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 28:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56773/comment/abbbdd75_4d36ccb1
PS28, Line 12:
Commit need to be added.
The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated.
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58555
to look at the new patch set (#7).
Change subject: amdfwtool: Set soc name for Stoneyridge
......................................................................
amdfwtool: Set soc name for Stoneyridge
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.
Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
M util/amdfwtool/amdfwtool.c
2 files changed, 9 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/58555/7
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Change subject: soc/intel: move SGX ACPI code to block/acpi
......................................................................
Patch Set 2:
(1 comment)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/58925/comment/c90ec481_50d050f5
PS2, Line 1239: void sgx_fill_ssdt(void);
> Why is this function declaration in common code, and not somewhere in soc/intel?
Why move it? intelblocks/sgx.h looks like the right place?
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