coreboot-gerrit November 2021

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Change in coreboot[master]: lib/cbfs: Add cbfs_preload()
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56491 ) Change subject: lib/cbfs: Add cbfs_preload() ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Gerrit-Change-Number: 56491 Gerrit-PatchSet: 14 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:37:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add list.c to all stages
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add list.c to all stages ...................................................................... lib: Add list.c to all stages This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0f96aeb..1af7346 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -28,6 +28,8 @@ $(obj)/ramstage/lib/asan.o: CFLAGS_asan = endif +all-y += list.c + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -155,7 +157,6 @@ ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c -ramstage-y += list.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: Add list.c to all stages
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add list.c to all stages ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:35:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56579 ) Change subject: arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA ...................................................................... arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA AMD platforms require the SPI contents to be 64 byte aligned in order to use the SPI DMA controller. BUG=b:179699789 TEST=Build guybrush and verify cbfs was invoked with -a 64 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I842c85288acd8f7ac99b127c94b1cf235e264ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56579 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Makefile.inc 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e91ddac..458bcc6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -43,6 +43,13 @@ pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) pci$(stripped_vgabios_dgpu_id).rom-type := optionrom +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +pci$(stripped_vgabios_id).rom-align := 64 +pci$(stripped_second_vbios_id).rom-align := 64 +pci$(stripped_vgabios_dgpu_id).rom-align := 64 +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + ############################################################################### # common support for early assembly includes ############################################################################### 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/56579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I842c85288acd8f7ac99b127c94b1cf235e264ea2 Gerrit-Change-Number: 56579 Gerrit-PatchSet: 14 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58707 ) Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index e775606..76f4ec7 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,6 +16,12 @@ help Select this option to enable SPI DMA support. +# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# aligned. +config CBFS_CACHE_ALIGN + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58706 ) Change subject: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option ...................................................................... lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option This option will allow platforms to set the alignment of the cbfs_cache buffers. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 8, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58706 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/Kconfig M src/lib/cbfs.c 2 files changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 0f651b3..41a23b2 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -99,6 +99,12 @@ lookup must re-read the same CBFS directory entries from flash to find the respective file. +config CBFS_CACHE_ALIGN + int + default 8 + help + Sets the alignment of the buffers returned by the cbfs_cache. + config PAYLOAD_PRELOAD bool depends on COOP_MULTITASKING diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 7633fdf..1c79b65 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,7 +20,7 @@ #if ENV_STAGE_HAS_DATA_SECTION struct mem_pool cbfs_cache = - MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), sizeof(uint64_t)); + MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); #else struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); #endif @@ -29,7 +29,7 @@ { if (_preram_cbfs_cache != _postram_cbfs_cache) mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), - sizeof(uint64_t)); + CONFIG_CBFS_CACHE_ALIGN); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Gerrit-Change-Number: 58706 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... commonlib/mem_pool: Allow configuring the alignment AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/lib/cbfs.c 3 files changed, 21 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index 6c85397..42b5d1e 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -3,6 +3,7 @@ #ifndef _MEM_POOL_H_ #define _MEM_POOL_H_ +#include <assert.h> #include <stddef.h> #include <stdint.h> @@ -16,23 +17,23 @@ * were chosen to optimize for the CBFS cache case which may need two buffers * to map a single compressed file, and will free them in reverse order.) * - * The memory returned by allocations are at least 8 byte aligned. Note - * that this requires the backing buffer to start on at least an 8 byte - * alignment. + * You must ensure the backing buffer is 'alignment' aligned. */ struct mem_pool { uint8_t *buf; size_t size; + size_t alignment; uint8_t *last_alloc; uint8_t *second_to_last_alloc; size_t free_offset; }; -#define MEM_POOL_INIT(buf_, size_) \ +#define MEM_POOL_INIT(buf_, size_, alignment_) \ { \ .buf = (buf_), \ .size = (size_), \ + .alignment = (alignment_), \ .last_alloc = NULL, \ .second_to_last_alloc = NULL, \ .free_offset = 0, \ @@ -46,10 +47,15 @@ } /* Initialize a memory pool. */ -static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz) +static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz, + size_t alignment) { + assert(alignment); + assert((uintptr_t)buf % alignment == 0); + mp->buf = buf; mp->size = sz; + mp->alignment = alignment; mem_pool_reset(mp); } diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index c300c65..d82ab18 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -7,8 +7,11 @@ { void *p; - /* Make all allocations be at least 8 byte aligned. */ - sz = ALIGN_UP(sz, 8); + if (mp->alignment == 0) + return NULL; + + /* We assume that mp->buf started mp->alignment aligned */ + sz = ALIGN_UP(sz, mp->alignment); /* Determine if any space available. */ if ((mp->size - mp->free_offset) < sz) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 322f161..7633fdf 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -19,16 +19,17 @@ #include <timestamp.h> #if ENV_STAGE_HAS_DATA_SECTION -struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache)); +struct mem_pool cbfs_cache = + MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), sizeof(uint64_t)); #else -struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0); +struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); #endif static void switch_to_postram_cache(int unused) { if (_preram_cbfs_cache != _postram_cbfs_cache) - mem_pool_init(&cbfs_cache, _postram_cbfs_cache, - REGION_SIZE(postram_cbfs_cache)); + mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), + sizeof(uint64_t)); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 13 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/i2c: Remove the weak function
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58771 ) Change subject: amd/i2c: Remove the weak function ...................................................................... amd/i2c: Remove the weak function BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/i2c/i2c.c M src/soc/amd/stoneyridge/i2c.c 2 files changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index ff9ec90..d2e0473 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -78,11 +78,6 @@ return -1; } -void __weak soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) -{ - /* Nothing by default. */ -} - static void dw_i2c_soc_init(bool is_early_init) { unsigned int bus; diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 6a6d776..e589b04 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -5,6 +5,7 @@ #include <soc/iomap.h> #include <soc/i2c.h> #include "chip.h" +#include <drivers/i2c/designware/dw_i2c.h> static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" }, @@ -26,3 +27,8 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + /* Do nothing. */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Gerrit-Change-Number: 58771 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Set Gen3 default for all PCIe devices
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58799 ) Change subject: mb/google/guybrush: Set Gen3 default for all PCIe devices ...................................................................... mb/google/guybrush: Set Gen3 default for all PCIe devices Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index a98983b..af06e7f 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,6 +14,7 @@ .port_present = true, .start_logical_lane = 0, .end_logical_lane = 0, + .link_speed_capability = 3, .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_aspm = ASPM_L1, @@ -28,6 +29,7 @@ .port_present = true, .start_logical_lane = 1, .end_logical_lane = 1, + .link_speed_capability = 3, .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, @@ -43,6 +45,7 @@ .port_present = true, .start_logical_lane = 2, .end_logical_lane = 2, + .link_speed_capability = 3, .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_aspm = ASPM_L1, @@ -57,6 +60,7 @@ .port_present = true, .start_logical_lane = 4, .end_logical_lane = 7, + .link_speed_capability = 3, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_aspm = ASPM_L1, -- To view, visit https://review.coreboot.org/c/coreboot/+/58799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Gerrit-Change-Number: 58799 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: Update GPIO table for speak and dmic
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58877 ) Change subject: mb/google/brya/var/kano: Update GPIO table for speak and dmic ...................................................................... mb/google/brya/var/kano: Update GPIO table for speak and dmic Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: CT Lin <ctlin0(a)nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/fw_config.c M src/mainboard/google/brya/variants/kano/gpio.c 2 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved CT Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index 55a6fad..631a908 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -8,8 +8,8 @@ static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ }; static const struct pad_config dmic_disable_pads[] = { @@ -24,10 +24,10 @@ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ }; static const struct pad_config i2s_disable_pads[] = { diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f40da1..898c87c 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -82,18 +82,18 @@ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/58877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Gerrit-Change-Number: 58877 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: CT Lin <ctlin0(a)nuvoton.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021