coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel: move SGX ACPI code to block/acpi
by Angel Pons (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58925 ) Change subject: soc/intel: move SGX ACPI code to block/acpi ...................................................................... Patch Set 2: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/58925/comment/471a46dd_b70f5363 PS2, Line 1239: void sgx_fill_ssdt(void); Why is this function declaration in common code, and not somewhere in soc/intel? -- To view, visit https://review.coreboot.org/c/coreboot/+/58925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Gerrit-Change-Number: 58925 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:51:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... util/spd_tools: Add LP5 support for ADL Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M util/spd_tools/README.md M util/spd_tools/src/part_id_gen/part_id_gen.go A util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 4 files changed, 726 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md index 5be666b..a422017 100644 --- a/util/spd_tools/README.md +++ b/util/spd_tools/README.md @@ -8,6 +8,9 @@ * LPDDR4x - based on the JESD209-4C spec and Intel recommendations (docs #616599, #610202, #634730). * DDR4 - based on the JESD79-4C and Jedec 4.1.2.L-5 R29 v103 specs. +* LPDDR5 - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2 (the + LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5), + and Intel recommendations in advisory #616599. There are two tools provided to assist with generating SPDs and Makefiles to integrate into the coreboot build. These tools can also be used to allocate DRAM @@ -292,6 +295,100 @@ } ``` +### LP5 attributes + +#### Mandatory + +* `densityPerDieGb`: Density per die in Gb. Valid values: `4, 6, 8, 12, 16, + 24, 32` Gb per die. + +* `diesPerPackage`: Number of physical dies in each SDRAM package. Valid + values: `2, 4, 8` dies per package. + +* `bitWidthPerChannel`: Width of each physical channel. Valid values: `8, 16` + bits. + +* `ranksPerChannel`: Number of ranks per physical channel. Valid values: `1, + 2`. If the channels across multiple dies share the same DQ/DQS pins but use + a separate CS, then ranks is 2 else it is 1. + +* `speedMbps`: Maximum data rate supported by the part in Mbps. Valid values: + `5500, 6400` Mbps. + +#### Optional + +* `trfcabNs`: Minimum Refresh Recovery Delay Time (tRFCab) for all banks in + nanoseconds. As per JESD209-5B, this is dependent on the density per die. + Default values used: + + * 4 Gb : 180 ns + * 6 Gb : 210 ns + * 8 Gb : 210 ns + * 12 Gb: 280 ns + * 16 Gb: 280 ns + * 24 Gb: 380 ns + * 32 Gb: 380 ns + +* `trfcpbNs`: Minimum Refresh Recovery Delay Time (tRFCpb) per bank in + nanoseconds. As per JESD209-5B, this is dependent on the density per die. + Default values used: + + * 4 Gb : 90 ns + * 6 Gb : 120 ns + * 8 Gb : 120 ns + * 12 Gb: 140 ns + * 16 Gb: 140 ns + * 24 Gb: 190 ns + * 32 Gb: 190 ns + +* `trpabMinNs`: Minimum Row Precharge Delay Time (tRPab) for all banks in + nanoseconds. As per JESD209-5B, this is max(21ns, 2nCK), which defaults to + `21 ns`. + +* `trppbMinNs`: Minimum Row Precharge Delay Time (tRPpb) per bank in + nanoseconds. As per JESD209-5B, this is max(18ns, 2nCK) which defaults to + `18 ns`. + +* `tckMinPs`: SDRAM minimum cycle time (tCKmin) value in picoseconds. LPDDR5 + has two clocks: the command/addrees clock (CK) and the data clock (WCK). + They are related by the WCK:CK ratio, which can be either 4:1 or 2:1. For + LPDDR5, tCKmin is the CK period, which can be calculated from the + `speedMbps` attribute and the WCK:CK ratio as follows: `tCKmin = 1 / + (speedMbps / 2 / WCK:CK)`. The default values used are for a 4:1 WCK:CK + ratio: + + * 6400 Mbps: 1250 ps + * 5500 Mbps: 1455 ps + +* `taaMinPs`: Minimum CAS Latency Time(tAAmin) in picoseconds. This value + defaults to nck * tCKmin, where nck is maximum CAS latency, and is + determined from the `speedMbps` attribute as per JESD209-5B: + + * 6400 Mbps: 17 + * 5500 Mbps: 15 + +* `trcdMinNs`: Minimum RAS# to CAS# Delay Time (tRCDmin) in nanoseconds. As + per JESD209-5B, this is max(18ns, 2nCK) which defaults to `18 ns`. + +#### Example `memory_parts.json` + +``` +{ + "parts": [ + { + "name": "MT62F1G32D4DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + }, + ] +} +``` + ### Output The `spd_gen` tool generates the directory structure shown below. The inputs to diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index c67f127..750b825 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -45,6 +45,7 @@ var supportedMemTechs = [...]string{ "lp4x", "ddr4", + "lp5", } func usage() { diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go new file mode 100644 index 0000000..2e52bd5 --- /dev/null +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -0,0 +1,617 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +package main + +import ( + "encoding/json" + "fmt" +) + +/* ------------------------------------------------------------------------------------------ */ +/* LP5-defined types */ +/* ------------------------------------------------------------------------------------------ */ + +type lp5 struct { +} + +type LP5MemAttributes struct { + /* Primary attributes - must be provided by JSON file for each part */ + DensityPerDieGb int + DiesPerPackage int + BitWidthPerChannel int + RanksPerChannel int + SpeedMbps int + + /* + * All the following parameters are optional and required only if the part requires + * special parameters as per the datasheet. + */ + /* Timing parameters */ + TRFCABNs int + TRFCPBNs int + TRPABMinNs int + TRPPBMinNs int + TCKMinPs int + TAAMinPs int + TRCDMinNs int +} + +type LP5DensityParams struct { + DensityEncoding byte + RowAddressBitsx8Channel int + RowAddressBitsx16Channel int + TRFCABNs int + TRFCPBNs int +} + +type LP5SpeedParams struct { + TCKMinPs int + MaxCASLatency int +} + +type LP5SPDAttribFunc func(*LP5MemAttributes) byte + +type LP5SPDAttribTableEntry struct { + constVal byte + getVal LP5SPDAttribFunc +} + +/* ------------------------------------------------------------------------------------------ */ +/* Constants */ +/* ------------------------------------------------------------------------------------------ */ + +const ( + /* SPD Byte Index */ + LP5SPDIndexSize = 0 + LP5SPDIndexRevision = 1 + LP5SPDIndexMemoryType = 2 + LP5SPDIndexModuleType = 3 + LP5SPDIndexDensityBanks = 4 + LP5SPDIndexAddressing = 5 + LP5SPDIndexPackageType = 6 + LP5SPDIndexOptionalFeatures = 7 + LP5SPDIndexModuleOrganization = 12 + LP5SPDIndexBusWidth = 13 + LP5SPDIndexTimebases = 17 + LP5SPDIndexTCKMin = 18 + LP5SPDIndexTAAMin = 24 + LP5SPDIndexTRCDMin = 26 + LP5SPDIndexTRPABMin = 27 + LP5SPDIndexTRPPBMin = 28 + LP5SPDIndexTRFCABMinLSB = 29 + LP5SPDIndexTRFCABMinMSB = 30 + LP5SPDIndexTRFCPBMinLSB = 31 + LP5SPDIndexTRFCPBMinMSB = 32 + LP5SPDIndexTRPPBMinFineOffset = 120 + LP5SPDIndexTRPABMinFineOffset = 121 + LP5SPDIndexTRCDMinFineOffset = 122 + LP5SPDIndexTAAMinFineOffset = 123 + LP5SPDIndexTCKMinFineOffset = 125 + LP5SPDIndexManufacturerPartNumberStartByte = 329 + LP5SPDIndexManufacturerPartNumberEndByte = 348 + + /* SPD Byte Value */ + + /* + * From JEDEC spec: + * 6:4 (Bytes total) = 2 (512 bytes) + * 3:0 (Bytes used) = 3 (384 bytes) + * Set to 0x23 for LPDDR5. + */ + LP5SPDValueSize = 0x23 + + /* + * Revision 1.0. + */ + LP5SPDValueRevision = 0x10 + + /* + * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13. + */ + LP5SPDValueMemoryType = 0x13 + + /* + * From JEDEC spec: + * 7:7 (Hybrid) = 0 (Not hybrid) + * 6:4 (Hybrid media) = 000 (Not hybrid) + * 3:0 (Base Module Type) = 1110 (Non-DIMM solution) + * + * This is dependent on hardware design. LPDDR5 only has memory down solution. + * Hence this is not hybrid non-DIMM solution. + * Set to 0x0E. + */ + LP5SPDValueModuleType = 0x0e + + /* + * From JEDEC spec: + * 5:4 (Maximum Activate Window) = 00 (8192 * tREFI) + * 3:0 (Maximum Activate Count) = 1000 (Unlimited MAC) + * Set to 0x08. + */ + LP5SPDValueOptionalFeatures = 0x08 + + /* + * For ADL (as per advisory #616599): + * 7:5 (Number of system channels) = 000 (1 channel always) + * 4:3 (Bus width extension) = 00 (no ECC) + * 2:0 (Bus width) = 001 (x16 always) + * Set to 0x01. + */ + LP5SPDValueBusWidth = 0x01 + + /* + * From JEDEC spec: + * 3:2 (MTB) = 00 (0.125ns) + * 1:0 (FTB) = 00 (1ps) + * Set to 0x00. + */ + LP5SPDValueTimebases = 0x00 + + /* As per JEDEC spec, unused digits of manufacturer part number are left as blank. */ + LP5SPDValueManufacturerPartNumberBlank = 0x20 +) + +const ( + /* + * LPDDR5 has a flexible bank architecture with three programmable bank modes: BG, 8B, 16B. + * ADL will use 8B mode for all parts. + * + * From JEDEC spec: + * 7:6 (Bank Group Bits) = 00 (no bank groups) + * 5:4 (Bank Address Bits) = 01 (8 banks) + * Set bits 7:4 to 0b0001. + */ + LP5BankGroupsBanks = 0x1 + + /* + * Tables 8 and 9 from JESD209-5B. + * ADL uses 8B mode for all parts. The column addresses are the same for x8 and x16. + * Effective column address bits = column address bits + burst address bits = 6 + 5 = 11. + * As per JESD 21-C, this is encoded as 0b010. + */ + LP5ColumnAddressBits = 0x2 +) + +/* ------------------------------------------------------------------------------------------ */ +/* Global variables */ +/* ------------------------------------------------------------------------------------------ */ + +var LP5PlatformSetMap = map[int][]int{ + 0: {PlatformADL}, +} + +var LP5PartAttributeMap = map[string]LP5MemAttributes{} +var LP5CurrSet int + +/* + * DensityEncoding: Maps the die density in Gb to the SPD encoding of the die density + * as per JESD 21-C. + * + * RowAddressBits: Maps the die density to the number of row address bits. + * Tables 6-11 in JESD209-5B (same for all three bank modes). + * + * TRFCABNs/TRFCPBNs: Maps the die density to the refresh timings. + * Tables 235 and 236 in JESD209-5B (same for all three bank modes). + */ +var LP5DensityGbToSPDEncoding = map[int]LP5DensityParams{ + 4: { + DensityEncoding: 0x4, + RowAddressBitsx8Channel: 15, + RowAddressBitsx16Channel: 14, + TRFCABNs: 180, + TRFCPBNs: 90, + }, + 6: { + DensityEncoding: 0xb, + RowAddressBitsx8Channel: 16, + RowAddressBitsx16Channel: 15, + TRFCABNs: 210, + TRFCPBNs: 120, + }, + 8: { + DensityEncoding: 0x5, + RowAddressBitsx8Channel: 16, + RowAddressBitsx16Channel: 15, + TRFCABNs: 210, + TRFCPBNs: 120, + }, + 12: { + DensityEncoding: 0x8, + RowAddressBitsx8Channel: 17, + RowAddressBitsx16Channel: 16, + TRFCABNs: 280, + TRFCPBNs: 140, + }, + 16: { + DensityEncoding: 0x6, + RowAddressBitsx8Channel: 17, + RowAddressBitsx16Channel: 16, + TRFCABNs: 280, + TRFCPBNs: 140, + }, + 24: { + DensityEncoding: 0x9, + RowAddressBitsx8Channel: 18, + RowAddressBitsx16Channel: 17, + TRFCABNs: 380, + TRFCPBNs: 190, + }, + 32: { + DensityEncoding: 0x7, + RowAddressBitsx8Channel: 18, + RowAddressBitsx16Channel: 17, + TRFCABNs: 380, + TRFCPBNs: 190, + }, +} + +/* + * Maps the number of row address bits to the SPD encoding as per JESD 21-C. + */ +var LP5RowAddressBitsEncoding = map[int]byte{ + 14: 0x2, + 15: 0x3, + 16: 0x4, + 17: 0x5, + 18: 0x6, +} + +/* + * TCKMinPs: + * LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are + * related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used. + * For ADL, the MRC expects the tCKmin to encode the CK period. This is calculated as: + * tCKmin = 1 / CK rate + * = 1 / (WCK rate / WCK:CK) + * = 1 / (speed grade / 2 / WCK:CK) // "double data rate" + * + * MaxCASLatency: + * From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0. + */ +var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{ + 6400: { + TCKMinPs: 1250, /* 1 / (6400 / 2 / 4) */ + MaxCASLatency: 17, + }, + 5500: { + TCKMinPs: 1455, /* 1 / (5500 / 2 / 4) */ + MaxCASLatency: 15, + }, +} + +var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{ + LP5SPDIndexSize: {constVal: LP5SPDValueSize}, + LP5SPDIndexRevision: {constVal: LP5SPDValueRevision}, + LP5SPDIndexMemoryType: {constVal: LP5SPDValueMemoryType}, + LP5SPDIndexModuleType: {constVal: LP5SPDValueModuleType}, + LP5SPDIndexDensityBanks: {getVal: LP5EncodeDensityBanks}, + LP5SPDIndexAddressing: {getVal: LP5EncodeSdramAddressing}, + LP5SPDIndexPackageType: {getVal: LP5EncodePackageType}, + LP5SPDIndexOptionalFeatures: {constVal: LP5SPDValueOptionalFeatures}, + LP5SPDIndexModuleOrganization: {getVal: LP5EncodeModuleOrganization}, + LP5SPDIndexBusWidth: {constVal: LP5SPDValueBusWidth}, + LP5SPDIndexTimebases: {constVal: LP5SPDValueTimebases}, + LP5SPDIndexTCKMin: {getVal: LP5EncodeTCKMin}, + LP5SPDIndexTCKMinFineOffset: {getVal: LP5EncodeTCKMinFineOffset}, + LP5SPDIndexTAAMin: {getVal: LP5EncodeTAAMin}, + LP5SPDIndexTAAMinFineOffset: {getVal: LP5EncodeTAAMinFineOffset}, + LP5SPDIndexTRCDMin: {getVal: LP5EncodeTRCDMin}, + LP5SPDIndexTRCDMinFineOffset: {getVal: LP5EncodeTRCDMinFineOffset}, + LP5SPDIndexTRPABMin: {getVal: LP5EncodeTRPABMin}, + LP5SPDIndexTRPABMinFineOffset: {getVal: LP5EncodeTRPABMinFineOffset}, + LP5SPDIndexTRPPBMin: {getVal: LP5EncodeTRPPBMin}, + LP5SPDIndexTRPPBMinFineOffset: {getVal: LP5EncodeTRPPBMinFineOffset}, + LP5SPDIndexTRFCABMinLSB: {getVal: LP5EncodeTRFCABMinLsb}, + LP5SPDIndexTRFCABMinMSB: {getVal: LP5EncodeTRFCABMinMsb}, + LP5SPDIndexTRFCPBMinLSB: {getVal: LP5EncodeTRFCPBMinLsb}, + LP5SPDIndexTRFCPBMinMSB: {getVal: LP5EncodeTRFCPBMinMsb}, +} + +/* ------------------------------------------------------------------------------------------ */ +/* Functions */ +/* ------------------------------------------------------------------------------------------ */ + +func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte { + var b byte + + // 3:0 Density per die. + b = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].DensityEncoding + + // 5:4 Bank address bits. + // 7:6 Bank group bits. + b |= LP5BankGroupsBanks << 4 + + return b +} + +func LP5EncodeSdramAddressing(memAttribs *LP5MemAttributes) byte { + var b byte + + // 2:0 Column address bits. + b = LP5ColumnAddressBits + + // 5:3 Row address bits. + density := memAttribs.DensityPerDieGb + var rowAddressBits int + if memAttribs.BitWidthPerChannel == 8 { + rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx8Channel + } else { + rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx16Channel + } + b |= LP5RowAddressBitsEncoding[rowAddressBits] << 3 + + return b +} + +func LP5EncodePackageType(memAttribs *LP5MemAttributes) byte { + var b byte + + // 1:0 Signal loading index. + b = 1 + + // 3:2 Channels per package. + // Channels per package = package width (e.g. x32) / bitWidthPerChannel (x8 or x16). + // This can equivalently be calculated as diesPerPackage / ranksPerChannel. + // This calculation is used to avoid adding a redundant attribute for package width. + channels := memAttribs.DiesPerPackage / memAttribs.RanksPerChannel + b |= byte(channels>>1) << 2 + + // 6:4 Dies per package. + b |= (byte(memAttribs.DiesPerPackage) - 1) << 4 + + // 7:7 Package type. + var packageType byte + if memAttribs.DiesPerPackage > 1 { + packageType = 1 // Non-Monolithic + } else { + packageType = 0 // Monolithic + } + b |= packageType << 7 + + return b +} + +func LP5EncodeModuleOrganization(memAttribs *LP5MemAttributes) byte { + var b byte + + // 2:0 Device data width per channel + b = byte(memAttribs.BitWidthPerChannel / 8) + + // 5:3 Package ranks per channel + b |= byte(memAttribs.RanksPerChannel-1) << 3 + + return b +} + +func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte { + return convPsToMtbByte(memAttribs.TCKMinPs) +} + +func LP5EncodeTCKMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convPsToFtbByte(memAttribs.TCKMinPs) +} + +func LP5EncodeTAAMin(memAttribs *LP5MemAttributes) byte { + return convPsToMtbByte(memAttribs.TAAMinPs) +} + +func LP5EncodeTAAMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convPsToFtbByte(memAttribs.TAAMinPs) +} + +func LP5EncodeTRCDMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRCDMinNs) +} + +func LP5EncodeTRCDMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRCDMinNs) +} + +func LP5EncodeTRPABMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRPABMinNs) +} + +func LP5EncodeTRPABMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRPABMinNs) +} + +func LP5EncodeTRPPBMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRPPBMinNs) +} + +func LP5EncodeTRPPBMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRPPBMinNs) +} + +func LP5EncodeTRFCABMinMsb(memAttribs *LP5MemAttributes) byte { + return byte((convNsToMtb(memAttribs.TRFCABNs) >> 8) & 0xff) +} + +func LP5EncodeTRFCABMinLsb(memAttribs *LP5MemAttributes) byte { + return byte(convNsToMtb(memAttribs.TRFCABNs) & 0xff) +} + +func LP5EncodeTRFCPBMinMsb(memAttribs *LP5MemAttributes) byte { + return byte((convNsToMtb(memAttribs.TRFCPBNs) >> 8) & 0xff) +} + +func LP5EncodeTRFCPBMinLsb(memAttribs *LP5MemAttributes) byte { + return byte(convNsToMtb(memAttribs.TRFCPBNs) & 0xff) +} + +func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) { + if memAttribs.TCKMinPs == 0 { + memAttribs.TCKMinPs = LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].TCKMinPs + } +} + +func LP5UpdateTAAMin(memAttribs *LP5MemAttributes) { + if memAttribs.TAAMinPs == 0 { + maxCAS := LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].MaxCASLatency + memAttribs.TAAMinPs = memAttribs.TCKMinPs * maxCAS + } +} + +func LP5UpdateTRFCAB(memAttribs *LP5MemAttributes) { + if memAttribs.TRFCABNs == 0 { + memAttribs.TRFCABNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCABNs + } +} + +func LP5UpdateTRFCPB(memAttribs *LP5MemAttributes) { + if memAttribs.TRFCPBNs == 0 { + memAttribs.TRFCPBNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCPBNs + } +} + +func LP5UpdateTRCD(memAttribs *LP5MemAttributes) { + if memAttribs.TRCDMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRCDMinNs = 18 + } +} + +func LP5UpdateTRPAB(memAttribs *LP5MemAttributes) { + if memAttribs.TRPABMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRPABMinNs = 21 + } +} + +func LP5UpdateTRPPB(memAttribs *LP5MemAttributes) { + if memAttribs.TRPPBMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRPPBMinNs = 18 + } +} + +func lp5UpdateMemoryAttributes(memAttribs *LP5MemAttributes) { + LP5UpdateTCKMin(memAttribs) + LP5UpdateTAAMin(memAttribs) + LP5UpdateTRFCAB(memAttribs) + LP5UpdateTRFCPB(memAttribs) + LP5UpdateTRCD(memAttribs) + LP5UpdateTRPAB(memAttribs) + LP5UpdateTRPPB(memAttribs) +} + +func LP5ValidateDensity(density int) error { + if _, ok := LP5DensityGbToSPDEncoding[density]; !ok { + return fmt.Errorf("Incorrect density per die: %d Gb", density) + } + return nil +} + +func LP5ValidateDies(dies int) error { + if dies != 2 && dies != 4 && dies != 8 { + return fmt.Errorf("Incorrect dies: %d", dies) + } + return nil +} + +func LP5ValidateDataWidth(width int) error { + if width != 8 && width != 16 { + return fmt.Errorf("Incorrect bit width: %d", width) + } + return nil +} + +func LP5ValidateRanks(ranks int) error { + if ranks != 1 && ranks != 2 { + return fmt.Errorf("Incorrect ranks: %d", ranks) + } + return nil +} + +func LP5ValidateSpeed(speed int) error { + if _, ok := LP5SpeedMbpsToSPDEncoding[speed]; !ok { + return fmt.Errorf("Incorrect speed: %d Mbps", speed) + } + return nil +} + +func lp5ValidateMemPartAttributes(memAttribs *LP5MemAttributes) error { + if err := LP5ValidateDensity(memAttribs.DensityPerDieGb); err != nil { + return err + } + if err := LP5ValidateDies(memAttribs.DiesPerPackage); err != nil { + return err + } + if err := LP5ValidateDataWidth(memAttribs.BitWidthPerChannel); err != nil { + return err + } + if err := LP5ValidateRanks(memAttribs.RanksPerChannel); err != nil { + return err + } + if err := LP5ValidateSpeed(memAttribs.SpeedMbps); err != nil { + return err + } + + return nil +} + +func LP5IsManufacturerPartNumberByte(index int) bool { + if index >= LP5SPDIndexManufacturerPartNumberStartByte && + index <= LP5SPDIndexManufacturerPartNumberEndByte { + return true + } + return false +} + +/* ------------------------------------------------------------------------------------------ */ +/* Interface Functions */ +/* ------------------------------------------------------------------------------------------ */ + +func (lp5) getSetMap() map[int][]int { + return LP5PlatformSetMap +} + +func (lp5) addNewPart(name string, attribs interface{}) error { + var lp5Attributes LP5MemAttributes + eByte, err := json.Marshal(attribs) + if err != nil { + return err + } + + if err := json.Unmarshal(eByte, &lp5Attributes); err != nil { + return err + } + + if err := lp5ValidateMemPartAttributes(&lp5Attributes); err != nil { + return err + } + + LP5PartAttributeMap[name] = lp5Attributes + return nil +} + +func (lp5) getSPDAttribs(name string, set int) (interface{}, error) { + lp5Attributes := LP5PartAttributeMap[name] + + LP5CurrSet = set + + lp5UpdateMemoryAttributes(&lp5Attributes) + + return lp5Attributes, nil +} + +func (lp5) getSPDLen() int { + return 512 +} + +func (lp5) getSPDByte(index int, attribs interface{}) byte { + e, ok := LP5SPDAttribTable[index] + if !ok { + if LP5IsManufacturerPartNumberByte(index) { + return LP5SPDValueManufacturerPartNumberBlank + } + return 0x00 + } + + if e.getVal != nil { + var lp5Attribs LP5MemAttributes + lp5Attribs = attribs.(LP5MemAttributes) + return e.getVal(&lp5Attribs) + } + + return e.constVal +} diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index 57b428b..fa65492 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -65,6 +65,12 @@ PlatformCZN: "CZN", } +var memTechMap = map[string]memTech{ + "lp4x": lp4x{}, + "ddr4": ddr4{}, + "lp5": lp5{}, +} + /* ------------------------------------------------------------------------------------------ */ /* Conversion Helper Functions */ /* ------------------------------------------------------------------------------------------ */ @@ -211,7 +217,9 @@ fmt.Printf("\nUsage: %s <mem_parts_list_json> <mem_technology>\n\n", os.Args[0]) fmt.Printf(" where,\n") fmt.Printf(" mem_parts_list_json = JSON File containing list of memory parts and attributes\n") - fmt.Printf(" mem_technology = Memory technology -- one of lp4x, ddr4\n\n\n") + fmt.Printf(" mem_technology = Memory technology for which to generate SPDs\n") + fmt.Printf(" supported technologies: %v\n\n\n", + reflect.ValueOf(memTechMap).MapKeys()) } func main() { @@ -223,11 +231,8 @@ var t memTech memPartsFilePath, memTechnology := os.Args[1], os.Args[2] - if strings.ToUpper(memTechnology) == "LP4X" { - t = lp4x{} - } else if strings.ToUpper(memTechnology) == "DDR4" { - t = ddr4{} - } else { + t, ok := memTechMap[strings.ToLower(memTechnology)] + if !ok { log.Fatal("Unsupported memory technology ", memTechnology) } 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 12 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl2: Clean up devicetree
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58887 ) Change subject: mb/siemens/mc_ehl2: Clean up devicetree ...................................................................... mb/siemens/mc_ehl2: Clean up devicetree There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 4 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 0ff38d7..67ff3d0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -98,11 +98,11 @@ # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C6] = PchSerialIoDisabled, [PchSerialIoIndexI2C7] = PchSerialIoDisabled, }" @@ -110,7 +110,7 @@ register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoPci, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + [PchSerialIoIndexUART2] = PchSerialIoPci, }" register "SerialIoUartDmaEnable" = "{ @@ -132,38 +132,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 08.0 off end # GNA - device pci 09.0 off end # CPU Intel Trace Hub - - device pci 10.0 off end # I2C6 - device pci 10.1 off end # I2C7 - device pci 10.5 on end # Integrated Error Handler - - device pci 11.0 off end # Intel PSE UART0 - device pci 11.1 off end # Intel PSE UART1 - device pci 11.2 off end # Intel PSE UART2 - device pci 11.3 off end # Intel PSE UART3 - device pci 11.4 off end # Intel PSE UART4 - device pci 11.5 off end # Intel PSE UART5 - device pci 11.6 off end # Intel PSE IS20 - device pci 11.7 off end # Intel PSE IS21 device pci 12.0 on end # GSPI2 - device pci 12.3 on end # Management Engine UMA Access - device pci 12.4 on end # Management Engine PTT DMA Controller - device pci 12.5 off end # UFS0 - device pci 12.7 off end # UFS1 - - device pci 13.0 off end # Intel PSE GSPI0 - device pci 13.1 off end # Intel PSE GSPI1 - device pci 13.2 off end # Intel PSE GSPI2 - device pci 13.3 off end # Intel PSE GSPI3 - device pci 13.4 off end # Intel PSE GPIO0 - device pci 13.5 off end # Intel PSE GPIO1 device pci 14.0 on end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI (OTG) device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 @@ -185,36 +157,16 @@ end device pci 15.3 on end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 on end # Management Engine Interface 4 + device pci 16.0 hidden end # Management Engine Interface 1 device pci 17.0 on end # SATA - device pci 18.0 off end # Intel PSE I2C7 - device pci 18.1 off end # Intel PSE CAN0 - device pci 18.2 off end # Intel PSE CAN1 - device pci 18.3 off end # Intel PSE QEP0 - device pci 18.4 off end # Intel PSE QEP1 - device pci 18.5 off end # Intel PSE QEP2 - device pci 18.6 off end # Intel PSE QEP3 - device pci 19.0 on end # I2C4 device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1a.3 off end # Intel Safety Island - - device pci 1b.0 off end # Intel PSE I2C0 - device pci 1b.1 off end # Intel PSE I2C1 - device pci 1b.2 off end # Intel PSE I2C2 - device pci 1b.3 off end # Intel PSE I2C3 - device pci 1b.4 off end # Intel PSE I2C4 - device pci 1b.5 off end # Intel PSE I2C5 - device pci 1b.6 off end # Intel PSE I2C6 device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) @@ -225,30 +177,18 @@ device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 - device pci 1d.3 off end # Intel PSE DMA0 - device pci 1d.4 off end # Intel PSE DMA1 - device pci 1d.5 off end # Intel PSE DMA2 - device pci 1d.6 off end # Intel PSE PWM - device pci 1d.7 off end # Intel PSE ADC device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.2 off end # GSPI0 - device pci 1e.3 off end # GSPI1 device pci 1e.4 on end # PCH Time-Sensitive Networking GbE - device pci 1e.6 on end # HPET - device pci 1e.7 on end # IOAPIC device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel cAVS/HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) - device pci 1f.7 off end # PCH Intel Trace Hub end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Gerrit-Change-Number: 58887 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/cbfs: Add cbfs_preload()
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56491 ) Change subject: lib/cbfs: Add cbfs_preload() ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Gerrit-Change-Number: 56491 Gerrit-PatchSet: 14 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:37:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add list.c to all stages
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add list.c to all stages ...................................................................... lib: Add list.c to all stages This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0f96aeb..1af7346 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -28,6 +28,8 @@ $(obj)/ramstage/lib/asan.o: CFLAGS_asan = endif +all-y += list.c + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -155,7 +157,6 @@ ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c -ramstage-y += list.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: Add list.c to all stages
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58804 ) Change subject: lib: Add list.c to all stages ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Gerrit-Change-Number: 58804 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 10:35:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56579 ) Change subject: arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA ...................................................................... arch/x86/Makefile: Align VGA_BIOS to 64 bytes when using AMD LPC SPI DMA AMD platforms require the SPI contents to be 64 byte aligned in order to use the SPI DMA controller. BUG=b:179699789 TEST=Build guybrush and verify cbfs was invoked with -a 64 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I842c85288acd8f7ac99b127c94b1cf235e264ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56579 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Makefile.inc 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e91ddac..458bcc6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -43,6 +43,13 @@ pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) pci$(stripped_vgabios_dgpu_id).rom-type := optionrom +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +pci$(stripped_vgabios_id).rom-align := 64 +pci$(stripped_second_vbios_id).rom-align := 64 +pci$(stripped_vgabios_dgpu_id).rom-align := 64 +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + ############################################################################### # common support for early assembly includes ############################################################################### 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/56579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I842c85288acd8f7ac99b127c94b1cf235e264ea2 Gerrit-Change-Number: 56579 Gerrit-PatchSet: 14 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58707 ) Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index e775606..76f4ec7 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,6 +16,12 @@ help Select this option to enable SPI DMA support. +# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# aligned. +config CBFS_CACHE_ALIGN + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58706 ) Change subject: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option ...................................................................... lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option This option will allow platforms to set the alignment of the cbfs_cache buffers. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 8, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58706 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/Kconfig M src/lib/cbfs.c 2 files changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 0f651b3..41a23b2 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -99,6 +99,12 @@ lookup must re-read the same CBFS directory entries from flash to find the respective file. +config CBFS_CACHE_ALIGN + int + default 8 + help + Sets the alignment of the buffers returned by the cbfs_cache. + config PAYLOAD_PRELOAD bool depends on COOP_MULTITASKING diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 7633fdf..1c79b65 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,7 +20,7 @@ #if ENV_STAGE_HAS_DATA_SECTION struct mem_pool cbfs_cache = - MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), sizeof(uint64_t)); + MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); #else struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); #endif @@ -29,7 +29,7 @@ { if (_preram_cbfs_cache != _postram_cbfs_cache) mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), - sizeof(uint64_t)); + CONFIG_CBFS_CACHE_ALIGN); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Gerrit-Change-Number: 58706 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Patrick Georgi (Code Review) 04 Nov '21

04 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... commonlib/mem_pool: Allow configuring the alignment AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/lib/cbfs.c 3 files changed, 21 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index 6c85397..42b5d1e 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -3,6 +3,7 @@ #ifndef _MEM_POOL_H_ #define _MEM_POOL_H_ +#include <assert.h> #include <stddef.h> #include <stdint.h> @@ -16,23 +17,23 @@ * were chosen to optimize for the CBFS cache case which may need two buffers * to map a single compressed file, and will free them in reverse order.) * - * The memory returned by allocations are at least 8 byte aligned. Note - * that this requires the backing buffer to start on at least an 8 byte - * alignment. + * You must ensure the backing buffer is 'alignment' aligned. */ struct mem_pool { uint8_t *buf; size_t size; + size_t alignment; uint8_t *last_alloc; uint8_t *second_to_last_alloc; size_t free_offset; }; -#define MEM_POOL_INIT(buf_, size_) \ +#define MEM_POOL_INIT(buf_, size_, alignment_) \ { \ .buf = (buf_), \ .size = (size_), \ + .alignment = (alignment_), \ .last_alloc = NULL, \ .second_to_last_alloc = NULL, \ .free_offset = 0, \ @@ -46,10 +47,15 @@ } /* Initialize a memory pool. */ -static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz) +static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz, + size_t alignment) { + assert(alignment); + assert((uintptr_t)buf % alignment == 0); + mp->buf = buf; mp->size = sz; + mp->alignment = alignment; mem_pool_reset(mp); } diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index c300c65..d82ab18 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -7,8 +7,11 @@ { void *p; - /* Make all allocations be at least 8 byte aligned. */ - sz = ALIGN_UP(sz, 8); + if (mp->alignment == 0) + return NULL; + + /* We assume that mp->buf started mp->alignment aligned */ + sz = ALIGN_UP(sz, mp->alignment); /* Determine if any space available. */ if ((mp->size - mp->free_offset) < sz) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 322f161..7633fdf 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -19,16 +19,17 @@ #include <timestamp.h> #if ENV_STAGE_HAS_DATA_SECTION -struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache)); +struct mem_pool cbfs_cache = + MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), sizeof(uint64_t)); #else -struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0); +struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); #endif static void switch_to_postram_cache(int unused) { if (_preram_cbfs_cache != _postram_cbfs_cache) - mem_pool_init(&cbfs_cache, _postram_cbfs_cache, - REGION_SIZE(postram_cbfs_cache)); + mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), + sizeof(uint64_t)); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 13 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021