coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow FSP-M to be relocated
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58984 ) Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated ...................................................................... drivers/intel/fsp2_0: Allow FSP-M to be relocated AMD platforms pass in the base address to cbfs tool: fspm.bin-options: -b $(CONFIG_FSP_M_ADDR) There is no technical reason not to allow FSP-M to be relocated when !XIP. By allowing this, we no longer need to pass in the base address into cbfstool when adding fspm.bin. This enables passing in the `--alignment` argument to cbfs tool instead. cbfstool currently has a check that prevents both `-b` and `-a` from being passed in. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 --- M src/commonlib/Makefile.inc M src/drivers/intel/fsp2_0/util.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58984/1 diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 53975bc..e8845d2 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -22,6 +22,7 @@ postcar-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c bootblock-y += cbfs.c diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 1128013..49934fe 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -163,8 +163,8 @@ if (!dest) return CB_ERR; - /* Don't allow FSP-M relocation. */ - if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) { + /* Don't allow FSP-M relocation when XIP. */ + if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) { printk(BIOS_ERR, "Unable to relocate FSP component!\n"); return CB_ERR; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 Gerrit-Change-Number: 58984 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... soc/amd/cezanne/romstage: Call preload_ramstage This will use the SPI DMA controller to preload ramstage while FSP-M executes. BUG=b:179699789 TEST=Boot nipperkin to OS and see 12ms reduction in boot time. | 8 - starting to load ramstage | 0 | 0.001 Δ( 0.00, 0.00%) | | 15 - starting LZMA decompress (ignore for x86) | 0.003 | 0.027 Δ( 0.02, 0.00%) | | 16 - finished LZMA decompress (ignore for x86) | 26.475 | 14.486 Δ(-11.99, -0.78%) | | 9 - finished loading ramstage | 0.548 | 0.559 Δ( 0.01, 0.00%) | We can achieve even more speed savings by having FSP-M call thread_yield() so we can preload more than 64KiB. Once we do that we can also switch the compression algorithm to LZ4 which will make the decompression time ~1ms. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I93ae358986059cdae6069421f4efba586235df51 --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58983/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 9f594d9..a220ab0 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -7,6 +7,7 @@ #include <console/uart.h> #include <device/device.h> #include <fsp/api.h> +#include <program_loading.h> #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> #include <string.h> @@ -160,4 +161,16 @@ fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(); + + /* + * At this point FSP-M has been loaded into RAM. If we were to start preloading before + * FSP-M was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-M read from SPI. Since FSP-M takes a while to execute and performs + * no SPI operations, we can preload while FSP-M executes. + * + * While FSP-M is executing, it's not currently possible to enqueue other transactions + * because FSP-M doesn't call `thread_yield()`. So the other preloads will start loading + * right after FSP-M completes. + */ + preload_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/lib/prog_loaders: Add preload_ramstage
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Martin Roth. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58982 ) Change subject: src/lib/prog_loaders: Add preload_ramstage ...................................................................... src/lib/prog_loaders: Add preload_ramstage This will enable preloading ramstage. By preloading the file into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush to OS and see 12ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 --- M Makefile.inc M src/include/program_loading.h M src/lib/prog_loaders.c 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/58982/1 diff --git a/Makefile.inc b/Makefile.inc index b784f3e..f14bc1e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1214,6 +1214,10 @@ $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +$(CONFIG_CBFS_PREFIX)/ramstage-align := 64 +endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 5b9a94d..ba42465 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -145,6 +145,13 @@ * RAMSTAGE LOADING * ************************/ +/* + * Asynchronously preloads ramstage. + * + * This should be called early on to allow ramstage to load before + * `run_ramstage` is called. + */ +void preload_ramstage(void); /* Run ramstage from romstage. */ void run_ramstage(void); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 1a361ea..671cd8a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -75,7 +75,15 @@ return rmodule_stage_load(&rmod_ram); } +void preload_ramstage(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + printk(BIOS_DEBUG, "Preloading ramstage\n"); + + cbfs_preload(CONFIG_CBFS_PREFIX "/ramstage"); +} void run_ramstage(void) { struct prog ramstage = -- To view, visit https://review.coreboot.org/c/coreboot/+/58982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Gerrit-Change-Number: 58982 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console/printk: Add console_mutex
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58981 ) Change subject: console/printk: Add console_mutex ...................................................................... console/printk: Add console_mutex Cooperative multitasking has only been used in ramstage. ramstage has spin locks enabled, while romstage and earlier don't. This means we can't rely on the console spin lock. This change adds a console mutex so printing can work correctly between threads in romstage. BUG=b:179699789 TEST=Start a thread in romstage and verify console output is not garbled Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5858bb18723f32f6b1e6ef0ed31906d7c79d3fec --- M src/console/printk.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58981/1 diff --git a/src/console/printk.c b/src/console/printk.c index 1ed39cb..4e630ea 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -13,6 +13,7 @@ #include <timer.h> DECLARE_SPIN_LOCK(console_lock) +struct thread_mutex console_mutex; #define TRACK_CONSOLE_TIME (!ENV_SMM && CONFIG(HAVE_MONOTONIC_TIMER)) @@ -81,6 +82,7 @@ return 0; spin_lock(&console_lock); + thread_mutex_lock(&console_mutex); console_time_run(); @@ -93,6 +95,7 @@ console_time_stop(); + thread_mutex_unlock(&console_mutex); spin_unlock(&console_lock); return i; -- To view, visit https://review.coreboot.org/c/coreboot/+/58981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5858bb18723f32f6b1e6ef0ed31906d7c79d3fec Gerrit-Change-Number: 58981 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Remove printk in thread_mutex_lock
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58980 ) Change subject: lib/thread: Remove printk in thread_mutex_lock ...................................................................... lib/thread: Remove printk in thread_mutex_lock While helpful, it will cause a dead lock with the next CL that adds a mutex in printk. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5a28f9c777fc0fb3bb73dff9e0974aeb6e210bba --- M src/lib/thread.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58980/1 diff --git a/src/lib/thread.c b/src/lib/thread.c index 7d5cdc5..4409d97 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -412,15 +412,9 @@ void thread_mutex_lock(struct thread_mutex *mutex) { - struct stopwatch sw; - - stopwatch_init(&sw); - while (mutex->locked) assert(thread_yield() == 0); mutex->locked = true; - - printk(BIOS_SPEW, "took %lu us to acquire mutex\n", stopwatch_duration_usecs(&sw)); } void thread_mutex_unlock(struct thread_mutex *mutex) -- To view, visit https://review.coreboot.org/c/coreboot/+/58980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a28f9c777fc0fb3bb73dff9e0974aeb6e210bba Gerrit-Change-Number: 58980 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/elog/elog: Add timestamps to elog_init
by Tim Wawrzynczak (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Raul Rangel, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58957 ) Change subject: drivers/elog/elog: Add timestamps to elog_init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Gerrit-Change-Number: 58957 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 21:12:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/elog/elog: Add timestamps to elog_init
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Paul Menzel. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58957 ) Change subject: drivers/elog/elog: Add timestamps to elog_init ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58957/comment/851dcdfb_f2b9f36c PS1, Line 14: <unknown> > Please paste the output of rebuild cbmem. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Gerrit-Change-Number: 58957 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 21:08:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/elog/elog: Add timestamps to elog_init
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58957 to look at the new patch set (#2). Change subject: drivers/elog/elog: Add timestamps to elog_init ...................................................................... drivers/elog/elog: Add timestamps to elog_init elog init requires doing a lot of SPI transactions. This change makes it clear how long we spend initializing elog. BUG=b:179699789 TEST=Boot guybrush and see elog init timestamps 114:started elog init 3,029,116 (88) 115:finished elog init 3,071,281 (42,165) Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/elog/elog.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/58957/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Gerrit-Change-Number: 58957 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/amd/agesa: fix out-of-bounds read
by Felix Held (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Jason Nein, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58803 ) Change subject: vc/amd/agesa: fix out-of-bounds read ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58803/comment/dadb2f37_1ca28987 PS5, Line 9: Fix the out-of-bounds read issue found by Coverity. would be good to add the coverity bug id in the commit message. https://review.coreboot.org/c/coreboot/+/55541/2//COMMIT_MSG#15 should be an example for that -- To view, visit https://review.coreboot.org/c/coreboot/+/58803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Gerrit-Change-Number: 58803 Gerrit-PatchSet: 5 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nein <finaljason(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 20:54:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Update 4.15 vboot supported boards
by Felix Held (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Martin Roth, Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58975 ) Change subject: Documentation/releases: Update 4.15 vboot supported boards ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: haven't checked if all devices in the list are still in the tree and if all devices with vboot support are listed File Documentation/security/vboot/list_vboot.md: https://review.coreboot.org/c/coreboot/+/58975/comment/e54ca0c0_99e98b66 PS1, Line 137: (Asus Chromebook C425, Flip C433, Flip C434) this probably shouldn't be removed; at least that comment is in the current source code, so i assume that it should be correct -- To view, visit https://review.coreboot.org/c/coreboot/+/58975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7 Gerrit-Change-Number: 58975 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 20:38:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021