coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow FSP-M to be relocated
by Felix Held (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58984 ) Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: ran a test on amd/mandolin with a picasso apu and it still boot successfully with this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/58984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 Gerrit-Change-Number: 58984 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 21:37:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Preload fspm.bin
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58988 to look at the new patch set (#2). Change subject: soc/amd/cezanne/romstage: Preload fspm.bin ...................................................................... soc/amd/cezanne/romstage: Preload fspm.bin FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.31 | 0.992 Δ( 0.68, 0.04%) | | 15 - starting LZMA decompress (ignore for x86) | 0.024 | 9.472 Δ( 9.45, 0.62%) | | 16 - finished LZMA decompress (ignore for x86) | 54.011 | 11.05 Δ(-42.96, -2.82%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/romstage.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/58988/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850b1576501753a355e7b23745e04802a0560387 Gerrit-Change-Number: 58988 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58986 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option ...................................................................... drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58986/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Gerrit-Change-Number: 58986 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58987 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps ...................................................................... drivers/intel/fsp2_0: Add preload_fspm and preload_fsps FSP is normally memmapped and then decompressed. The AMD SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58987/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Gerrit-Change-Number: 58987 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58985 to look at the new patch set (#2). Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin ...................................................................... soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Makefile.inc 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/58985/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Gerrit-Change-Number: 58985 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow FSP-M to be relocated
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58984 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated ...................................................................... drivers/intel/fsp2_0: Allow FSP-M to be relocated AMD platforms pass in the base address to cbfs tool: fspm.bin-options: -b $(CONFIG_FSP_M_ADDR) There is no technical reason not to allow FSP-M to be relocated when !XIP. By allowing this, we no longer need to pass in the base address into cbfstool when adding fspm.bin. This enables passing in the `--alignment` argument to cbfs tool instead. cbfstool currently has a check that prevents both `-b` and `-a` from being passed in. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 --- M src/commonlib/Makefile.inc M src/drivers/intel/fsp2_0/util.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58984/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 Gerrit-Change-Number: 58984 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/romstage: Preload fspm.bin
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58988 ) Change subject: soc/amd/cezanne/romstage: Preload fspm.bin ...................................................................... soc/amd/cezanne/romstage: Preload fspm.bin FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.31 | 0.992 Δ( 0.68, 0.04%) | | 15 - starting LZMA decompress (ignore for x86) | 0.024 | 9.472 Δ( 9.45, 0.62%) | | 16 - finished LZMA decompress (ignore for x86) | 54.011 | 11.05 Δ(-42.96, -2.82%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/romstage.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/58988/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index dbafa8c..6af0abb 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -207,6 +207,14 @@ hex default 0x40000 if CBFS_PRELOAD +config FSP_ALIGNMENT_FSP_S + int + default 64 if CBFS_PRELOAD + +config FSP_ALIGNMENT_FSP_M + int + default 64 if CBFS_PRELOAD + config RAMBASE hex default 0x10000000 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 9e863c3..4135cbc 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -23,6 +23,8 @@ /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); + preload_fspm(); + fsp_memory_init(acpi_is_wakeup_s3()); /* Fixup settings FSP-M should not be changing */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850b1576501753a355e7b23745e04802a0560387 Gerrit-Change-Number: 58988 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58987 ) Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps ...................................................................... drivers/intel/fsp2_0: Add preload_fspm and preload_fsps FSP is normally memmapped and then decompressed. The AMD SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58987/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 68b8470..c035452 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -32,7 +32,9 @@ }; /* Main FSP stages */ +void preload_fspm(void); void fsp_memory_init(bool s3wake); +void preload_fsps(void); void fsp_silicon_init(void); /* diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0c9fe97..6ea64ed 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -340,6 +340,16 @@ return (void *)fspm_begin; } +void preload_fspm(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS); + + cbfs_preload(CONFIG_FSP_M_CBFS); +} + void fsp_memory_init(bool s3wake) { struct range_entry prog_ranges[2]; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b3e60c2..0303fc9 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -230,6 +230,16 @@ load_done = 1; } +void preload_fsps(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS); + + cbfs_preload(CONFIG_FSP_S_CBFS); +} + void fsp_silicon_init(void) { timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); -- To view, visit https://review.coreboot.org/c/coreboot/+/58987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Gerrit-Change-Number: 58987 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58986 ) Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option ...................................................................... drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58986/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index ba93baa..a0e02a8 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -218,6 +218,16 @@ bool depends on !FSP_M_XIP +config FSP_ALIGNMENT_FSP_S + int + help + Sets the CBFS alignment for FSP-S + +config FSP_ALIGNMENT_FSP_M + int + help + Sets the CBFS alignment for FSP-M + config FSP_M_ADDR hex help diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 92ebf24..4b3fb05 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -65,6 +65,9 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) $(FSP_M_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),) +$(FSP_M_CBFS)-alignment := $(CONFIG_FSP_ALIGNMENT_FSP_M) +endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) @@ -75,6 +78,9 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),) +$(FSP_S_CBFS)-alignment := $(CONFIG_FSP_ALIGNMENT_FSP_S) +endif ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) -- To view, visit https://review.coreboot.org/c/coreboot/+/58986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Gerrit-Change-Number: 58986 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
by Raul Rangel (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58985 ) Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin ...................................................................... soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Makefile.inc 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/58985/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 8787441..8db0f6c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -53,8 +53,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) # ROMSIG Normally At ROMBASE + 0x20000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 45e9c80..7db4719 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -281,8 +281,6 @@ apu/amdfw_b-type := raw endif -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/58985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Gerrit-Change-Number: 58985 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021