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Change subject: UefiPayloadPkg: Map ESC to Boot Manager
......................................................................
Patch Set 2: Code-Review+2
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/edk2/+/58778 )
Change subject: UefiPayloadPkg: Enable PS2 keyboard by default
......................................................................
UefiPayloadPkg: Enable PS2 keyboard by default
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Change-Id: I33cc1654fbe2e578aa8f1485d755fc19b4db780d
Reviewed-on: https://review.coreboot.org/c/edk2/+/58778
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---
M UefiPayloadPkg/UefiPayloadPkg.dsc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
Sean Rhodes: Looks good to me, but someone else must approve
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 856d5ea..4aab59e 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -27,7 +27,7 @@
PCD_DYNAMIC_AS_DYNAMICEX = TRUE
DEFINE SOURCE_DEBUG_ENABLE = FALSE
- DEFINE PS2_KEYBOARD_ENABLE = FALSE
+ DEFINE PS2_KEYBOARD_ENABLE = TRUE
DEFINE UNIVERSAL_PAYLOAD = FALSE
#
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING
......................................................................
Patch Set 4: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58987 )
Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58987/comment/a1a1bb70_0fa475ed
PS2, Line 8:
: FSP is normally memmapped and then decompressed.
nit: this is only true in the non-XIP world, it cannot be decompressed "in-place" on Intel platforms.
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/58987/comment/cfb1bf1d_ec7f9067
PS2, Line 349:
nit: extra blank line
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/58987/comment/ef61c93e_54c2b635
PS2, Line 239:
same
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Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
seems fine to me, all intel FSP2.0 platforms are forced to use FSP-M XIP, so if that works for AMD 👍
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Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
......................................................................
Patch Set 2:
(2 comments)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58986/comment/7cfbd3b2_efd41b66
PS2, Line 69: alignment
Unless I missed a change in this train, shouldn't this be
`-align`
?
https://review.coreboot.org/c/coreboot/+/58986/comment/2d32c695_441e6a9d
PS2, Line 82: alignment
same?
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Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
also still works with this on a mandolin with picasso apu.
without having checked, i assume that we now can rip out everything around FSP_M_ADDR in soc/amd, so it would be good if you could look into that. that ould also avoid the problem that we need to reserve the maximum amount of memory a debug build of the fsp-m needs even though the release builds are significantly smaller
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