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Change subject: Documentation/releases: Update 4.15 release notes
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> would be good to also update the planned release date in coreboot-4.16-relnotes.md. […]
I would do that in this patch since it is announced here. Else, there would be two conflicting statements.
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Change subject: 3rdparty/amd_blobs: advance submodule pointer
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58989 )
Change subject: 3rdparty/amd_blobs: advance submodule pointer
......................................................................
3rdparty/amd_blobs: advance submodule pointer
This adds the following commits from the submodule:
* cezanne: Upgrade blobs to 1.0.0.5
* cezanne: Upgrade ABL to ver. 0x19036070
* cezanne: Upgrade SMU FW to 64.52.0
* cezanne: Upgrade SMU to 64.57.0
* cezanne: Update ABLs to 0x1A296070
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Id7b3f5d38d34c2714548dff92b7b83fb2628e936
---
M 3rdparty/amd_blobs
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58989/1
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
index 75c8cb5..f638765 160000
--- a/3rdparty/amd_blobs
+++ b/3rdparty/amd_blobs
@@ -1 +1 @@
-Subproject commit 75c8cb53516eb3e9a65e6b9bd69144e761eb0081
+Subproject commit f638765f17cdca735b69229f4f0479562bcb7526
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Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58987/comment/1c4ddc4f_92710f9a
PS2, Line 8:
: FSP is normally memmapped and then decompressed.
> nit: this is only true in the non-XIP world, it cannot be decompressed "in-place" on Intel platforms […]
Done
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/58987/comment/ef3160a2_77e6d75d
PS2, Line 349:
> nit: extra blank line
Done
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/58987/comment/a10d237a_b1609145
PS2, Line 239:
> same
Done
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Hello Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58987
to look at the new patch set (#3).
Change subject: drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
......................................................................
drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
3 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58987/3
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Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58986/comment/272275d7_6602cfa5
PS2, Line 69: alignment
> Unless I missed a change in this train, shouldn't this be […]
lol you are right. I guess I got lucky when I removed the `-b` since the file ended up 64 byte aligned when I tested.
https://review.coreboot.org/c/coreboot/+/58986/comment/414ed6d0_b0561484
PS2, Line 82: alignment
> same?
Done
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Hello Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
......................................................................
drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X option
This option will allow setting the FSP alignment in CBFS.
BUG=b:179699789
TEST=Boot with and without the option set and verify -a option was
passed.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58986/3
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Change subject: soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> also still works with this on a mandolin with picasso apu. […]
I wish we could, but we still need to tell the loader where to place the binary in RAM. If we had the cbmem stage cache active, then we totally could just use that. That might be a nice improvement for S3 resume....
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Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated
......................................................................
Patch Set 3:
(1 comment)
File src/commonlib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58984/comment/06ce0154_b5301eb7
PS2, Line 25: romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
> probably wouldn't be a one-liner any more, but i'd guard that with both CONFIG_PLATFORM_USES_FSP2_0 […]
Yeah, I debated but thought the single line looked less jarring. I'll add the guard since you had the same thought.
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Hello Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58984
to look at the new patch set (#3).
Change subject: drivers/intel/fsp2_0: Allow FSP-M to be relocated
......................................................................
drivers/intel/fsp2_0: Allow FSP-M to be relocated
AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
---
M src/commonlib/Makefile.inc
M src/drivers/intel/fsp2_0/util.c
2 files changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58984/3
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