coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/common/block: Add spi_hw mutex
by Marshall Dawson (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Julius Werner, Rob Barnes, Karthik Ramasubramanian, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58926 ) Change subject: soc/amd/common/block: Add spi_hw mutex ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I assume flash reads during DMA should be avoided too? If so, are you guaranteeing that by using DMA to load cbfs files? And again, if so, it seems there could be the potential for FSP to read it. For example we pass in a pointer to MRC cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/58926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Gerrit-Change-Number: 58926 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 23:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Andrey Pronin, Raul Rangel, Marshall Dawson, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58870 to look at the new patch set (#5). Change subject: [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. BUG=b:200578885 TEST=Multiple cycles of S0i3 suspend resume. ~50ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/verstage.c M src/security/vboot/vboot_common.h M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 9 files changed, 137 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Enable CBFS_PRELOAD
by Marshall Dawson (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Rob Barnes, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58961 ) Change subject: soc/amd/cezanne: Enable CBFS_PRELOAD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Gerrit-Change-Number: 58961 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 23:30:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Rob Barnes, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Andrey Pronin, Raul Rangel, Marshall Dawson, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58870 to look at the new patch set (#4). Change subject: [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... [WIP]soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. BUG=b:200578885 TEST=Multiple cycles of S0i3 suspend resume. ~50ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/verstage.c M src/security/vboot/vboot_common.h M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 9 files changed, 140 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/thread: Switch to using types.h
by Felix Held (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58990 ) Change subject: lib/thread: Switch to using types.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd Gerrit-Change-Number: 58990 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 23:26:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint/kconfig_lint: Fix off by one error that missed last line
by Martin Roth (Code Review) 06 Nov '21

06 Nov '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58992 ) Change subject: util/lint/kconfig_lint: Fix off by one error that missed last line ...................................................................... util/lint/kconfig_lint: Fix off by one error that missed last line This error prevented the last line of the Kconfig tree from being printed or added to the output file. This is a significant problem if you try to use the generated file as the kconfig source, because it changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to NO. This causes the build to stop working. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a --- M util/lint/kconfig_lint 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/58992/1 diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index a3495ce..32bf92d 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1312,7 +1312,7 @@ return unless $print_full_output; - for ( my $i = 0 ; $i < $#wholeconfig ; $i++ ) { + for ( my $i = 0 ; $i <= $#wholeconfig ; $i++ ) { my $line = $wholeconfig[$i]; chop( $line->{text} ); -- To view, visit https://review.coreboot.org/c/coreboot/+/58992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a Gerrit-Change-Number: 58992 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in edk2[coreboot-stable202108]: MdeModulePkg: load boot logo into BGRT table
by Matt DeVillier (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Patrick Rudolph. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58786 ) Change subject: MdeModulePkg: load boot logo into BGRT table ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > If there's official code already: how much effort is it to backport it? That would make this commit […] I'll give it a look and report back -- To view, visit https://review.coreboot.org/c/edk2/+/58786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I726fd7a9deb9ba5f8e351ce24834fc627acc4542 Gerrit-Change-Number: 58786 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 23:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add ASYNC_FILE_LOADING
by Marshall Dawson (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58861 ) Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Gerrit-Change-Number: 58861 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 23:07:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: Testing coreboot callbacks from FSP
by Raul Rangel (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58991 ) Change subject: WIP: Testing coreboot callbacks from FSP ...................................................................... WIP: Testing coreboot callbacks from FSP Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I02818987a574f14f790d34f4f0af6b993c520727 --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/fsp_s_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h M src/vendorcode/amd/fsp/cezanne/FspsUpd.h 4 files changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58991/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index a220ab0..ccd5435 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -11,6 +11,7 @@ #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> #include <string.h> +#include <thread.h> #include <types.h> #include "chip.h" @@ -64,6 +65,12 @@ mcfg->fch_ioapic_id = FCH_IOAPIC_ID; } +static void my_yield(void) +{ + printk(BIOS_ERR, "Got called from FSP-M!\n"); + thread_yield(); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -158,6 +165,8 @@ else mcfg->usb_phy = NULL; + mcfg->void_function = (uintptr_t)my_yield; + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(); diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index 60f3942..9550f7e 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -5,16 +5,24 @@ #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> +#include <thread.h> static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } +static void my_yield(void) +{ + thread_yield(); +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { FSP_S_CONFIG *scfg = &supd->FspsConfig; + scfg->void_function = (uintptr_t)my_yield; + fsp_assign_vbios_upds(scfg); /* diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42..294e896 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -27,7 +27,8 @@ /** Offset 0x007C**/ uint32_t serial_reserved; /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; - /** Offset 0x0359**/ uint8_t pcie_reserved[51]; + /** Offset 0x0359**/ uint32_t void_function; + /** Offset 0x035D**/ uint8_t pcie_reserved2[47]; /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 3ac52c0..0bb3343 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -11,8 +11,10 @@ typedef struct __packed { /** Offset 0x0020**/ uint32_t vbios_buffer; - /** Offset 0x0024**/ uint64_t gop_reserved; - /** Offset 0x002C**/ uint32_t reserved1; + /** Offset 0x0024**/ uint16_t gop_edp_init_delay; + /** Offset 0x0026**/ uint16_t gop_reserved1; + /** Offset 0x0028**/ uint32_t gop_reserved2; + /** Offset 0x002C**/ uint32_t void_function; /** Offset 0x0030**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/58991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02818987a574f14f790d34f4f0af6b993c520727 Gerrit-Change-Number: 58991 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Switch to using types.h
by Raul Rangel (Code Review) 06 Nov '21

06 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58990 ) Change subject: lib/thread: Switch to using types.h ...................................................................... lib/thread: Switch to using types.h thread_mutex uses bool. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd --- M src/include/thread.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/58990/1 diff --git a/src/include/thread.h b/src/include/thread.h index 62c6283..19b69fa 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -5,7 +5,7 @@ #include <arch/cpu.h> #include <bootstate.h> #include <commonlib/bsd/cb_err.h> -#include <stdint.h> +#include <types.h> struct thread_mutex { bool locked; -- To view, visit https://review.coreboot.org/c/coreboot/+/58990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26b37d3e38852d72fcb6ff07ed578b0879e55dd Gerrit-Change-Number: 58990 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021