coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/strago: Fix some CHROMEOS guards
by Kyösti Mälkki (Code Review) 06 Nov '21

06 Nov '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58924 ) Change subject: intel/strago: Fix some CHROMEOS guards ...................................................................... Patch Set 2: (1 comment) File src/mainboard/intel/strago/Makefile.inc: https://review.coreboot.org/c/coreboot/+/58924/comment/0c1ab663_aaf1ae5b PS2, Line 5: all-y += chromeos.c Should continue to guard this file -- To view, visit https://review.coreboot.org/c/coreboot/+/58924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Gerrit-Change-Number: 58924 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 06 Nov 2021 10:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55367/comment/7c98953e_93747eb3 PS43, Line 36: the user could enable : PchPseShellEnabled flag > If the user shall be able to enable it, make it a Kconfig Answered below, this is a mainboard related config. File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/5fff51a1_3f4c783b PS43, Line 216: It is required to allocate at least 512 KiB for PSE FW and 256 KiB for : PSE config data > Please add a dot/period at the end of the sentence. Done https://review.coreboot.org/c/coreboot/+/55367/comment/7d2f221e_c0b22b12 PS43, Line 217: FSP will append PSE config data to memory region : right after PSE FW memory region > Please add a dot/period at the end of the sentence. Done File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/db7fd54b_ab9aeec5 PS43, Line 57: pse.bin-align := 0x1000 : pse.bin-compression := lzma > We had this discussion already earlier and I do not see a real reason for this alignment as well. Thanks for the input. Done. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/53bac03c_c4a5c80b PS2, Line 480: : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseDmaSbInterruptEnable[0] = 0x0; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseLogOutputChannel = 0x3; //Set the log output to PSE UART 2 : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : : /* : * Set to predefined GPIO Pin Muxing. If the device is disabled, it : * will not be consumed by FSP. : */ : params->PchPseTgpio6PinMux = 0x8B81A203; //GPIO pin mux for GPP_T3 : params->PchPseTgpio7PinMux = 0x8B82A40B; //GPIO pin mux for GPP_T11 : params->PchPseTgpio8PinMux = 0x8B80A607; //GPIO pin mux for GPP_B7 : params->PchPseTgpio9PinMux = 0x8B80A808; //GPIO pin mux for GPP_B8 : params->PchPseTgpio10PinMux = 0x8B86AA07; //GPIO pin mux for GPP_U7 : params->PchPseTgpio11PinMux = 0x8B86AC0B; //GPIO pin mux for GPP_U11 : params->PchPseTgpio12PinMux = 0x8B86AE13; //GPIO pin mux for GPP_U19 : params->PchPseTgpio13PinMux = 0x8B85B00C; //GPIO pin mux for GPP_D12 : params->PchPseTgpio14PinMux = 0x8B90B214; //GPIO pin mux for GPP_E20 : params->PchPseTgpio15PinMux = 0x8B90B403; //GPIO pin mux for GPP_E3 : params->PchPseTgpio16PinMux = 0x8B90B607; //GPIO pin mux for GPP_E7 : params->PchPseTgpio17PinMux = 0x8B90B80F; //GPIO pin mux for GPP_E15 : params->PchPseTgpio18PinMux = 0x8B90BA06; //GPIO pin mux for GPP_E6 : params->PchPseTgpio19PinMux = 0x8B8DBC01; //GPIO pin mux for GPP_C1 : params->PchPsePwmPinMux[8] = 0x7B706604; //GPIO pin mux for GPP_E4 : params->PchPsePwmPinMux[9] = 0x7B706805; //GPIO pin mux for GPP_E5 : params->PchPsePwmPinMux[10] = 0x7B706A06; //GPIO pin mux for GPP_E6 : params->PchPsePwmPinMux[11] = 0x7B706C11; //GPIO pin mux for GPP_E17 : params->PchPsePwmPinMux[12] = 0x7B706E12; //GPIO pin mux for GPP_E18 : params->PchPsePwmPinMux[13] = 0x7B707013; //GPIO pin mux for GPP_E19 : params->PchPsePwmPinMux[14] = 0x4B64720A; //GPIO pin mux for GPP_H10 : params->PchPsePwmPinMux[15] = 0x4B64740B; //GPIO pin mux for GPP_H11 : params->PchPseSpiMosiPinMux[1] = 0x4B852003; //GPIO pin mux for GPP_D3 : params->PchPseSpiMisoPinMux[1] = 0x4B853002; //GPIO pin mux for GPP_D2 : params->PchPseSpiClkPinMux[1] = 0x4B854001; //GPIO pin mux for GPP_D1 : params->PchPseSpiCs0PinMux[1] = 0x4B855000; //GPIO pin mux for GPP_D0 : params->PchPseI2sTxPinMux[0] = 0x1B702610; //GPIO pin mux for GPP_E16 : params->PchPseI2sRxPinMux[0] = 0x1B70160F; //GPIO pin mux for GPP_E15 : params->PchPseI2sSfrmPinMux[0] = 0x1B704614; //GPIO pin mux for GPP_E21 : params->PchPseI2sSclkPinMux[0] = 0x1B703615; //GPIO pin mux for GPP_E20 > What about requesting GpioOverride from the FSP team? The EHL FSP is unfortunately wont have extra features or modifications unless bug fixes :( File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/722d11cc_6773e54c PS43, Line 373: CONFIG_PSE_BUFFER_SIZE > > beware that the file-size function currently has a bug where it can get stuck when an empty string […] Wow great input here guys. Thanks Werner, Arther, Felix and Angel for your kind review! :) -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 09:33:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (7 comments) File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/de72b8e1_81df7623 PS47, Line 198: config PSE_IMAGE > I would rename it to something like "ENABLE_PSE" or the like since with this switch you decide wheth […] good suggestion. https://review.coreboot.org/c/coreboot/+/55367/comment/d76371f7_057a0a11 PS47, Line 211: config PSE_FW_FILE_SIZE : hex "Memory buffer (KiB) for PSE FW image" : default 0x200 : help : It is recommended to allocate at least 512 KiB for PSE FW : : config PSE_CONFIG_BUFFER_SIZE : hex "Memory buffer (KiB) for PSE config data" : default 0x100 : help : It is recommended to allocate at least 256 KiB for PSE config : data (FSP will append PSE config data to memory region right : after PSE FW memory region) > Make these dependent on "PSE_IMAGE so that they disappear if the PSE is disabled. Done File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/92b602d5_fbe64da2 PS48, Line 204: added to CBFS and loaded by FSP to run PSE. > trailing whitespace Please fix. File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/33d911fe_20af0d9e PS47, Line 58: ifeq ($(CONFIG_PSE_IMAGE),y) : ifeq ($(call int-gt,\ : $(call file-size,$(CONFIG_PSE_IMAGE_FILE))\ : $(shell printf "%d" $(CONFIG_PSE_FW_FILE_SIZE))),\ : 1) > You are comparing CONFIG_PSE_FW_FILE_SIZE, which in in KB units, to the real size of the PSE file in […] This is great. Thanks Werner! File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/42f43d9c_e44a39d1 PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; > Well, this is about enabling/disabling it. […] Thanks Michael. I will still prefer to keep this PSE console shell enabling to mainboard devicetree as this is mainboard related, as some board might choose to build PSE FW without the PSE console shell function. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/b123d673_d36a4a6d PS47, Line 373: #define psebufsize (CONFIG_PSE_FW_FILE_SIZE + CONFIG_PSE_CONFIG_BUFFER_SIZE) * KiB > Move this define somewhere on top of the file? And all defined symbols should be written in upper-ca […] Removed the define and just added into the line as our conversation suggested. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/c8d639e6_a0b468a6 PS48, Line 373: static char psefwbuf[(CONFIG_PSE_FW_FILE_SIZE +\ > Avoid unnecessary line continuations Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 09:28:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55367 to look at the new patch set (#49). Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enables the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 170 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by build bot (Jenkins) (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Patrick Rudolph, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 48: (2 comments) File src/soc/intel/elkhartlake/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132494): https://review.coreboot.org/c/coreboot/+/55367/comment/5f3cd12a_a1f359a1 PS48, Line 204: added to CBFS and loaded by FSP to run PSE. trailing whitespace File src/soc/intel/elkhartlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132494): https://review.coreboot.org/c/coreboot/+/55367/comment/f4a7a9a9_8b18b96d PS48, Line 373: static char psefwbuf[(CONFIG_PSE_FW_FILE_SIZE +\ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 48 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 09:19:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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2013

coreboot-gerrit November 2021