coreboot-gerrit November 2021

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Change in coreboot[master]: google/beltino,jecht: Refactor ChromeOS GPIOs
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58998 ) Change subject: google/beltino,jecht: Refactor ChromeOS GPIOs ...................................................................... google/beltino,jecht: Refactor ChromeOS GPIOs Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/onboard.h M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/onboard.h 4 files changed, 37 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58998/1 diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 6ed8e3a..2d35e75 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -8,9 +8,7 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -27,6 +25,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -45,11 +53,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); /* Developer: Virtual */ diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 2cced23..8bd21ce 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -16,6 +16,12 @@ /* WLAN wake is GPIO 10 */ #define WLAN_WAKE_GPIO 10 +/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + +/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + /* IT8772F defs */ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 70bc5d7..4588e31 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -12,9 +12,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h" -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -30,6 +27,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -48,11 +55,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); /* Developer: Virtual */ diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index 1c37d72..a6ba80a 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -37,4 +37,10 @@ #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) #define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + +/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Gerrit-Change-Number: 58998 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: samsung/lumpy,stumpy: Refactor ChromeOS GPIOs
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58997 ) Change subject: samsung/lumpy,stumpy: Refactor ChromeOS GPIOs ...................................................................... samsung/lumpy,stumpy: Refactor ChromeOS GPIOs Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/onboard.h M src/mainboard/samsung/stumpy/chromeos.c A src/mainboard/samsung/stumpy/onboard.h 4 files changed, 45 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58997/1 diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index c414fd7..b9e59af 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -9,9 +9,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 24 -#define GPIO_REC_MODE 42 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -42,6 +40,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -60,10 +68,10 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index d281e2e..d43e1bae 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -12,4 +12,10 @@ #define BOARD_TRACKPAD_IRQ 21 #define BOARD_TRACKPAD_WAKE_GPIO 0x1b +/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ +#define GPIO_SPI_WP 24 + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 489d066..91fabbd 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -8,9 +8,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 68 -#define GPIO_REC_MODE 42 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -38,6 +36,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -56,10 +64,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); + /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/stumpy/onboard.h b/src/mainboard/samsung/stumpy/onboard.h new file mode 100644 index 0000000..602d456 --- /dev/null +++ b/src/mainboard/samsung/stumpy/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef STUMPY_ONBOARD_H +#define STUMPY_ONBOARD_H + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + +/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ +#define GPIO_SPI_WP 68 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2 Gerrit-Change-Number: 58997 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ChromeOS: Add missing <commonlib/helpers.h>
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58996 ) Change subject: ChromeOS: Add missing <commonlib/helpers.h> ...................................................................... ChromeOS: Add missing <commonlib/helpers.h> Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 64 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58996/1 diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index e5f3b5c..501fb96 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index bb0ffeea..4b1d022 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 6f8f242..2be0b6d 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <security/tpm/tis.h> diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2274ff7..77a396b 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index a33caca..6ed8e3a 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -3,6 +3,7 @@ #include <device/pci_ops.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index e0a13b8..710c11b 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 356e97b..0b431a2 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 748e06e..93e2df0 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <security/tpm/tis.h> diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 3f0937f..d6350b8 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 14efdc3..cc2f9b5 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 7599295..1edbc64 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 0d75ac3..6e8b68a 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index dbdb273..9fdbe77 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -5,6 +5,7 @@ #include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index e3a9cd3..c1db7e5 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 73eae78..1c5d5b7 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index a9456e4..ba4ea1b 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4e744f1..d1fe8fb 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 2987e91..82c7407 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -3,6 +3,7 @@ #include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <drivers/i2c/ww_ring/ww_ring.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index acd4cd6..a12b05b 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 688c0dd..fd3b988 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <security/tpm/tis.h> diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index 6131322..d9ac0a6 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 354d839..90438b4 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index a116675..7f7f500 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include "board.h" diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 5cfe9df..70bc5d7 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <device/device.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index a386dd6..b8f0e49 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -3,6 +3,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 3f15a3f..1615328 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <security/tpm/tis.h> diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 540803c..0bc7897 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index c827c7d..bfa9a4b 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 7fe877b..4d77c8a 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include <gpio.h> diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 7fe877b..4d77c8a 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include <gpio.h> diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 7fe877b..4d77c8a 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include <gpio.h> diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 9e7af27..36e801b 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -3,6 +3,7 @@ #include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include "gpio.h" diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index d0ceabc..413789b 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 03b0d47..66bcbbf 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <device/device.h> diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index ebbfdd3..ec3868e 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index c9b91ad..90f6bf7 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index f9a1718..35f92c8 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index a45ccdd..db56739 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 3dc9f19..e1b9635 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 4fffd45..a213a6d 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 13a69bc..956e949 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include "gpio.h" diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 69f0fcc..dc18fb8 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -3,6 +3,7 @@ #include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <drivers/i2c/ww_ring/ww_ring.h> diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 07fdee3..09e6cf2 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 9006000..984f5a4 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <bootmode.h> #include "board.h" #include <security/tpm/tis.h> diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index cdea2ce..40c2d12 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <gpio.h> diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index a3fe3f4..0ef5c43 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 7dcf7dc..27f62b9 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include "board.h" diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 5f87821..63d9f1e 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index cfb55a7..863ad57 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 85807a1..32e7cfc 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2b14014..04300e4 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 1e02e3d..9ab3efa 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index e0f5faf..254ac95 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 7878a2a..c047285 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 8a8bc42..d147b41 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -5,6 +5,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 320f92a..f46e2c0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index df01242..45925a3 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3a99e25..ba9393f 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 052191f..c387ed8 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index ad23ea1..4e99684 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index cb9af47..664d396 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 996eee2..ec4c9ee 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index aa96153..c414fd7 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <device/device.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index c8fbf98..489d066 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/58996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Gerrit-Change-Number: 58996 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Martin Roth (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (1 comment) Patchset: PS49: > Well, since the PSE is a ARM SoC and running it's own OS, ofc it's runtime persistent. […] We were told in the leadership meeting where this binary was discussed that it did not have access to memory or other x86 resources. Some PCI devices are controlled by either the x86 or the PSE, but can't be accessed by both at the same time. Sheng was going to verify that this was the case, in which case, it's just like any other embedded controller in a laptop. We don't print warnings for those, so we probably shouldn't for this either. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 21:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (1 comment) Patchset: PS49: > (the host OS I mean) Well, since the PSE is a ARM SoC and running it's own OS, ofc it's runtime persistent. The question here is how it is connected to the main SoC and what accesses are possible (memory access like ME?). -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 19:13:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Nico Huber (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (1 comment) Patchset: PS49: > It's not just another blob. It's runtime persistent and Martin brought the security […] (the host OS I mean) -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 18:43:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Nico Huber (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (1 comment) Patchset: PS49: > dropped my -2, since it's optional, even though I don't like more blobs... […] It's not just another blob. It's runtime persistent and Martin brought the security aspect up on the ML. I'd actually be surprised if there is any security for the OS. Maybe we should add a warning about that as well? in Kconfig? printed after the build? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 18:43:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (1 comment) Patchset: PS49: dropped my -2, since it's optional, even though I don't like more blobs... However, Werner is working on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 18:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Removed Code-Review-2 by Michael Niewöhner <foss(a)mniewoehner.de> -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: drvs/intel/gma/acpi: Add methods to use MBOX3
by Nico Huber (Code Review) 06 Nov '21

06 Nov '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27711 ) Change subject: drvs/intel/gma/acpi: Add methods to use MBOX3 ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > I have few Desktop and laptops that gets bsod acpi_bios_error in MS windows with the cause of "using […] The line makes 0x2000 bytes (8KiB) of RAM accessible to the ASL code around it. This reserved RAM region is used for communication between the ASL code and the OS graphics driver. I don't see anything wrong with it nor a way to do it differently. I've seen the size specified in a document from 2008. Might be a bug in the windows graphics driver. Have you tried Linux; if it complains about anything in dmesg? What boards do you have? -- To view, visit https://review.coreboot.org/c/coreboot/+/27711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51554c819148336b204d28972cbf775a10c3fb8a Gerrit-Change-Number: 27711 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: xin hua wang <xinhuawang0101(a)gmail.com> Gerrit-Comment-Date: Sat, 06 Nov 2021 16:22:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: xin hua wang <xinhuawang0101(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021