coreboot-gerrit November 2021

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Change in coreboot[master]: pci_mmio_cfg: Move guard around pci_s_* functions to x86
by Nico Huber (Code Review) 07 Nov '21

07 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58331 ) Change subject: pci_mmio_cfg: Move guard around pci_s_* functions to x86 ...................................................................... Patch Set 4: (1 comment) File src/arch/x86/include/arch/pci_ops.h: https://review.coreboot.org/c/coreboot/+/58331/comment/5d10ede9_ab70a950 PS2, Line 7: MMCONF_SUPPORT > Ok. I would assume that we need to rename MMCONF_BASE_ADDRESS and MMCONF_LENGTH to MMCONF_ECAM... […] Sounds good, maybe not patch set 1 exactly, but something like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/58331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Gerrit-Change-Number: 58331 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Nov 2021 16:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: pci_mmio_cfg: Move guard around pci_s_* functions to x86
by Nico Huber (Code Review) 07 Nov '21

07 Nov '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Furquan Shaikh, Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58331 to look at the new patch set (#4). Change subject: pci_mmio_cfg: Move guard around pci_s_* functions to x86 ...................................................................... pci_mmio_cfg: Move guard around pci_s_* functions to x86 There is no platform in our tree that requires the PCI MMIO ops but doesn't want the pci_s_* definitions. The only case where we include the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to use MMIO is on older x86 platforms, so move the guard there. Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/arch/x86/include/arch/pci_ops.h M src/include/device/pci_mmio_cfg.h 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58331/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Gerrit-Change-Number: 58331 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build ...
by Nico Huber (Code Review) 07 Nov '21

07 Nov '21

Attention is currently required from: Bill XIE, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51671 ) Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time ...................................................................... Patch Set 22: Code-Review+1 (1 comment) File src/arch/x86/bootblock.ld: https://review.coreboot.org/c/coreboot/+/51671/comment/67393243_b15dfa5f PS22, Line 57: _ID_SECTION_END - _ECFW_PTR > It can only happen when someone messes up the code. Exactly that. And ECFW_PTR_ADDR is a Kconfig, so we kind of have to expect that it might change. Which makes me realize the following: If the Kconfig is used in arch/x86/ then it should be declared in arch/x86/Kconfig, along with a help text that describes this constraint (i.e. must be below the reset vector or FIT pointer if present). The EC Kconfig should only set the default number. -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 22 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sun, 07 Nov 2021 15:50:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices
by Nico Huber (Code Review) 07 Nov '21

07 Nov '21

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58603 ) Change subject: [RFC]cpu/x86/mp_init.c: Copy BSP chip_info to AP devices ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Sorry, tried to review this, but the cpu_info() function starts with a comment I don't understand / makes no sense to me: /* We use a #if because we don't want to mess with the &s below. */ The `&s` is aligned up by the stack size, hence we should get the same result as long is `s` is on the stack, shouldn't we? What do I miss? -- To view, visit https://review.coreboot.org/c/coreboot/+/58603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9b83b096da07821b7c1f9b36b3e311cd751718 Gerrit-Change-Number: 58603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 07 Nov 2021 14:32:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59000 ) Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... mb/google,intel: Add ChromeOS GPIOs to onboard.h Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 94 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59000/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59004 ) Change subject: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs ...................................................................... google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs Low-level GPIOs should not depend of late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/sarien/chromeos.c 3 files changed, 21 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59004/1 diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 9fdbe77..7ed2dbc 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -33,24 +33,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPIO_PCH_WP); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_REC_MODE); } void mainboard_chromeos_acpi_generate(void) @@ -63,11 +53,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -93,7 +78,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index c1db7e5..2ab1d6f 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -31,24 +31,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -61,11 +51,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -91,7 +76,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index e1b9635..2acfbd0 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -29,24 +29,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -59,11 +49,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -89,7 +74,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Gerrit-Change-Number: 59004 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/butterfly: Refactor get_recovery_mode_switch()
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59003 ) Change subject: google/butterfly: Refactor get_recovery_mode_switch() ...................................................................... google/butterfly: Refactor get_recovery_mode_switch() Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/butterfly/chromeos.c 1 file changed, 4 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59003/1 diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 43b9e78..117d2d2 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -13,8 +11,6 @@ #include "ec.h" #include "onboard.h" -#define FORCE_RECOVERY_MODE 0 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -42,23 +38,13 @@ return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; } +/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ int get_recovery_mode_switch(void) { - int ec_rec_mode = 0; + if (ENV_RAMSTAGE) + return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); - if (FORCE_RECOVERY_MODE) { - printk(BIOS_DEBUG, "FORCING RECOVERY MODE.\n"); - return 1; - } - - if (ENV_RAMSTAGE) { - if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) - ec_rec_mode = 1; - - printk(BIOS_DEBUG, "RECOVERY MODE FROM EC: %x\n", ec_rec_mode); - } - - return ec_rec_mode; + return 0; } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Gerrit-Change-Number: 59003 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: samsung/lumpy,stumpy: Add get_power_switch()
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59002 ) Change subject: samsung/lumpy,stumpy: Add get_power_switch() ...................................................................... samsung/lumpy,stumpy: Add get_power_switch() Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/onboard.h M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/onboard.h 4 files changed, 22 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/59002/1 diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index bbae938..5447e11 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -19,9 +19,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), @@ -30,7 +27,7 @@ {100, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -54,6 +51,13 @@ return ec_read(0x83) & 1; } +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index d43e1bae..dd57076 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -18,4 +18,8 @@ /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ #define GPIO_REC_MODE 42 +#ifndef __ACPI__ +int get_power_switch(void); +#endif + #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 91fabbd..447aa0d 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -15,9 +15,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), @@ -27,7 +24,7 @@ {100, ACTIVE_HIGH, 1, "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -46,6 +43,13 @@ return !get_gpio(GPIO_REC_MODE); } +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/stumpy/onboard.h b/src/mainboard/samsung/stumpy/onboard.h index 602d456..b89c20c 100644 --- a/src/mainboard/samsung/stumpy/onboard.h +++ b/src/mainboard/samsung/stumpy/onboard.h @@ -9,4 +9,6 @@ /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ #define GPIO_SPI_WP 68 +int get_power_switch(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Gerrit-Change-Number: 59002 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: samsung/lumpy: Add get_lid_switch()
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59001 ) Change subject: samsung/lumpy: Add get_lid_switch() ...................................................................... samsung/lumpy: Add get_lid_switch() Change-Id: Ib360a6fa00d0ebda4635b96f1b671a66c1ca11c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/samsung/lumpy/chromeos.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59001/1 diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index b9e59af..bbae938 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -21,14 +21,13 @@ { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - u8 lid = ec_read(0x83); struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, - {100, ACTIVE_HIGH, lid & 1, "lid"}, + {100, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, @@ -50,6 +49,11 @@ return !get_gpio(GPIO_REC_MODE); } +int get_lid_switch(void) +{ + return ec_read(0x83) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/59001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib360a6fa00d0ebda4635b96f1b671a66c1ca11c1 Gerrit-Change-Number: 59001 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 07 Nov '21

07 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59000 ) Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... mb/google,intel: Add ChromeOS GPIOs to onboard.h Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 89 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59000/1 diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 77a396b..cd1db11 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -7,8 +7,7 @@ #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 58 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h new file mode 100644 index 0000000..6d4ff28 --- /dev/null +++ b/src/mainboard/google/auron/onboard.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AURON_ONBOARD_H +#define AURON_ONBOARD_H + +/* SPI Write protect is GPIO 58 */ +#define CROS_WP_GPIO 58 + +#endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 0b431a2..43b9e78 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -11,9 +11,8 @@ #include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include "onboard.h" -#define WP_GPIO 6 -#define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index b8da862..2e780c9 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -16,4 +16,10 @@ /* 0x00: White LINK LED and Amber ACTIVE LED */ #define BUTTERFLY_NIC_LED_MODE 0x00 + +/* SPI write protect, active low */ +#define WP_GPIO 6 + +#define DEVMODE_GPIO 54 + #endif diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 0bc7897..370388d 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -26,12 +26,12 @@ int get_write_protect_state(void) { - return get_gpio(57); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index 7e351e4..efcda92 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -16,4 +16,8 @@ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a #define BOARD_TOUCHSCREEN_IRQ 22 +#define GPIO_REC_MODE 9 + +#define GPIO_SPI_WP 57 + #endif diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 66bcbbf..4cabf91 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -9,9 +9,9 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <ec/compal/ene932/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" + +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -20,7 +20,7 @@ struct lb_gpio chromeos_gpios[] = { /* Lid switch GPIO active high (open). */ - {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, @@ -34,32 +34,27 @@ int get_lid_switch(void) { - return get_gpio(15); + return get_gpio(GPIO_LID); } int get_write_protect_state(void) { - return !get_gpio(70); + return !get_gpio(GPIO_SPI_WP); } int get_recovery_mode_switch(void) { - u8 gpio = !get_gpio(68); - /* GPIO68, active low. For Servo support - * Treat as active high and let the caller invert if needed. */ - printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio); - - return gpio; + return !get_gpio(GPIO_REC_MODE); } static int parrot_ec_running_ro(void) { - return !get_gpio(68); + return get_recovery_mode_switch(); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index 9bece67..d564c56 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -9,4 +9,13 @@ #define BOARD_TRACKPAD_IRQ_PVT 20 #define BOARD_TRACKPAD_WAKE_GPIO 0x1c +#define GPIO_LID 15 + +/* GPIO68, active low. For Servo support + * Treat as active high and let the caller invert if needed. */ +#define GPIO_REC_MODE 68 + + +#define GPIO_SPI_WP 70 + #endif diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a213a6d..7142940 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -19,12 +19,12 @@ int get_write_protect_state(void) { - return get_gpio(58); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 6b7fdb2..a1f30fd 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -23,4 +23,7 @@ #define PEPPY_BOARD_VERSION_PROTO 0 #define PEPPY_BOARD_VERSION_EVT 1 +/* Write protect is active high */ +#define GPIO_SPI_WP 58 + #endif diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 09e6cf2..41dd51a 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -3,15 +3,9 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> - #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include <ec/quanta/it8518/ec.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,7 +29,7 @@ int get_write_protect_state(void) { - return !get_gpio(7); + return !get_gpio(GPIO_SPI_WP); } int get_lid_switch(void) @@ -76,8 +70,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index a31dffd..2f9b92d 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -11,4 +11,7 @@ #define XHCI_PREBOOT 0 // No PreOS boot support #define XHCI_STREAMS 1 // Sure, lets have streams +/* Write protect is active low */ +#define GPIO_SPI_WP 7 + #endif diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 04300e4..555e3d5 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -12,7 +11,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -32,18 +31,18 @@ * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return get_gpio(69); + return get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(22); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h new file mode 100644 index 0000000..66812a5 --- /dev/null +++ b/src/mainboard/intel/baskingridge/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASKINGRIDGE_ONBOARD_H +#define BASKINGRIDGE_ONBOARD_H + +/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */ +#define GPIO_REC_MODE 69 + +/* Write protect is active low */ +#define GPIO_SPI_WP 22 + +#endif diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 254ac95..192e177 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -12,7 +11,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -29,18 +28,18 @@ int get_recovery_mode_switch(void) { /* Recovery: GPIO22, active low */ - return !get_gpio(22); + return !get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(48); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h new file mode 100644 index 0000000..658ad83 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EMERALDLAKE2_ONBOARD_H +#define EMERALDLAKE2_ONBOARD_H + +/* Recovery: GPIO22, active low */ +#define GPIO_REC_MODE 22 + +/* Write protect is active low */ +#define GPIO_SPI_WP 48 + +#endif diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 4e99684..531029d 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -6,10 +6,7 @@ #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#define WP_GPIO GP_E_22 - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index bc2e7a2..d8af569 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -29,6 +29,9 @@ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ #define BOARD_SCI_GPIO_INDEX 15 + +#define WP_GPIO GP_E_22 + /* Trackpad: Gpio index in N bank */ #define BOARD_TRACKPAD_GPIO_INDEX 18 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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