coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Nico Huber (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: (18 comments) Patchset: PS49: > From a technical point of view this patch looks good so far. Bold words, made me look ;) File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/8a65e7e6_86274cf9 PS49, Line 202: that is designed as an Asymmetric : Multi-Processing (AMP) system AIUI, Intel describes the whole SoC as AMP. Some cores are in the CPU complex and x86 and the PSE is in the PCH and ARM, hence asymmetric. Or did I get it wrong? https://review.coreboot.org/c/coreboot/+/55367/comment/4e37deea_31cd7260 PS49, Line 203: be *to* be? https://review.coreboot.org/c/coreboot/+/55367/comment/5515618a_39677622 PS49, Line 204: added to CBFS and loaded by FSP to run PSE. Please add a sentence that this is only a temporary solution. File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/3435adf3_d40fa05b PS49, Line 52: CONFIG_PSE_IMAGE Did you mean CONFIG_PSE_ENABLE? https://review.coreboot.org/c/coreboot/+/55367/comment/34037902_bc93f3d1 PS49, Line 61: $(shell printf "%d" $(call int-shift-left,\ This looks like there is no line break necessary? https://review.coreboot.org/c/coreboot/+/55367/comment/5655ccdf_8192c952 PS49, Line 66: The way this is implemented (if PSE_ENABLE then the file is required) does not allow to enable the PSE and adding the file manually with cbfstool, and neither to build test the option (without the file in the repository). The latter needs to be fixed. Also, it would make it impossible for a board port to provide correct Kconfig defaults when, for instance, the PSE is needed to make the MACs work. The usually solution is to have a separate option to add the file and print a warning at the end of the build when this option wasn't set. File src/soc/intel/elkhartlake/chip.h: https://review.coreboot.org/c/coreboot/+/55367/comment/f4250d06_dff6faa4 PS49, Line 482: runtime Runtime of coreboot or the whole time, i.e. OS? https://review.coreboot.org/c/coreboot/+/55367/comment/c57a5c63_8e14283c PS49, Line 485: enum pse_device_ownership PseDmaOwn[3]; : enum pse_device_ownership PseUartOwn[6]; : enum pse_device_ownership PseHsuartOwn[4]; : enum pse_device_ownership PseQepOwn[4]; : enum pse_device_ownership PseI2cOwn[8]; : enum pse_device_ownership PseI2sOwn[2]; : enum pse_device_ownership PseSpiOwn[4]; : enum pse_device_ownership PseSpiCs0Own[4]; : enum pse_device_ownership PseSpiCs1Own[4]; : enum pse_device_ownership PseCanOwn[2]; : enum pse_device_ownership PsePwmOwn; : enum pse_device_ownership PseAdcOwn; : /* PSE devices sideband interrupt: Disable (0) / Enable (1) */ : bool PseDmaSbIntEn[3]; : bool PseUartSbIntEn[6]; : bool PseQepSbIntEn[4]; : bool PseI2cSbIntEn[8]; : bool PseI2sSbIntEn[2]; : bool PseSpiSbIntEn[4]; : bool PseCanSbIntEn[2]; : bool PseLh2PseSbIntEn; : bool PsePwmSbIntEn; : bool PseAdcSbIntEn; : /* PSE PWM native function: Disable (0) / Enable (1) */ : bool PsePwmPinEn[16]; : /* PSE Console Shell */ : bool PseShellEn; There shouldn't be any CamelCase. But it looks like half of the file does it wrong already? I guess one of the downsides of not having the initial commit reviewed. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/01ba5a62_65bacf72 PS49, Line 383: /* PSE devices config */ I don't understand this comment. https://review.coreboot.org/c/coreboot/+/55367/comment/a516cce0_7cb492c2 PS49, Line 384: /* PSE DMA */ That's literally what the indentifier says, such a comment is just distraction. https://review.coreboot.org/c/coreboot/+/55367/comment/dce38d4a_cd1ea496 PS49, Line 385: FSP_ARRAY_LOAD What is this? It hides the implementation. Hiding memcpy() seems dangerous as it discards all type checking. https://review.coreboot.org/c/coreboot/+/55367/comment/2f604b0d_7005bc8a PS49, Line 423: Nit, missing line break after the /* https://review.coreboot.org/c/coreboot/+/55367/comment/81ac00e8_a4b3ffe1 PS49, Line 426: * as it still allows user to change these params from devicetree. That's not true. The devicetree can't change it because the devicetree values are overridden here, AFAICS. Where is this "minimum requirement" documented? Is it specific to the blob you used to test it? https://review.coreboot.org/c/coreboot/+/55367/comment/2586a640_c62819f1 PS49, Line 436: 0x0 Why is this hex? https://review.coreboot.org/c/coreboot/+/55367/comment/f99dd5b5_f0aecc8b PS49, Line 438: 0x3 Why is this hex? https://review.coreboot.org/c/coreboot/+/55367/comment/3c4d08c8_72dfddf3 PS49, Line 438: // Please use common comment style. File src/soc/intel/elkhartlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/35b12bee_b4218549 PS49, Line 127: m_cfg->PchPseEnable = CONFIG(PSE_ENABLE); Could we check for the file in CBFS here, so we could still boot if it's missing? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 16:04:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Patrick Rudolph, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 49: Code-Review+1 (1 comment) Patchset: PS49: From a technical point of view this patch looks good so far. For the ones who do not like the PSE and yet another blob, it can be disabled with the consequence of loosing some peripherals (of which are two network MACs). I am in discussions with Intel on what can be done in terms of opening the PSE to the community but I doubt this discussions will be finished soon. Once there is a result that can be shared I will write to the mailinglist. In the meantime, if there are no technical issues with this particular commit, I would like to get it merged. Michael, are you OK with this approach? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 49 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 06 Nov 2021 14:33:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu/power9: add file structure for power9, implement SCOM access
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Felix Singer, Krystian Hebel, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57078 ) Change subject: src/cpu/power9: add file structure for power9, implement SCOM access ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57078/comment/e83356ad_16d26345 PS10, Line 7: /* > not needed here. please remove that. Done Patchset: PS11: Removed `/*` from message of one commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/57078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Gerrit-Change-Number: 57078 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 06 Nov 2021 14:11:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external: add skiboot (for QEMU/Power9)
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson. Hello build bot (Jenkins), Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58656 to look at the new patch set (#3). Change subject: payloads/external: add skiboot (for QEMU/Power9) ...................................................................... payloads/external: add skiboot (for QEMU/Power9) Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/mainboard/emulation/qemu-power9.md M payloads/Makefile.inc M payloads/external/.gitignore M payloads/external/Makefile.inc A payloads/external/skiboot/Kconfig A payloads/external/skiboot/Kconfig.name A payloads/external/skiboot/Makefile M src/mainboard/emulation/qemu-power9/Kconfig 8 files changed, 105 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58656/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Gerrit-Change-Number: 58656 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57084 to look at the new patch set (#13). Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... src/arch/ppc64/*: pass FDT address to payload It's available in %r3 in bootblock and needs to be passed first to romstage, then to ramstage, where it's put into CMBEM to be read on starting payload. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/boot.c M src/arch/ppc64/bootblock_crt0.S A src/arch/ppc64/fdt.h M src/arch/ppc64/stages.c 4 files changed, 85 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 13 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/ppc64/boot.c: handle non-OPD entry point
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57083 to look at the new patch set (#12). Change subject: arch/ppc64/boot.c: handle non-OPD entry point ...................................................................... arch/ppc64/boot.c: handle non-OPD entry point Change-Id: I309be370d66a808b355241fcee880883631f38ce Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/boot.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/57083/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/57083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309be370d66a808b355241fcee880883631f38ce Gerrit-Change-Number: 57083 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Paul Menzel, Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57082 to look at the new patch set (#12). Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... src/mainboard/emulation/qemu-power9: require hb-mode=on "hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> --- M src/arch/ppc64/rom_media.c M src/arch/ppc64/stages.c M src/mainboard/emulation/qemu-power9/memlayout.ld 3 files changed, 32 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/57082/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: add RAM detection
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Timothy Pearson, Sergii Dmytruk. Hello build bot (Jenkins), Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57081 to look at the new patch set (#11). Change subject: src/mainboard/emulation/qemu-power9: add RAM detection ...................................................................... src/mainboard/emulation/qemu-power9: add RAM detection Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> --- M src/mainboard/emulation/qemu-power9/cbmem.c M src/mainboard/emulation/qemu-power9/mainboard.c M src/mainboard/emulation/qemu-power9/memlayout.ld M src/mainboard/emulation/qemu-power9/romstage.c 4 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/57081/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/57081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7 Gerrit-Change-Number: 57081 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ppc64/arch/mmio.h: ignore HRMOR and inhibit cache
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Krystian Hebel, Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Krystian Hebel, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57080 to look at the new patch set (#11). Change subject: ppc64/arch/mmio.h: ignore HRMOR and inhibit cache ...................................................................... ppc64/arch/mmio.h: ignore HRMOR and inhibit cache Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/arch/ppc64/include/arch/mmio.h 1 file changed, 67 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/57080/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/57080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d Gerrit-Change-Number: 57080 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
by Sergii Dmytruk (Code Review) 06 Nov '21

06 Nov '21

Attention is currently required from: Timothy Pearson, Sergii Dmytruk. Hello build bot (Jenkins), Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57079 to look at the new patch set (#11). Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard ...................................................................... src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard Add initial implementation for booting on QEMU POWER9 emulation Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- A Documentation/mainboard/emulation/qemu-power9.md A configs/config.emulation_qemu_power9 A src/mainboard/emulation/qemu-power9/Kconfig A src/mainboard/emulation/qemu-power9/Kconfig.name A src/mainboard/emulation/qemu-power9/Makefile.inc A src/mainboard/emulation/qemu-power9/board.fmd A src/mainboard/emulation/qemu-power9/board_info.txt A src/mainboard/emulation/qemu-power9/cbmem.c A src/mainboard/emulation/qemu-power9/devicetree.cb A src/mainboard/emulation/qemu-power9/mainboard.c A src/mainboard/emulation/qemu-power9/memlayout.ld A src/mainboard/emulation/qemu-power9/romstage.c 12 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/57079/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/57079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Gerrit-Change-Number: 57079 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021