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I'd like you to reexamine a change. Please visit
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Change subject: src/cpu/power9: add file structure for power9, implement SCOM access
......................................................................
src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/arch/ppc64/include/arch/byteorder.h
M src/arch/ppc64/include/arch/io.h
M src/cpu/Makefile.inc
A src/cpu/power9/Kconfig
A src/cpu/power9/Makefile.inc
A src/cpu/power9/power9.c
A src/cpu/power9/scom.c
A src/include/cpu/power/scom.h
A src/include/cpu/power/spr.h
9 files changed, 411 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: ChromeOS: Fix <vc/google/chromeos/chromeos.h>
......................................................................
ChromeOS: Fix <vc/google/chromeos/chromeos.h>
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/intel/fsp1_1/romstage.c
M src/ec/google/chromeec/vboot_storage.c
M src/mainboard/google/auron/ec.c
M src/mainboard/google/brya/variants/anahera/gpio.c
M src/mainboard/google/brya/variants/brask/gpio.c
M src/mainboard/google/brya/variants/felwinter/gpio.c
M src/mainboard/google/brya/variants/gimble/gpio.c
M src/mainboard/google/brya/variants/kano/gpio.c
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/redrix/gpio.c
M src/mainboard/google/brya/variants/taeko/gpio.c
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/dedede/variants/blipper/gpio.c
M src/mainboard/google/dedede/variants/boten/gpio.c
M src/mainboard/google/dedede/variants/gooey/gpio.c
M src/mainboard/google/dedede/variants/metaknight/gpio.c
M src/mainboard/google/deltaur/variants/baseboard/gpio.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/foster/mainboard.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/nyan/mainboard.c
M src/mainboard/google/nyan_big/mainboard.c
M src/mainboard/google/nyan_blaze/mainboard.c
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/google/veyron/mainboard.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/mainboard.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/mainboard.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
M src/mainboard/intel/strago/ec.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/vpd_calibration.c
50 files changed, 21 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58923/11
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Change subject: intel/strago: Fix some CHROMEOS guards
......................................................................
intel/strago: Fix some CHROMEOS guards
Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/intel/strago/Makefile.inc
M src/mainboard/intel/strago/chromeos.c
2 files changed, 7 insertions(+), 8 deletions(-)
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 49:
(1 comment)
Patchset:
PS46:
> > @Nico I wonder how you want to integrate that minimal sample exactly. That minimal sample code should be in the Zephyr project IMO, so we might add it to 3rdparty/Zephyr and build it like other external stuff (payloads, libgfxinit). Is that what you have in mind?
>
> IMHO, Zephyr would be complete overkill. And I've also talked to Werner, it's
> not what they want. I would add a stub to coreboot that is enough to boot. So
> when needed (e.g. for these ethernet MACs) we can easily add configuration
> code to it. If somebody wants to do more with the PSE beside silicon init,
> we can still discuss that later ;)
>
> From a coreboot perspective, we could treat the PSE as just another AP.
> Unfortunately the only one that has access to all the registers of its
> peripherals and hence needs to do part of ramstage's job or at least act
> as a broker.
>
> Of course, having the Zephyr code published would answer what we have to
> do to talk to FSP and get these MACs running.
I fully agree. The idea was just to have *something* this minimal stub can be based on.
However, for booting nothing is required, when the UPD is set (PchPseEnable). So, what about another change adding this UPD (set to 0) first?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 49:
(1 comment)
Patchset:
PS46:
> @Nico I wonder how you want to integrate that minimal sample exactly. That minimal sample code should be in the Zephyr project IMO, so we might add it to 3rdparty/Zephyr and build it like other external stuff (payloads, libgfxinit). Is that what you have in mind?
IMHO, Zephyr would be complete overkill. And I've also talked to Werner, it's
not what they want. I would add a stub to coreboot that is enough to boot. So
when needed (e.g. for these ethernet MACs) we can easily add configuration
code to it. If somebody wants to do more with the PSE beside silicon init,
we can still discuss that later ;)
From a coreboot perspective, we could treat the PSE as just another AP.
Unfortunately the only one that has access to all the registers of its
peripherals and hence needs to do part of ramstage's job or at least act
as a broker.
Of course, having the Zephyr code published would answer what we have to
do to talk to FSP and get these MACs running.
--
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Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 49: Code-Review-2
(1 comment)
Patchset:
PS46:
> Thanks again Nico for your kind understanding. […]
I wonder if it's possible for Intel to just push the current state to a public repo to officially make it available for interested people? Upstreaming to Zephyr is another topic and I'm open for discussion of the -2 if we at least have the code in public.
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