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Hello build bot (Jenkins), Michał Żygowski, Patrick Rudolph, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50298
to look at the new patch set (#4).
Change subject: [WIP] soc/intel/braswell: Use acpigen for wifi_regulatory_domain()
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[WIP] soc/intel/braswell: Use acpigen for wifi_regulatory_domain()
Change-Id: I012dc849b69c6c504f005a71c885ab230f3b795a
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/cyan/dsdt.asl
M src/mainboard/intel/strago/dsdt.asl
M src/mainboard/protectli/vault_bsw/dsdt.asl
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/globalnvs.asl
M src/soc/intel/braswell/include/soc/nvs.h
D src/soc/intel/common/acpi/wifi.asl
7 files changed, 2 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/50298/4
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 )
Change subject: soc/amd/cezanne/romstage: Call preload_ramstage
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Question in CB:58926
Just to add to that, We pass in the DRAM MRC address on S0 boots, and use the mmap address on S3 boots:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
So in the S0 case there won't be any contention. For the S3 case, I'm thinking we should preload the MRC cache using the SPI DMA controller since it's faster.
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Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56322/comment/95a58d6b_16742d88
PS6, Line 147: + 1
> Will this be confusing to the (console) reader?
I either need to `current_block + 1` or `total_blocks - 1`, I figured block 0/100 read like we haven't read any block.
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Change subject: soc/amd/common/block: Add spi_hw mutex
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I assume flash reads during DMA should be avoided too? If so, are you guaranteeing that by using DM […]
Flash reads using the SPI registers will also be problematic. This CL should handle that case. Thought I don't think we really have anything that does that. mmap reads are fine during a DMA transaction. The LPC arbitration logic handles that correctly. As for FSP reading the MRC cache, this will be a mmap read, so it will be fine.
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Change subject: doc/mb/ocp: update Delta Lake documentation
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Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Thanks for the update!
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Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56322/comment/1e7f4386_5275878d
PS6, Line 147: + 1
Will this be confusing to the (console) reader?
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