coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

1 participants
5514 discussions

Change in coreboot[master]: Revert "mb/google/brya: Disable crashlog on brya"
by Name of user not set (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik. vagdevi.p(a)intel.com has removed Furquan Shaikh from this change. ( https://review.coreboot.org/c/coreboot/+/57950 ) Change subject: Revert "mb/google/brya: Disable crashlog on brya" ...................................................................... Removed reviewer Furquan Shaikh. -- To view, visit https://review.coreboot.org/c/coreboot/+/57950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f257c67cb078a633eb860b3872a13d55778b69e Gerrit-Change-Number: 57950 Gerrit-PatchSet: 1 Gerrit-Owner: vagdevi.p(a)intel.com Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: soc/intel/dnv_ns: correct size of GPE0 registers in FADT
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58086 ) Change subject: soc/intel/dnv_ns: correct size of GPE0 registers in FADT ...................................................................... soc/intel/dnv_ns: correct size of GPE0 registers in FADT There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/acpi.c 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index aa59aa8..574d106 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -101,7 +101,6 @@ /* Control Registers - Length */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -149,14 +148,6 @@ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; } static acpi_tstate_t denverton_tss_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/58086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Gerrit-Change-Number: 58086 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Always enable SpeedStep
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57669 ) Change subject: soc/intel/denverton_ns: Always enable SpeedStep ...................................................................... soc/intel/denverton_ns: Always enable SpeedStep When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: King Sumo <kingsumos(a)gmail.com> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 4 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, approved King Sumo: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 10e79be..95f164d 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -90,12 +90,10 @@ /* Enable Turbo */ enable_turbo(); - /* Enable speed step. */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - } + /* Enable speed step. Always ON.*/ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= SPEED_STEP_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/57669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Gerrit-Change-Number: 57669 Gerrit-PatchSet: 5 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Always enable SpeedStep
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57669 ) Change subject: soc/intel/denverton_ns: Always enable SpeedStep ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Gerrit-Change-Number: 57669 Gerrit-PatchSet: 4 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 04:40:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58112 ) Change subject: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Gerrit-Change-Number: 58112 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 04:37:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl2: Set the suitable SPD data
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58111 ) Change subject: mb/siemens/mc_ehl2: Set the suitable SPD data ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58111/comment/98fcb63a_2068b88d PS1, Line 9: On this mainboard are Micron MT53D512M32D2NP modules. Since there are : other DRAM modules on mc_ehl1, the SPD data file must be adjusted here : accordingly. We do not use the traditional DRMA modules here but have memory down with different memory chips. Maybe we should adapt the wording to avoid confusions? -- To view, visit https://review.coreboot.org/c/coreboot/+/58111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Gerrit-Change-Number: 58111 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 04:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add HECI Reset flow in the CSE driver
by Ravindra (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Sridhar Siricilla, Paul Menzel, Patrick Rudolph. Ravindra has uploaded a new patch set (#3) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/55363 ) Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ...................................................................... soc/intel/common: Add HECI Reset flow in the CSE driver The patch adds HECI Reset flow in the CSE driver. This is required as part of the HECI Interface initialization in order to put the host and CSE into a known good state for communication. This change is required to send HECI commands before DRAM Init. TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Gerrit-Change-Number: 55363 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya: Disable crashlog on brya
by Name of user not set (Code Review) 07 Oct '21

07 Oct '21

vagdevi.p(a)intel.com has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/56654 ) Change subject: mb/google/brya: Disable crashlog on brya ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/56654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6 Gerrit-Change-Number: 56654 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

1 0

Change in coreboot[master]: Revert "mb/google/brya: Disable crashlog on brya"
by Name of user not set (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57950 to review the following change. Change subject: Revert "mb/google/brya: Disable crashlog on brya" ...................................................................... Revert "mb/google/brya: Disable crashlog on brya" This reverts commit 8326fc01645ed084033cc894d23b1d3b00df2ef7. Reason for revert: To check PMT driver behavior Change-Id: I5f257c67cb078a633eb860b3872a13d55778b69e --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/57950/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 72059ae..f11a998 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -5,6 +5,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_CRASHLOG config BOARD_GOOGLE_PRIMUS bool "-> Primus" -- To view, visit https://review.coreboot.org/c/coreboot/+/57950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f257c67cb078a633eb860b3872a13d55778b69e Gerrit-Change-Number: 57950 Gerrit-PatchSet: 1 Gerrit-Owner: vagdevi.p(a)intel.com Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: Add PsysPmax setting to 145W
by Ryan Lin (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Hou-hsun Lee, Kane Chen. Ryan Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58104 ) Change subject: mb/google/brya: Add PsysPmax setting to 145W ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58104/comment/b6798129_0f2f9d2a PS1, Line 13: Ensure > ensure done. -- To view, visit https://review.coreboot.org/c/coreboot/+/58104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Gerrit-Change-Number: 58104 Gerrit-PatchSet: 2 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 04:06:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2021