coreboot-gerrit October 2021

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Change in coreboot[master]: ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:20:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add new API for USB-C mux handling
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58059 ) Change subject: ec/google/chromeec: Add new API for USB-C mux handling ...................................................................... ec/google/chromeec: Add new API for USB-C mux handling Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux related information. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a8e4f6..e27ad9e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1565,6 +1565,42 @@ return 0; } +/* + * Obtain any USB-C mux data needed for the specified port + * in: physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error +*/ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info) +{ + uint8_t mux_flags; + uint8_t dp_pin_mode; + bool ufp, dbg_acc, active_cable; + + if (google_chromeec_usb_get_pd_mux_info(port, &mux_flags) < 0) { + printk(BIOS_ERR, "Port C%d: get_pd_mux_info failed\n", port); + return -1; + } + + if (google_chromeec_usb_pd_get_info(port, &ufp, &dbg_acc, + &active_cable, &dp_pin_mode) < 0) { + printk(BIOS_ERR, "Port C%d: pd_control failed\n", port); + return -1; + } + + mux_info->usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_info->dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_info->polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_info->hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_info->hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_info->ufp = !!ufp; + mux_info->dbg_acc = !!dbg_acc; + mux_info->cable = !!active_cable; + mux_info->dp_pin_mode = dp_pin_mode; + + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index a06dfa1..f4090fe 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -9,6 +9,7 @@ #include <types.h> #include <device/device.h> #include "ec_commands.h" +#include <device/usbc_mux.h> /* Fill in base and size of the IO port resources used. */ void google_chromeec_ioport_range(uint16_t *base, size_t *size); @@ -48,6 +49,13 @@ * specified port. * Return: 0 on success, -1 on error */ int google_chromeec_typec_control_enter_dp_mode(int port); +/* + * Obtain any USB-C mux data needed for the specified port + * in: int port physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error + */ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Gerrit-Change-Number: 58059 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Add APIs for USB-C DP ALT mode
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: ec/google/chromeec: Add APIs for USB-C DP ALT mode ...................................................................... ec/google/chromeec: Add APIs for USB-C DP ALT mode Add API to allow AP to send the command to EC to enter DP ALT mode and API to wait for DP HPD event. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system you will find below message in the coreboot log with or without USB-C display connected: 'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'. Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 54 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 9086693..5a8e4f6 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1508,6 +1508,33 @@ return 0; } +int google_chromeec_typec_control_enter_dp_mode(int port) +{ + if (!google_chromeec_check_feature(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY)) + return 0; + + struct ec_params_typec_control typec_control = { + .port = port, + .command = TYPEC_CONTROL_COMMAND_ENTER_MODE, + .mode_to_enter = TYPEC_MODE_DP, + }; + + struct chromeec_command cmd = { + .cmd_code = EC_CMD_TYPEC_CONTROL, + .cmd_version = 0, + .cmd_data_in = &typec_control, + .cmd_size_in = sizeof(typec_control), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + return 0; +} + /** * Check for the current mux state in EC. Flags representing the mux state found * in ec_commands.h @@ -1632,6 +1659,25 @@ return ret; } +int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms) +{ + uint8_t mux_flags; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + do { + google_chromeec_usb_get_pd_mux_info(port, &mux_flags); + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "HPD not ready after %ldms. Abort.\n", timeout_ms); + return -1; + } + mdelay(100); + } while (!(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED)); + printk(BIOS_INFO, "HPD ready after %lu ms\n", stopwatch_duration_msecs(&sw)); + + return 0; +} + int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) { struct chromeec_command cmd = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 6fa58a9..a06dfa1 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -40,6 +40,14 @@ * >=1: Bitmask of the ports that DP device is connected */ int google_chromeec_wait_for_displayport(long timeout_ms); +/* Poll (up to `timeout_ms` ms) for a Hot-Plug Detect (HPD) + * event on the specified port. + * Return: 0 on HPD ready, -1 on timeout */ +int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms); +/* Send command to EC to request to enter DisplayPort ALT mode on the + * specified port. + * Return: 0 on success, -1 on error */ +int google_chromeec_typec_control_enter_dp_mode(int port); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 17 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Add APIs for USB-C DP ALT mode
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Brandon Breitenstein, Curtis Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: ec/google/chromeec: Add APIs for USB-C DP ALT mode ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 16 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:18:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Update some PD and DisplayPort APIs
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58058 ) Change subject: ec/google/chromeec: Update some PD and DisplayPort APIs ...................................................................... ec/google/chromeec: Update some PD and DisplayPort APIs 1. Update google_chromeec_pd_get_amode() to return bitmask. 2. Update google_chromeec_wait_for_displayport() to handle the updated return value of google_chromeec_pd_get_amode(). 3. Drop google_chromeec_pd_get_amode() from ec.h and make it static because it's not used outside of ec.c. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 29 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 650fd14..9086693 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1542,9 +1542,10 @@ * Check if EC/TCPM is in an alternate mode or not. * * @param svid SVID of the alternate mode to check - * @return 0: Not in the mode. -1: Error. 1: Yes. + * @return 0: Not in the mode. -1: Error. + * >=1: bitmask of the ports that are in the mode. */ -int google_chromeec_pd_get_amode(uint16_t svid) +static int google_chromeec_pd_get_amode(uint16_t svid) { struct ec_response_usb_pd_ports resp; struct chromeec_command cmd = { @@ -1557,6 +1558,7 @@ .cmd_dev_index = 0, }; int i; + int ret = 0; if (google_chromeec_command(&cmd) < 0) return -1; @@ -1582,12 +1584,12 @@ if (google_chromeec_command(&cmd) < 0) return -1; if (resp2.svid == svid) - return 1; + ret |= BIT(i); svid_idx++; } while (resp2.svid); } - return 0; + return ret; } #define USB_SID_DISPLAYPORT 0xff01 @@ -1595,20 +1597,31 @@ /** * Wait for DisplayPort to be ready * - * @param timeout Wait aborts after <timeout> ms. - * @return 1: Success or 0: Timeout. + * @param timeout_ms Wait aborts after <timeout_ms> ms. + * @return -1: Error. 0: Timeout. + * >=1: Bitmask of the ports that DP device is connected */ -int google_chromeec_wait_for_displayport(long timeout) +int google_chromeec_wait_for_displayport(long timeout_ms) { struct stopwatch sw; + int ret = 0; printk(BIOS_INFO, "Waiting for DisplayPort\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT) != 1) { + stopwatch_init_msecs_expire(&sw, timeout_ms); + while (1) { + ret = google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT); + if (ret > 0) + break; + + if (ret < 0) { + printk(BIOS_ERR, "Can't get alternate mode!\n"); + return ret; + } + if (stopwatch_expired(&sw)) { printk(BIOS_WARNING, "DisplayPort not ready after %ldms. Abort.\n", - timeout); + timeout_ms); return 0; } mdelay(200); @@ -1616,7 +1629,7 @@ printk(BIOS_INFO, "DisplayPort ready after %lu ms\n", stopwatch_duration_msecs(&sw)); - return 1; + return ret; } int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ebb7ae2..6fa58a9 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -26,7 +26,6 @@ int google_ec_running_ro(void); enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); -int google_chromeec_pd_get_amode(uint16_t svid); /* Check for the current mux state in EC * in: int port physical port number of the type-c port * out: uint8_t flags representing the status of the mux such as @@ -36,7 +35,11 @@ /* Returns data role and type of device connected */ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, bool *active_cable, uint8_t *dp_mode); -int google_chromeec_wait_for_displayport(long timeout); +/* Poll (up to `timeout_ms` ms) for DisplayPort to be ready + * Return: -1: Error. 0: Timeout. + * >=1: Bitmask of the ports that DP device is connected + */ +int google_chromeec_wait_for_displayport(long timeout_ms); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Gerrit-Change-Number: 58058 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Update some PD and DisplayPort APIs
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58058 ) Change subject: ec/google/chromeec: Update some PD and DisplayPort APIs ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: NM gerrit was being silly -- To view, visit https://review.coreboot.org/c/coreboot/+/58058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Gerrit-Change-Number: 58058 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:17:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Update some PD and DisplayPort APIs
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58058 ) Change subject: ec/google/chromeec: Update some PD and DisplayPort APIs ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Needs to be rebased -- To view, visit https://review.coreboot.org/c/coreboot/+/58058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Gerrit-Change-Number: 58058 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:17:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Update google_chromeec_usb_pd_control()
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58057 ) Change subject: ec/google/chromeec: Update google_chromeec_usb_pd_control() ...................................................................... ec/google/chromeec: Update google_chromeec_usb_pd_control() Add parameter `active_cable` to obtain the cable type (active or passive) which is needed for USB-C configuration for some SoCs (at least Intel TGL and ADL), change the function name to google_chromeec_usb_pd_get_info() for better understanding. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 5 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 29d0411..650fd14 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1477,7 +1477,8 @@ return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, + bool *active_cable, uint8_t *dp_mode) { struct ec_params_usb_pd_control pd_control = { .port = port, @@ -1501,6 +1502,7 @@ *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *active_cable = !!(resp.control_flags & USB_PD_CTRL_ACTIVE_CABLE); *dp_mode = resp.dp_mode; return 0; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 743651b..ebb7ae2 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -34,8 +34,8 @@ */ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); /* Returns data role and type of device connected */ -int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, - uint8_t *dp_mode); +int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, + bool *active_cable, uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Gerrit-Change-Number: 58057 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/device: Generic interface for USB-C mux operations
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58002 ) Change subject: include/device: Generic interface for USB-C mux operations ...................................................................... include/device: Generic interface for USB-C mux operations Create a generic interface to allow any of the EC or other drivers to provide set of USB-C mux operations. Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/include/device/usbc_mux.h 1 file changed, 69 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h new file mode 100644 index 0000000..e395d2d --- /dev/null +++ b/src/include/device/usbc_mux.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* struct to hold all USB-C mux related variables */ +struct usbc_mux_info { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* 0 = Passive cable, 1 = Active cable */ + bool polarity; /* Polarity of connected device. 0 = Normal, 1 = Flipped */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; /* 0 = DFP, 1 = UFP */ + bool dbg_acc; /* Debug Accessory. 0 = Disable, 1 = Enable */ + uint8_t dp_pin_mode; /* DP pin assignments + 0h: Reserved. + 1h: Pin Assignment A. + 2h: Pin Assignment B. + 3h: Pin Assignment C. + 4h: Pin Assignment D. + 5h: Pin Assignment E. + 6h: Pin Assignment F. + 7-Fh: Reserved. */ +}; +struct usbc_mux_ops { + /* + * Get mux information on a given port. + * + * Return value: + * -1 = error + * 0 = success + */ + int (*get_mux_info)(int port, struct usbc_mux_info *info); +}; + +struct usbc_dp_ops { + /* + * Wait up to `timeout_ms` for DP connection to be ready on any available port. + * + * Return value: + * -1 = error + * 0 = no DP connection + * <bit mask> = mask for ports that are ready in DP mode. + */ + int (*wait_for_connection)(long timeout_ms); + + /* + * Enter DP mode on a given `port`. + * + * Return value: + * -1 = error + * 0 = success + */ + int (*enter_dp_mode)(int port); + + /* + * Wait up to `timeout_ms` for HPD on a given port. + * + * Return value: + * -1 = timeout + * 0 = success + */ + int (*wait_for_hpd)(int port, long timeout_ms); +}; + +struct usbc_ops { + struct usbc_mux_ops mux_ops; + struct usbc_dp_ops dp_ops; +}; + +const struct usbc_ops *usbc_get_ops(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/58002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Gerrit-Change-Number: 58002 Gerrit-PatchSet: 6 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Disable unused i2s pins for BT offload
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Sugnan Prabhu S, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58137 ) Change subject: mb/google/brya: Disable unused i2s pins for BT offload ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Gerrit-Change-Number: 58137 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:02:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021