coreboot-gerrit October 2021

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Change in coreboot[master]: sc7280: Enable UART driver
by Shelley Chen (Code Review) 06 Oct '21

06 Oct '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55963 ) Change subject: sc7280: Enable UART driver ...................................................................... sc7280: Enable UART driver Enable common Uart driver on sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org> Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index a65a3ee..24d5c20 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -14,6 +14,7 @@ select CACHE_MRC_SETTINGS select HAS_RECOVERY_MRC_CACHE select COMPRESS_BOOTBLOCK + select HAVE_UART_SPECIAL if SOC_QUALCOMM_SC7280 @@ -36,4 +37,10 @@ int default 16 +config UART_FOR_CONSOLE + int + default 5 + help + Select the QUP instance to be used for UART console output. + endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 420e0ca..9214152 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -20,15 +20,21 @@ bootblock-y += bootblock.c bootblock-y += mmu.c bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c + +################################################################################ +verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + ################################################################################ romstage-y += cbmem.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c +romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += cbmem.c +ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ -- To view, visit https://review.coreboot.org/c/coreboot/+/55963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Gerrit-Change-Number: 55963 Gerrit-PatchSet: 30 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Enable UART driver
by Julius Werner (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Rajesh Patil. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55963 ) Change subject: sc7280: Enable UART driver ...................................................................... Patch Set 29: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Gerrit-Change-Number: 55963 Gerrit-PatchSet: 29 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 23:58:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Enable UART driver for sc7280
by Ravi kumar (Code Review) 06 Oct '21

06 Oct '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47527 ) Change subject: libpayload: Enable UART driver for sc7280 ...................................................................... libpayload: Enable UART driver for sc7280 Add Qualcomm's QUPV3 serial driver for herobrine board Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc D payloads/libpayload/drivers/serial/sc7280.c 4 files changed, 1 insertion(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47527/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 52be71d..f5b81a9 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -264,11 +264,6 @@ depends on SERIAL_CONSOLE default n -config SC7280_SERIAL_CONSOLE - bool "SC7280 SOC compatible serial port driver" - depends on SERIAL_CONSOLE - default n - config QUALCOMM_QUPV3_SERIAL_CONSOLE bool "Qualcomm QUPV3 serial port driver" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine index a9d576a..18ca19d 100644 --- a/payloads/libpayload/configs/config.herobrine +++ b/payloads/libpayload/configs/config.herobrine @@ -2,4 +2,4 @@ CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_SC7280_SERIAL_CONSOLE=y +CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 6c54c49..c4f7bf6 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -42,8 +42,6 @@ libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c -libc-$(CONFIG_LP_SC7280_SERIAL_CONSOLE) += serial/sc7280.c serial/serial.c - libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c libc-$(CONFIG_LP_MOUSE_CURSOR) += mouse_cursor.c diff --git a/payloads/libpayload/drivers/serial/sc7280.c b/payloads/libpayload/drivers/serial/sc7280.c deleted file mode 100644 index 0d7f5cf..0000000 --- a/payloads/libpayload/drivers/serial/sc7280.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <libpayload.h> - -/* For simplicity sake let's rely on coreboot initalizing the UART. */ -void serial_console_init(void) -{ - -} -- To view, visit https://review.coreboot.org/c/coreboot/+/47527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335 Gerrit-Change-Number: 47527 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Enable bootblock compression
by Shelley Chen (Code Review) 06 Oct '21

06 Oct '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52131 ) Change subject: sc7280: Enable bootblock compression ...................................................................... sc7280: Enable bootblock compression This patch enables bootblock compression on SC7280. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Ref link: https://review.coreboot.org/c/coreboot/+/45855 BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/decompressor.c 3 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index fad3040..a65a3ee 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -13,6 +13,7 @@ select SOC_QUALCOMM_COMMON select CACHE_MRC_SETTINGS select HAS_RECOVERY_MRC_CACHE + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7280 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index c4e3f3e..420e0ca 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -1,5 +1,8 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += ../common/timer.c all-y += ../common/timer.c all-y += ../common/gpio.c all-y += ../common/clock.c diff --git a/src/soc/qualcomm/sc7280/decompressor.c b/src/soc/qualcomm/sc7280/decompressor.c new file mode 100644 index 0000000..3108b04 --- /dev/null +++ b/src/soc/qualcomm/sc7280/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void decompressor_soc_init(void) +{ + sc7280_mmu_init(); +} 51 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/52131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Gerrit-Change-Number: 52131 Gerrit-PatchSet: 53 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Test: adlrvp: hard code sku id to 2147483647
by Anil Kumar K (Code Review) 06 Oct '21

06 Oct '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58153 ) Change subject: Test: adlrvp: hard code sku id to 2147483647 ...................................................................... Test: adlrvp: hard code sku id to 2147483647 Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6 --- M src/mainboard/intel/adlrvp/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58153/1 diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index a113683..b23ad77 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -16,9 +16,9 @@ const char *smbios_system_sku(void) { static char sku_str[7] = ""; - uint8_t sku_id = get_board_id(); + int sku_id = 2147483647; - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + snprintf(sku_str, sizeof(sku_str), "sku%d", sku_id); return sku_str; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id168133406e8033995d80b13cca21b79d5aa21d6 Gerrit-Change-Number: 58153 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Curtis Chen, Brandon Breitenstein. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... Patch Set 24: -Code-Review (1 comment) Patchset: PS24: This one does conflict though -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 24 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Register USB-C mux operations
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58061 ) Change subject: ec/google/chromeec: Register USB-C mux operations ...................................................................... ec/google/chromeec: Register USB-C mux operations Register USB-C mux operations to the generic interface. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/usbc_mux.c 2 files changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index cb3b97e..23e7b3d 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -20,7 +20,7 @@ bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -ramstage-y += ec.c crosec_proto.c vstore.c +ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c diff --git a/src/ec/google/chromeec/usbc_mux.c b/src/ec/google/chromeec/usbc_mux.c new file mode 100644 index 0000000..6419542 --- /dev/null +++ b/src/ec/google/chromeec/usbc_mux.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> + +static const struct usbc_ops google_chromeec_usbc_ops = { + .mux_ops = { + .get_mux_info = google_chromeec_get_usbc_mux_info, + }, + .dp_ops = { + .wait_for_connection = google_chromeec_wait_for_displayport, + .enter_dp_mode = google_chromeec_typec_control_enter_dp_mode, + .wait_for_hpd = google_chromeec_wait_for_dp_hpd, + }, +}; + +const struct usbc_ops *usbc_get_ops(void) +{ + return &google_chromeec_usbc_ops; +} 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220 Gerrit-Change-Number: 58061 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... ec/google/chromeec: Update google_chromeec_usb_pd_get_info() google_chromeec_usb_pd_get_info() is used in ec.c only. Make it static and drop from ec.h. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e27ad9e..642c313 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1477,7 +1477,8 @@ return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, +/* Returns data role and type of device connected */ +static int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, bool *active_cable, uint8_t *dp_mode) { struct ec_params_usb_pd_control pd_control = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f4090fe..131a460 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,9 +33,6 @@ * usb capability, dp capability, cable type, etc */ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); -/* Returns data role and type of device connected */ -int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, - bool *active_cable, uint8_t *dp_mode); /* Poll (up to `timeout_ms` ms) for DisplayPort to be ready * Return: -1: Error. 0: Timeout. * >=1: Bitmask of the ports that DP device is connected -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 22:20:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add new API for USB-C mux handling
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58059 ) Change subject: ec/google/chromeec: Add new API for USB-C mux handling ...................................................................... ec/google/chromeec: Add new API for USB-C mux handling Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux related information. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a8e4f6..e27ad9e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1565,6 +1565,42 @@ return 0; } +/* + * Obtain any USB-C mux data needed for the specified port + * in: physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error +*/ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info) +{ + uint8_t mux_flags; + uint8_t dp_pin_mode; + bool ufp, dbg_acc, active_cable; + + if (google_chromeec_usb_get_pd_mux_info(port, &mux_flags) < 0) { + printk(BIOS_ERR, "Port C%d: get_pd_mux_info failed\n", port); + return -1; + } + + if (google_chromeec_usb_pd_get_info(port, &ufp, &dbg_acc, + &active_cable, &dp_pin_mode) < 0) { + printk(BIOS_ERR, "Port C%d: pd_control failed\n", port); + return -1; + } + + mux_info->usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_info->dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_info->polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_info->hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_info->hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_info->ufp = !!ufp; + mux_info->dbg_acc = !!dbg_acc; + mux_info->cable = !!active_cable; + mux_info->dp_pin_mode = dp_pin_mode; + + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index a06dfa1..f4090fe 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -9,6 +9,7 @@ #include <types.h> #include <device/device.h> #include "ec_commands.h" +#include <device/usbc_mux.h> /* Fill in base and size of the IO port resources used. */ void google_chromeec_ioport_range(uint16_t *base, size_t *size); @@ -48,6 +49,13 @@ * specified port. * Return: 0 on success, -1 on error */ int google_chromeec_typec_control_enter_dp_mode(int port); +/* + * Obtain any USB-C mux data needed for the specified port + * in: int port physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error + */ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Gerrit-Change-Number: 58059 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2021