coreboot-gerrit October 2021

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Change in coreboot[master]: util/cse_serger: Add a new tool for stitching CSE components
by build bot (Jenkins) (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Cliff Huang, Martin Roth, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego, Andrew McRae. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55503 ) Change subject: util/cse_serger: Add a new tool for stitching CSE components ...................................................................... Patch Set 17: (3 comments) File util/cbfstool/bpdt_formats/subpart_entry_1.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129933): https://review.coreboot.org/c/coreboot/+/55503/comment/0ab8ca5a_36067693 PS17, Line 49: printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", "Huffman Compressed?", line over 96 characters File util/cbfstool/cse_serger.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129933): https://review.coreboot.org/c/coreboot/+/55503/comment/17b8193e_73ccb67b PS17, Line 272: ERROR("Part(%d) exceeds file size. Part offset=0x%x, Part size = 0x%x, File size = 0x%zx\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129933): https://review.coreboot.org/c/coreboot/+/55503/comment/6aca2da2_9a940927 PS17, Line 923: if (c < LONGOPT_START) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/55503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Gerrit-Change-Number: 55503 Gerrit-PatchSet: 17 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Attention: Andrew McRae <amcrae(a)google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 20:40:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cse_serger: Add a new tool for stitching CSE components
by Furquan Shaikh (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Cliff Huang, Martin Roth, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego, Andrew McRae. Hello build bot (Jenkins), Cliff Huang, Martin Roth, Patrick Georgi, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Bernardo Perez Priego, Andrew McRae, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55503 to look at the new patch set (#17). Change subject: util/cse_serger: Add a new tool for stitching CSE components ...................................................................... util/cse_serger: Add a new tool for stitching CSE components This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M Makefile.inc M util/cbfstool/Makefile M util/cbfstool/Makefile.inc A util/cbfstool/bpdt_formats/Makefile.inc A util/cbfstool/bpdt_formats/bpdt_1_6.c A util/cbfstool/bpdt_formats/bpdt_1_7.c A util/cbfstool/bpdt_formats/subpart_entry_1.c A util/cbfstool/bpdt_formats/subpart_hdr_1.c A util/cbfstool/bpdt_formats/subpart_hdr_2.c A util/cbfstool/cse_serger.c A util/cbfstool/cse_serger.h 11 files changed, 1,960 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55503/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/55503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Gerrit-Change-Number: 55503 Gerrit-PatchSet: 17 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Attention: Andrew McRae <amcrae(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add enable PCH FIVR entry
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

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Change in coreboot[master]: drivers/intel/dptf: Add PCH FIVR enable support under TPCH device
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58141 ) Change subject: drivers/intel/dptf: Add PCH FIVR enable support under TPCH device ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/58141/comment/9482bd23_c04f5696 PS1, Line 308: acpigen_write_method("_STA", 0); : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_namestring("\\PCHE"); : acpigen_emit_byte(ONE_OP); : acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); : acpigen_write_else(); : acpigen_emit_byte(RETURN_OP); : acpigen_emit_byte(ZERO_OP); : acpigen_pop_len(); : acpigen_write_method_end(); I do not see why it is necessary to consult NVS to determine if the mainboard is choosing to enable the TPCH. This is decided at build-time via selecting `DRIVERS_INTEL_DPTF_SUPPORTS_TPCH`. If `DRIVERS_INTEL_DPTF_SUPPORTS_TPCH` is not selected, this code will never be called and there will not be a TPCH device in the ACPI, hence there will never be a need to return 0 from _STA, and this can be replaced with: `acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON)` -- To view, visit https://review.coreboot.org/c/coreboot/+/58141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5eb37d5fd0eb1a4490e810ea802cbecc04ac386 Gerrit-Change-Number: 58141 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 20:02:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Explain how to join Slack
by Angel Pons (Code Review) 06 Oct '21

06 Oct '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58150 ) Change subject: Documentation: Explain how to join Slack ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2 Gerrit-Change-Number: 58150 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Oct 2021 20:01:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add enable PCH FIVR entry under GNVS
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Update GPP_D5 configuration
by Karthik Ramasubramanian (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: shkim, Henry Sun, SH Kim. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58073 ) Change subject: mb/google/dedede/var/bugzzy: Update GPP_D5 configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Gerrit-Change-Number: 58073 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 19:54:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 06 Oct '21

06 Oct '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57815 ) Change subject: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices ...................................................................... soc/intel/alderlake: Skip setting D0I3 bit for HECI devices This patch skips setting D0I3 bit for all HECI devices by FSP. BUG=b:200644229 TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ae2537..333957f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -599,6 +599,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + /* Skip setting D0I3 bit for all HECI devices */ + s_cfg->DisableD0I3SettingForHeci = 1; /* * Power Optimizer for DMI * DmiPwrOptimizeDisable is default to 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/57815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Gerrit-Change-Number: 57815 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Explain how to join Slack
by Patrick Georgi (Code Review) 06 Oct '21

06 Oct '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58150 ) Change subject: Documentation: Explain how to join Slack ...................................................................... Documentation: Explain how to join Slack Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/community/forums.md 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/58150/1 diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md index 2ad69e1..91cadca 100644 --- a/Documentation/community/forums.md +++ b/Documentation/community/forums.md @@ -17,7 +17,9 @@ also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on [OSF Slack](https://osfw.slack.com/), which has channels on many open source -firmware related topics. +firmware related topics. Slack requires that people come from specific domains +or are explicitly invited. To work around that, there's an +[invite bot](https://slack.osfw.dev/) to let people in. ## Fortnightly coreboot leadership meeting -- To view, visit https://review.coreboot.org/c/coreboot/+/58150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2 Gerrit-Change-Number: 58150 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*/me.c: Check more than PCI interface for printing ME info
by Sean Rhodes (Code Review) 06 Oct '21

06 Oct '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58149 ) Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info ...................................................................... soc/intel/*/me.c: Check more than PCI interface for printing ME info Dump the (CS)ME status if it's in a valid state or the PCI device is enabled. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I6ad1215cceb75651b7890f3bab5df39b1b72ecf6 --- M src/soc/intel/alderlake/me.c M src/soc/intel/cannonlake/me.c M src/soc/intel/elkhartlake/me.c M src/soc/intel/icelake/me.c M src/soc/intel/jasperlake/me.c M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/me.c 7 files changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/58149/1 diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index da1a299..c9de5fe 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -99,7 +99,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 7bbe1ae..04a4b2c 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -103,7 +103,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c index 5087781..aec1547 100644 --- a/src/soc/intel/elkhartlake/me.c +++ b/src/soc/intel/elkhartlake/me.c @@ -14,7 +14,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c index c494fa5..29f8714 100644 --- a/src/soc/intel/icelake/me.c +++ b/src/soc/intel/icelake/me.c @@ -99,7 +99,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index b40b4dc..66f4823 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -14,7 +14,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 89491f8..a4bf453 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -188,7 +188,10 @@ union me_hfsts3 hfs3; union me_hfsts6 hfs6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfs1.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a299..c9de5fe 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -99,7 +99,10 @@ union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; - if (!is_cse_enabled()) + if (!is_cse_enabled() || + !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal() || + !cse_is_hfs1_com_soft_temp_disable()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); -- To view, visit https://review.coreboot.org/c/coreboot/+/58149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ad1215cceb75651b7890f3bab5df39b1b72ecf6 Gerrit-Change-Number: 58149 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit October 2021