Change in coreboot[master]: soc/intel/alderlake: Add enable PCH FIVR entry

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58140 )

Change subject: soc/intel/alderlake: Add enable PCH FIVR entry
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Patch Set 1:

(1 comment)

Patchset:

PS1: 
The mainboard already chooses to select `DRIVERS_INTEL_DPTF_SUPPORTS_TPCH` or not, there is no need to determine if TPCH will be enabled at runtime, just buildtime