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Change subject: mb/google/brya: Add PsysPmax setting to 145W
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58104/comment/ff989346_ce3461f2
PS1, Line 13: Ensure
ensure
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 )
Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/psp/psp_efs.c:
https://review.coreboot.org/c/coreboot/+/58115/comment/c3ec45b5_0db9b3e5
PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
> Oh that's not confusing. This file is under /psp and called psp_efs. […]
Done
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Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58117
to look at the new patch set (#3).
Change subject: mb/google/guybrush: Override SPI Fast speeds
......................................................................
mb/google/guybrush: Override SPI Fast speeds
Add support to override SPI fast speeds based on board version from both
bootblock and verstage. Overrides apply for Guybrush only and SPI speed
is overridden from 66 MHz to 100 MHz starting board version 4. This will
help to improve the boot time on board version by ~60 ms and still allow
the old boards to boot with 66 MHz.
BUG=b:199779306
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/bootblock.c
M src/mainboard/google/guybrush/verstage.c
3 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58117/3
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58115
to look at the new patch set (#3).
Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
......................................................................
soc/amd/common: Add support to read and set SPI speeds from verstage
Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.
BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
---
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/psp/Makefile.inc
M src/soc/amd/common/block/psp/psp_efs.c
M src/soc/amd/common/block/spi/fch_spi.c
M src/soc/amd/common/psp_verstage/fch.c
6 files changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58115/3
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