coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
by Subrata Banik (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58040 to look at the new patch set (#10). Change subject: soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS ...................................................................... soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS `heci_finalize` ensures to put all heci devices to D3 by setting the D0i3 bit prior to booting to the OS. BUG=b:200644229 TEST=Verified D0i3 bit is set for all HECI devices prior to booting to OS. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 --- M src/soc/intel/alderlake/finalize.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58040/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/58040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 Gerrit-Change-Number: 58040 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Helper function to check CSE device `devfn` status
by Subrata Banik (Code Review) 06 Oct '21

06 Oct '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58064 ) Change subject: soc/intel/common: Helper function to check CSE device `devfn` status ...................................................................... soc/intel/common: Helper function to check CSE device `devfn` status This patch creates a helper function in cse common code block to check the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and CSE_4. Currently cse common code is only able to read the device state of `PCH_DEVFN_CSE` CSE device alone. Additionally, print `slot` and 'func' number of CSE devices in case the device is either disable or hidden. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P with this patch where the serial message listed the CSE devices that are disabled in the device tree as below: HECI: CSE device 16.01 is disabled HECI: CSE device 16.04 is disabled HECI: CSE device 16.05 is disabled Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 18 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 471bc1b..e41e337 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -581,23 +581,29 @@ return 0; } -bool is_cse_enabled(void) +bool is_cse_devfn_visible(unsigned int devfn) { - const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); + int slot = PCI_SLOT(devfn); + int func = PCI_FUNC(devfn); - if (!cse_dev || !cse_dev->enabled) { - printk(BIOS_WARNING, "HECI: No CSE device\n"); + if (!is_devfn_enabled(devfn)) { + printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); return false; } - if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { - printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); + if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); return false; } return true; } +bool is_cse_enabled(void) +{ + return is_cse_devfn_visible(PCH_DEVFN_CSE); +} + uint32_t me_read_config32(int offset) { return pci_read_config32(PCH_DEV_CSE, offset); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 076f294..f162d48 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -153,6 +153,12 @@ uint32_t me_read_config32(int offset); /* + * Check if the CSE device as per function argument `devfn` is enabled in device tree + * and also visible on the PCI bus. + */ +bool is_cse_devfn_visible(unsigned int devfn); + +/* * Check if the CSE device is enabled in device tree. Also check if the device * is visible on the PCI bus by reading config space. * Return true if device present and config space enabled, else return false. 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Gerrit-Change-Number: 58064 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Curtis Chen, Brandon Breitenstein. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... Patch Set 24: (1 comment) Patchset: PS24: Nice work Derek, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 24 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 19:03:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices
by Subrata Banik (Code Review) 06 Oct '21

06 Oct '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58039 ) Change subject: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices ...................................................................... soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. BUG=b:200644229 TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is able to put the CSE device toidle state or active state based on `devfn` as argument. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 41 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d3b7d9b..471bc1b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -65,11 +67,11 @@ #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) /* Get HECI BAR 0 from PCI configuration space */ -static uintptr_t get_cse_bar(void) +static uintptr_t get_cse_bar(pci_devfn_t dev) { uintptr_t bar; - bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); assert(bar != 0); /* * Bits 31-12 are the base address as per EDS for SPI, @@ -85,15 +87,12 @@ */ void heci_init(uintptr_t tempbar) { -#if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; -#else - struct device *dev = PCH_DEV_CSE; -#endif + u16 pcireg; /* Assume it is already initialized, nothing else to do */ - if (get_cse_bar()) + if (get_cse_bar(dev)) return; /* Use default pre-ram bar */ @@ -114,29 +113,29 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -static uint32_t read_bar(uint32_t offset) +static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) { - return read32p(get_cse_bar() + offset); + return read32p(get_cse_bar(dev) + offset); } -static void write_bar(uint32_t offset, uint32_t val) +static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) { - return write32p(get_cse_bar() + offset, val); + return write32p(get_cse_bar(dev) + offset, val); } static uint32_t read_cse_csr(void) { - return read_bar(MMIO_CSE_CSR); + return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); } static uint32_t read_host_csr(void) { - return read_bar(MMIO_HOST_CSR); + return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); } static void write_host_csr(uint32_t data) { - write_bar(MMIO_HOST_CSR, data); + write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); } static size_t filled_slots(uint32_t data) @@ -170,12 +169,12 @@ static uint32_t read_slot(void) { - return read_bar(MMIO_CSE_CB_RW); + return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); } static void write_slot(uint32_t val) { - write_bar(MMIO_CSE_CB_WW, val); + write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); } static int wait_write_slots(size_t cnt) @@ -887,16 +886,16 @@ die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); } -static bool disable_cse_idle(void) +static bool disable_cse_idle(pci_devfn_t dev) { struct stopwatch sw; - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); dev_idle_ctrl &= ~CSE_DEV_IDLE; - write_bar(MMIO_CSE_DEVIDLE, dev_idle_ctrl); + write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); do { - dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) return true; udelay(HECI_DELAY_US); @@ -905,51 +904,51 @@ return false; } -static void enable_cse_idle(void) +static void enable_cse_idle(pci_devfn_t dev) { - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); dev_idle_ctrl |= CSE_DEV_IDLE; - write_bar(MMIO_CSE_DEVIDLE, dev_idle_ctrl); + write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); } -enum cse_device_state get_cse_device_state(void) +enum cse_device_state get_cse_device_state(unsigned int devfn) { - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) return DEV_IDLE; return DEV_ACTIVE; } -static enum cse_device_state ensure_cse_active(void) +static enum cse_device_state ensure_cse_active(pci_devfn_t dev) { - if (!disable_cse_idle()) + if (!disable_cse_idle(dev)) return DEV_IDLE; - pci_or_config32(PCH_DEV_CSE, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); return DEV_ACTIVE; } -static void ensure_cse_idle(void) +static void ensure_cse_idle(pci_devfn_t dev) { - enable_cse_idle(); + enable_cse_idle(dev); - pci_and_config32(PCH_DEV_CSE, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER)); + pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); } -bool set_cse_device_state(enum cse_device_state requested_state) +bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) { - enum cse_device_state current_state = get_cse_device_state(); + enum cse_device_state current_state = get_cse_device_state(devfn); + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (current_state == requested_state) return true; if (requested_state == DEV_ACTIVE) - return ensure_cse_active() == requested_state; + return ensure_cse_active(dev) == requested_state; else - ensure_cse_idle(); + ensure_cse_idle(dev); return true; } diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index c9bbfff..1f54469 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -6,6 +6,7 @@ #include <intelblocks/pmc_ipc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> +#include <soc/pci_devs.h> #include <timestamp.h> #include <types.h> @@ -174,13 +175,13 @@ static void set_cse_end_of_post(void *unused) { - set_cse_device_state(DEV_ACTIVE); + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_BEFORE_END_OF_POST); handle_cse_eop_result(cse_send_eop()); timestamp_add_now(TS_ME_AFTER_END_OF_POST); - set_cse_device_state(DEV_IDLE); + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); } /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c00e227..076f294 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -287,9 +287,9 @@ }; /* Function to get the current CSE device state as per `cse_device_state` */ -enum cse_device_state get_cse_device_state(void); +enum cse_device_state get_cse_device_state(unsigned int devfn); /* Function that put the CSE into desired state based on `requested_state` */ -bool set_cse_device_state(enum cse_device_state requested_state); +bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state); #endif // SOC_INTEL_COMMON_CSE_H 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Gerrit-Change-Number: 58039 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Curtis Chen, Brandon Breitenstein. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... Patch Set 24: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 24 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 19:03:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Helper function to check CSE device `devfn` status
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58064 ) Change subject: soc/intel/common: Helper function to check CSE device `devfn` status ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Gerrit-Change-Number: 58064 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Oct 2021 19:02:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add PsysPmax setting to 145W
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Hou-hsun Lee, Ryan Lin, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58104 ) Change subject: mb/google/brya: Add PsysPmax setting to 145W ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58104/comment/ff989346_ce3461f2 PS1, Line 13: Ensure ensure -- To view, visit https://review.coreboot.org/c/coreboot/+/58104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Gerrit-Change-Number: 58104 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 19:01:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Tim Wawrzynczak (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Angel Pons, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Evgeny Zinoviev, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 77: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 77 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Oct 2021 18:52:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Override SPI Fast speeds
by Karthik Ramasubramanian (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58117 ) Change subject: mb/google/guybrush: Override SPI Fast speeds ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/bootblock.c: https://review.coreboot.org/c/coreboot/+/58117/comment/0c81c82f_bc61a774 PS1, Line 97: > nit: extra line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Gerrit-Change-Number: 58117 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Oct 2021 18:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage
by Karthik Ramasubramanian (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 ) Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/psp/psp_efs.c: https://review.coreboot.org/c/coreboot/+/58115/comment/c3ec45b5_0db9b3e5 PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs)); > Oh that's not confusing. This file is under /psp and called psp_efs. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I281531e506b56173471b918c746f58d1ad97162c Gerrit-Change-Number: 58115 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Oct 2021 18:40:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2021