coreboot-gerrit October 2021

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Change in coreboot[master]: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table
by Hsuan-ting Chen (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58156 to review the following change. Change subject: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table ...................................................................... [WIP] mainboard/google: Add EC_IN_RW to the early gpio table vboot_reference is introducing a new field (ctx) to store the current boot mode. This boot mode needs to be decided at verstage in coreboot. We need the pin EC_IN_RW in deciding the bootmode, so we moved this pin to early gpios, which will be configured at bootblock. This change applies on the following platforms: - brya - [TBA] This CL will be squashed into the main boot mode change after finishing. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: Ib1bd26b0ed7c0ff23b5fbfa1b641c092c25f921c --- M 3rdparty/chromeec M 3rdparty/vboot M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 4 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58156/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 4c21b57..f48b299 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 4c21b57eb9619cc3dc86d11226917d25f62f1bc8 +Subproject commit f48b29920036c69793eb1fdca0af7f8d945a20ab diff --git a/3rdparty/vboot b/3rdparty/vboot index 13f601f..2cf7657 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 13f601fbd4c1b128f333391e4552082594f0ff25 +Subproject commit 2cf76574dbf57c70da3a835f2a45d5619dc058f5 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 777b816..8e51126 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -390,6 +390,8 @@ PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 73fad72..7eff064 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -414,6 +414,8 @@ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bd26b0ed7c0ff23b5fbfa1b641c092c25f921c Gerrit-Change-Number: 58156 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/lzma-test test case
by Jakub Czapiga (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Hello build bot (Jenkins), Paul Fagerburg, Julius Werner, Jan Dabros, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57555 to look at the new patch set (#7). Change subject: tests: Add lib/lzma-test test case ...................................................................... tests: Add lib/lzma-test test case Files used by this test are in: tests/data/lib/lzma-test/ file.bin - files with uncompressed data file.lzma.bin - files with LZMA-compressed data from file.bin How to prepare compressed file: util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 --- A tests/data/lib/lzma-test/data.1.bin A tests/data/lib/lzma-test/data.1.lzma.bin A tests/data/lib/lzma-test/data.2.bin A tests/data/lib/lzma-test/data.2.lzma.bin A tests/data/lib/lzma-test/data.3.bin A tests/data/lib/lzma-test/data.3.lzma.bin A tests/data/lib/lzma-test/data.4.bin A tests/data/lib/lzma-test/data.4.lzma.bin M tests/lib/Makefile.inc A tests/lib/lzma-test.c 10 files changed, 1,048 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/57555/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Gerrit-Change-Number: 57555 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Hsuan-ting Chen (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Hsuan-ting Chen, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Andrey Petrov, Patrick Rudolph, Yu-Ping Wu. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57951 to look at the new patch set (#2). Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using intel SoC Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 --- M src/include/bootmode.h M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/chromeos.c M src/security/vboot/bootmode.c M src/security/vboot/vboot_logic.c M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/skylake/Makefile.inc 51 files changed, 0 insertions(+), 323 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57951/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Gerrit-Change-Number: 57951 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main
by Hsuan-ting Chen (Code Review) 07 Oct '21

07 Oct '21

Hsuan-ting Chen has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/57048 ) Change subject: vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/57048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Gerrit-Change-Number: 57048 Gerrit-PatchSet: 10 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Hsuan-ting Chen (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Tim Wawrzynczak, Julius Werner, Andrey Petrov, Patrick Rudolph, Yu-Ping Wu. Hello build bot (Jenkins), Tim Wawrzynczak, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57951 to review the following change. Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using intel SoC Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 --- M src/include/bootmode.h M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/chromeos.c M src/security/vboot/bootmode.c M src/security/vboot/vboot_logic.c M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/skylake/Makefile.inc 51 files changed, 0 insertions(+), 323 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57951/1 diff --git a/src/include/bootmode.h b/src/include/bootmode.h index da2dbf6..aadecba 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -11,7 +11,6 @@ int clear_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); -int get_ec_is_trusted(void); /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 1aa8876..6f8f242 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -40,9 +40,3 @@ { return gpio_eint_poll(GPIO_H1_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index f449c9c..50eeddc 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -8,13 +8,6 @@ /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 -/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */ -#if CONFIG(BOARD_GOOGLE_SAMUS) -#define EC_IN_RW_GPIO 25 -#else -#define EC_IN_RW_GPIO 14 -#endif - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,9 +32,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(EC_IN_RW_GPIO); -} diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 5c49649..a33caca 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -65,10 +65,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index 184cd52..add7346 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -29,9 +29,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 960dd87..356e97b 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -77,10 +77,3 @@ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 13b673c..748e06e 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -59,9 +59,3 @@ { return gpio_eint_poll(GPIO_GSC_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 4a48aeb..b88862c 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -12,8 +12,6 @@ #define WP_GPIO GP_E_22 -#define EC_IN_RW_GPIO GP_SW_77 - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -64,9 +62,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW_GPIO); -} diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 9cb57f8..7599295 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -37,9 +37,3 @@ { return !gpio_get_value(GPIO_D16); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get_value(GPIO_D17); -} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 6be7652..fb904cc 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -30,9 +30,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index b2c34a2..9d3929e 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -111,10 +111,3 @@ if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 607f7c3..d92ebb1 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -110,10 +110,3 @@ pmc_soc_set_afterg3_en(true); #endif } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 10a837d..11931c6 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -34,9 +34,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 593982b..a74c2f7 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -34,9 +34,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 8ed41cd..38d12cb 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -26,10 +26,3 @@ { return 0; } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index ac464b4..4674581 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -157,10 +157,3 @@ { return !read_gpio(get_wp_status_gpio_pin()); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 70b4f64..6a1f0b4 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -33,9 +33,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 479ca3d..688c0dd 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -49,9 +49,3 @@ return gpio_irq_status(GPIO_TPM_IRQ); } #endif - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index c1621d9..f129957 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> -#include <boardid.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -25,14 +24,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Board versions 1 & 2 support H1 DB, but the EC_IN_RW signal is not - routed. So emulate EC is trusted. */ - if (CONFIG(BOARD_GOOGLE_GUYBRUSH) && - (board_id() == UNDEFINED_STRAPPING_ID || board_id() < 3)) - return 1; - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 400a3fa..ee54ade 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -34,9 +34,3 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index 319f929..643dcc2 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -18,9 +18,3 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Stub GPIO. */ - return 0; -} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index bc00994..cf59636 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -67,10 +67,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 1f81f22..b85f976 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -32,9 +32,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 4c4a8be..3f15a3f 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -37,9 +37,3 @@ { return gpio_eint_poll(CR50_IRQ); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index ce9a33d..540803c 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -6,8 +6,6 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#define GPIO_EC_IN_RW 21 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,9 +37,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 171a8ee..c827c7d 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,16 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 9aaad2f..7fe877b 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -19,9 +19,3 @@ { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 9aaad2f..7fe877b 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -19,9 +19,3 @@ { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 9aaad2f..7fe877b 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -19,9 +19,3 @@ { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 739df2e..9e7af27 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -34,9 +34,3 @@ { return !gpio_get(WRITE_PROTECT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 4a7f040..03d3b4f 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -33,9 +33,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 346fe76..03b0d47 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -68,10 +68,3 @@ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 3d4f51c..ebbfdd3 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -37,9 +37,3 @@ { return !gpio_get_value(GPIO_X30); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get_value(GPIO_X23); -} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 35a9323..5dd1e98 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -38,9 +38,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index edc714e..f9a1718 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -8,9 +8,6 @@ /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 -/* The EC_IN_RW lives on SCGPIO59 */ -#define EC_IN_RW_PAD 59 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -46,9 +43,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !score_get_gpio(EC_IN_RW_PAD); -} diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index f87d935..94d76b9 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -33,9 +33,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 36825b5..f49b639 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -107,10 +107,3 @@ if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 11d41cd..4fffd45 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -30,9 +30,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(14); -} diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index d74df82..13a69bc 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -19,9 +19,3 @@ { return !gpio_get(WRITE_PROTECT_L); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 51a0c5c..21cf94f 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -128,10 +128,3 @@ { return !read_gpio(WP_SW); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 718df33..9006000 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -55,9 +55,3 @@ { return gpio_irq_status(GPIO_H1_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 411b14e..b99df04 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -56,9 +56,3 @@ { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_ECINRW); -} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index f3587a3..a3ba752 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -34,10 +34,3 @@ { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 33f0ee4..95158bf 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -43,10 +43,3 @@ { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index cdf418d..abd50c5 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -32,9 +32,3 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index 3c60f98..b581b90 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -31,9 +31,3 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 3c50e4e..6c05109 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -57,16 +57,6 @@ return 0; } -int __weak get_ec_is_trusted(void) -{ - /* - * If board doesn't override this, by default we always assume EC is in - * RW and untrusted. However, newer platforms are supposed to use cr50 - * BOOT_MODE to report this and won't need to override this anymore. - */ - return 0; -} - #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ff93d0b..10993d3 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -327,9 +327,6 @@ if (CONFIG(TPM_CR50)) check_boot_mode(ctx); - if (get_ec_is_trusted()) - ctx->flags |= VB2_CONTEXT_EC_TRUSTED; - /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(ctx); diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 1c578f21..c7e0abc 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -46,8 +46,6 @@ ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c -verstage-y += gpio.c - smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b17607..49707da 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -92,13 +92,11 @@ romstage-y += gpio_glk.c smm-y += gpio_glk.c ramstage-y += gpio_glk.c -verstage-y += gpio_glk.c else bootblock-y += gpio_apl.c romstage-y += gpio_apl.c smm-y += gpio_apl.c ramstage-y += gpio_apl.c -verstage-y += gpio_apl.c endif CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 51700b3..c191aac 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += lpc.c bootblock-y += uart.c -verstage-y += gpio.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c -- To view, visit https://review.coreboot.org/c/coreboot/+/57951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Gerrit-Change-Number: 57951 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add HECI Reset flow in the CSE driver
by Ravindra (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Sridhar Siricilla, Paul Menzel, Ravindra, Patrick Rudolph. Ravindra has uploaded a new patch set (#4) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/55363 ) Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ...................................................................... soc/intel/common: Add HECI Reset flow in the CSE driver The patch adds HECI Reset flow in the CSE driver. This is required as part of the HECI Interface initialization in order to put the host and CSE into a known good state for communication. This change is required to send HECI commands before DRAM Init. TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Gerrit-Change-Number: 55363 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Set the suitable SPD data
by Mario Scheithauer (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58111 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl2: Set the suitable SPD data ...................................................................... mb/siemens/mc_ehl2: Set the suitable SPD data Since other LPDDR4X modules with memory down are used on this board, the SPD data file must be adapted. Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58111/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Gerrit-Change-Number: 58111 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/adlrvp: Add hook function to return EC in RW status
by Hsuan-ting Chen (Code Review) 07 Oct '21

07 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Bernardo Perez Priego. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/adlrvp: Add hook function to return EC in RW status ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/adlrvp/early_gpio.c: https://review.coreboot.org/c/coreboot/+/58099/comment/42e15640_0dcff4f8 PS6, Line 9: early_gpio_table We found out that we made a bug at the introducing get_ec_is_trusted() CL... (https://review.coreboot.org/c/coreboot/+/57048) And we are aiming for solutions to fix it. The get_ec_is_trusted() is called in verstage, but normally the GPIO is initialized in ramstage, which will cause errors. Can we move the GPIO_EC_IN_RW configuration in this early_gpio_table? -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Thu, 07 Oct 2021 05:31:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable x86_64 support
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58089 ) Change subject: soc/intel/cannonlake: Enable x86_64 support ...................................................................... soc/intel/cannonlake: Enable x86_64 support Select HAVE_EXP_X86_64_SUPPORT. Tested on prodrive/hermes: Boots into Linux. Change-Id: I033ccd5dc793b637a2ac4271b450335464564885 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 88c914d..227f680 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,6 +7,7 @@ select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select HAVE_EXP_X86_64_SUPPORT config SOC_INTEL_WHISKEYLAKE bool -- To view, visit https://review.coreboot.org/c/coreboot/+/58089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I033ccd5dc793b637a2ac4271b450335464564885 Gerrit-Change-Number: 58089 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/vboot: Remove vb2ex_hwcrypto stubs
by Werner Zeh (Code Review) 07 Oct '21

07 Oct '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58095 ) Change subject: security/vboot: Remove vb2ex_hwcrypto stubs ...................................................................... security/vboot: Remove vb2ex_hwcrypto stubs Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib (CL:2353775), we can remove the same stubs from coreboot. BUG=none TEST=emerge-brya coreboot TEST=emerge-cherry coreboot BRANCH=none Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 0 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ff93d0b..91d42b2 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -54,27 +54,6 @@ return VB2_SUCCESS; } -/* No-op stubs that can be overridden by SoCs with hardware crypto support. */ -__weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) -{ - return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; -} - -__weak vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, - uint32_t size) -{ - BUG(); /* Should never get called if init() returned an error. */ - return VB2_ERROR_UNKNOWN; -} - -__weak vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, - uint32_t digest_size) -{ - BUG(); /* Should never get called if init() returned an error. */ - return VB2_ERROR_UNKNOWN; -} - static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) { int is_resume; -- To view, visit https://review.coreboot.org/c/coreboot/+/58095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Gerrit-Change-Number: 58095 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2021