coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/puff: Use customized emmc dll settings for Kaisa.
by Kane Chen (Code Review) 02 Sep '20

02 Sep '20

Hello Kane Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45027 to review the following change. Change subject: mb/google/puff: Use customized emmc dll settings for Kaisa. ...................................................................... mb/google/puff: Use customized emmc dll settings for Kaisa. ODM is reporting some systems are stuck in linux kernel because of crc errors during mmc cmd6 transaction. The dll settings in this commit is one of dll settings in CML FSP. But on the certain SKU, fsp chooses the another dll settings. So this commit picks the working dll for Kaisa from fsp and overrides it in coreboot, and ODM is able to boot to OS without problem. Before we clarify final dll selection, Kaisa needs this dll settings to recover the failing boards. BUG=b:161682230 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Change-Id: I301b7a668cedf4d7d175084717e280f5e19b31c4 --- M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/variants/kaisa/overridetree.cb 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45027/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3f803c5..0a381ab1 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -35,10 +35,12 @@ bool "-> Kaisa Legacy (32MB)" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 + select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_KAISA bool "-> Kaisa" select BOARD_GOOGLE_BASEBOARD_PUFF + select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index c6aef05..0585f51 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -169,7 +169,7 @@ # Refer to EDS-Vol2-14.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0xC0B" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-14.3.9. @@ -177,7 +177,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C292929" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-14.3.10. @@ -185,7 +185,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C101616" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-14.3.12. @@ -196,7 +196,7 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x20006" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-14.3.11. -- To view, visit https://review.coreboot.org/c/coreboot/+/45027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I301b7a668cedf4d7d175084717e280f5e19b31c4 Gerrit-Change-Number: 45027 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: treewide: stop using hexdumps for spd files
by Michael Niewöhner (Code Review) 02 Sep '20

02 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44775 ) Change subject: treewide: stop using hexdumps for spd files ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/44775/14/src/lib/Makefile.inc File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/44775/14/src/lib/Makefile.inc@363 PS14, Line 363: cat $(LIB_SPD_DEPS) > $@ > Check that fails the build? Yes. And perhaps decouple the assumptions this code is making -- i.e. […] No, not "fails the build" but add an empty spd.bin, exactly as I said ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/44775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 Gerrit-Change-Number: 44775 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Sep 2020 13:37:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/volteer/variant/lindar: Update memory settings."
by Patrick Georgi (Code Review) 02 Sep '20

02 Sep '20

Hello Rasheed Hsueh, build bot (Jenkins), Martin Roth, Caveh Jalali, Nick Vaccaro, Michael Niewöhner, Zhuohao Lee, Zhuohao Lee, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44993 to review the following change. Change subject: Revert "mb/google/volteer/variant/lindar: Update memory settings." ...................................................................... Revert "mb/google/volteer/variant/lindar: Update memory settings." This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb. Reason for revert: broke the build Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 --- M src/mainboard/google/volteer/variants/lindar/Makefile.inc D src/mainboard/google/volteer/variants/lindar/memory.c D src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc D src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt D src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 5 files changed, 1 insertion(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44993/1 diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc index b0bfc56..776c4ea 100644 --- a/src/mainboard/google/volteer/variants/lindar/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c -romstage-y += memory.c +bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c deleted file mode 100644 index 11bcf4c..0000000 --- a/src/mainboard/google/volteer/variants/lindar/memory.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> - -static const struct lpddr4x_cfg lindar_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &lindar_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) -{ - return &board_memcfg; -} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc deleted file mode 100644 index 4c95819..0000000 --- a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! - -SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt deleted file mode 100644 index 9bf0bd9..0000000 --- a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt +++ /dev/null @@ -1,2 +0,0 @@ -DRAM Part Name ID to assign -K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt deleted file mode 100644 index a226d2f..0000000 --- a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt +++ /dev/null @@ -1 +0,0 @@ -K4U6E3S4AA-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/44993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 Gerrit-Change-Number: 44993 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add mainboard hook for overriding SoC config
by Jes Klinke (Code Review) 02 Sep '20

02 Sep '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44914 to review the following change. Change subject: soc/intel/tigerlake: Add mainboard hook for overriding SoC config ...................................................................... soc/intel/tigerlake: Add mainboard hook for overriding SoC config TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Signed-off-by: jbk(a)chromium.org --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44914/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2da63ed..bcc57c8 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -395,4 +395,7 @@ typedef struct soc_intel_tigerlake_config config_t; +/* Override settings per board. */ +void mainboard_config_update(config_t *config); + #endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 0a5fbe7..faaff88 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -82,6 +82,11 @@ PCH_DEVFN_UART2 }; +void __weak mainboard_config_update(struct soc_intel_tigerlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -92,6 +97,7 @@ struct device *dev; struct soc_intel_tigerlake_config *config; config = config_of_soc(); + mainboard_config_update(config); /* Parse device tree and enable/disable Serial I/O devices */ parse_devicetree(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/44914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Gerrit-Change-Number: 44914 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Add SPD mapping for Shyvana, Shyvana-M and Leona sup...
by Kane Chen (Code Review) 02 Sep '20

02 Sep '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44854 ) Change subject: mb/google/poppy: Add SPD mapping for Shyvana, Shyvana-M and Leona support ...................................................................... mb/google/poppy: Add SPD mapping for Shyvana, Shyvana-M and Leona support Add SAMSUNG SPD file, and add "samsung_dimm_K4E8E324ED-EGCG" and "samsung_dimm_K4E6E304ED-EGCG" mapping. BUG=none BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 --- A src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex M src/mainboard/google/poppy/variants/rammus/Makefile.inc 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44854/1 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex new file mode 100644 index 0000000..168f15e --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 08 00 50 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 08 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 0d835cb..2baeb52 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -4,6 +4,8 @@ SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 +SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/44854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 Gerrit-Change-Number: 44854 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Use customized emmc dll settings for Kaisa
by Kane Chen (Code Review) 02 Sep '20

02 Sep '20

Hello Kane Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44972 to review the following change. Change subject: mb/google/puff: Use customized emmc dll settings for Kaisa ...................................................................... mb/google/puff: Use customized emmc dll settings for Kaisa ODM is reporting boot issue on certain eMMC part With this eMMC dll value, ODM is able to boot to OS without problem. BUG=b:161682230 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Change-Id: Ic38d0fdd31763f998061abcb8b593cbc8823a6e0 --- M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/variants/kaisa/overridetree.cb 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44972/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3f803c5..83952ae 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -35,6 +35,7 @@ bool "-> Kaisa Legacy (32MB)" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 + select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_KAISA bool "-> Kaisa" diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index c6aef05..0585f51 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -169,7 +169,7 @@ # Refer to EDS-Vol2-14.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0xC0B" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-14.3.9. @@ -177,7 +177,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C292929" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-14.3.10. @@ -185,7 +185,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C101616" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-14.3.12. @@ -196,7 +196,7 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x20006" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-14.3.11. -- To view, visit https://review.coreboot.org/c/coreboot/+/44972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic38d0fdd31763f998061abcb8b593cbc8823a6e0 Gerrit-Change-Number: 44972 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'
by HAOUAS Elyes (Code Review) 02 Sep '20

02 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44929 ) Change subject: soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE' ...................................................................... soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE' POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44929/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 545b423..a4274df 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,7 +31,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS @@ -70,7 +69,6 @@ depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 select UDK_202005_BINDING - select POSTCAR_CONSOLE select POSTCAR_STAGE config MAX_SOCKET -- To view, visit https://review.coreboot.org/c/coreboot/+/44929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Gerrit-Change-Number: 44929 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: libpayload/xhci: Fix Slot State field width definition
by Caveh Jalali (Code Review) 02 Sep '20

02 Sep '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45023 ) Change subject: libpayload/xhci: Fix Slot State field width definition ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Gerrit-Change-Number: 45023 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 Sep 2020 08:59:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES'
by HAOUAS Elyes (Code Review) 02 Sep '20

02 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44927 ) Change subject: mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES' ...................................................................... mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES' GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44927/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..437f5c6 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -12,7 +12,6 @@ select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI - select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e23da43..a446835 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -10,7 +10,6 @@ select MAINBOARD_HAS_LPC_TPM select DRIVERS_ASPEED_AST2050 select SUPERIO_ASPEED_AST2400 - select GENERATE_SMBIOS_TABLES select IPMI_KCS select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND -- To view, visit https://review.coreboot.org/c/coreboot/+/44927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1 Gerrit-Change-Number: 44927 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: util: update .gitignore to ignore spd_tools binaries
by Rob Barnes (Code Review) 02 Sep '20

02 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44951 ) Change subject: util: update .gitignore to ignore spd_tools binaries ...................................................................... util: update .gitignore to ignore spd_tools binaries Ignore spd_tools binaries. BUG=None TEST=None Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: Ib5759157b668085866d0164301d84e3c15a9ef00 --- M .gitignore 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44951/1 diff --git a/.gitignore b/.gitignore index e353f49..190d3717 100644 --- a/.gitignore +++ b/.gitignore @@ -118,6 +118,8 @@ util/autoport/autoport util/kbc1126/kbc1126_ec_dump util/kbc1126/kbc1126_ec_insert +util/spd_tools/*/gen_spd +util/spd_tools/*/gen_part_id Documentation/*.aux Documentation/*.idx -- To view, visit https://review.coreboot.org/c/coreboot/+/44951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5759157b668085866d0164301d84e3c15a9ef00 Gerrit-Change-Number: 44951 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020