coreboot-gerrit September 2020

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Change in coreboot[master]: util: update .gitignore to ignore spd_tools binaries
by Rob Barnes (Code Review) 02 Sep '20

02 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44951 ) Change subject: util: update .gitignore to ignore spd_tools binaries ...................................................................... util: update .gitignore to ignore spd_tools binaries Ignore spd_tools binaries. BUG=None TEST=None Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: Ib5759157b668085866d0164301d84e3c15a9ef00 --- M .gitignore 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44951/1 diff --git a/.gitignore b/.gitignore index e353f49..190d3717 100644 --- a/.gitignore +++ b/.gitignore @@ -118,6 +118,8 @@ util/autoport/autoport util/kbc1126/kbc1126_ec_dump util/kbc1126/kbc1126_ec_insert +util/spd_tools/*/gen_spd +util/spd_tools/*/gen_part_id Documentation/*.aux Documentation/*.idx -- To view, visit https://review.coreboot.org/c/coreboot/+/44951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5759157b668085866d0164301d84e3c15a9ef00 Gerrit-Change-Number: 44951 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guide
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44820 ) Change subject: util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guide ...................................................................... util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guide BUG=b:153888802 TEST=Able to list correct eSPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 60MHz Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168 --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 83 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/44820/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 3d9d55b..287c8c6 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -507,6 +507,63 @@ _decode_spi_frequency(freq); } +static void _decode_espi_frequency(unsigned int freq) +{ + switch (freq) { + case ESPI_FREQUENCY_20MHZ: + printf("20MHz"); + break; + case ESPI_FREQUENCY_24MHZ: + printf("24MHz"); + break; + case ESPI_FREQUENCY_30MHZ: + printf("30MHz"); + break; + case ESPI_FREQUENCY_48MHZ: + printf("48MHz"); + break; + case ESPI_FREQUENCY_60MHZ: + printf("60MHz"); + break; + case ESPI_FREQUENCY_17MHZ: + printf("17MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void _decode_espi_frequency_500_series(unsigned int freq) +{ + switch (freq) { + case ESPI_FREQUENCY_500SERIES_20MHZ: + printf("20MHz"); + break; + case ESPI_FREQUENCY_500SERIES_24MHZ: + printf("24MHz"); + break; + case ESPI_FREQUENCY_500SERIES_25MHZ: + printf("25MHz"); + break; + case ESPI_FREQUENCY_500SERIES_48MHZ: + printf("48MHz"); + break; + case ESPI_FREQUENCY_500SERIES_60MHZ: + printf("60MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_espi_frequency(unsigned int freq) +{ + if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + _decode_espi_frequency_500_series(freq); + else + _decode_espi_frequency(freq); +} + static void decode_component_density(unsigned int density) { switch (density) { @@ -560,8 +617,10 @@ return 0; } -static void dump_fcba(const fcba_t *fcba) +static void dump_fcba(const fcba_t *fcba, const fpsba_t *fpsba) { + unsigned int freq; + printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", @@ -575,7 +634,11 @@ printf("\n Fast Read Support: %ssupported", (fcba->flcomp & (1 << 20))?"":"not "); printf("\n Read Clock Frequency: "); - decode_spi_frequency((fcba->flcomp >> 17) & 7); + if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + freq = (fpsba->pchstrp[22] & 0x38) >> 3; + else + freq = (fcba->flcomp >> 17) & 7; + decode_espi_frequency(freq); switch (ifd_version) { case IFD_VERSION_1: @@ -870,7 +933,7 @@ if (frba && fcba && fpsba && fmba && fmsba) { dump_frba(frba); - dump_fcba(fcba); + dump_fcba(fcba, fpsba); dump_fpsba(fdb, fpsba); dump_fmba(fmba); dump_fmsba(fmsba); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 0842924..b725823 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -71,6 +71,23 @@ SPI_FREQUENCY_14MHZ = 6, }; +enum espi_frequency { + ESPI_FREQUENCY_20MHZ = 0, + ESPI_FREQUENCY_24MHZ = 1, + ESPI_FREQUENCY_30MHZ = 2, + ESPI_FREQUENCY_48MHZ = 3, + ESPI_FREQUENCY_60MHZ = 4, + ESPI_FREQUENCY_17MHZ = 6, +}; + +enum espi_frequency_500_series { + ESPI_FREQUENCY_500SERIES_20MHZ = 0, + ESPI_FREQUENCY_500SERIES_24MHZ = 1, + ESPI_FREQUENCY_500SERIES_25MHZ = 2, + ESPI_FREQUENCY_500SERIES_48MHZ = 3, + ESPI_FREQUENCY_500SERIES_60MHZ = 4, +}; + enum component_density { COMPONENT_DENSITY_512KB = 0, COMPONENT_DENSITY_1MB = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/44820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168 Gerrit-Change-Number: 44820 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guide
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44819 ) Change subject: util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guide ...................................................................... util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guide BUG=b:153888802 TEST=Able to list correct SPI frequency as per TGL SPI flash guide Without this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: supported Read Clock Frequency: 20MHz With this CL : Found Component Section FLCOMP 0x093030f6 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44819/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ac86441..3d9d55b 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -446,7 +446,7 @@ printf("Wrote layout to %s\n", layout_fname); } -static void decode_spi_frequency(unsigned int freq) +static void _decode_spi_frequency(unsigned int freq) { switch (freq) { case SPI_FREQUENCY_20MHZ: @@ -476,6 +476,37 @@ } } +static void _decode_spi_frequency_500_series(unsigned int freq) +{ + switch (freq) { + case SPI_FREQUENCY_100MHZ: + printf("100MHz"); + break; + case SPI_FREQUENCY_50MHZ: + printf("50MHz"); + break; + case SPI_FREQUENCY_500SERIES_33MHZ: + printf("33MHz"); + break; + case SPI_FREQUENCY_25MHZ: + printf("25MHz"); + break; + case SPI_FREQUENCY_14MHZ: + printf("14MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_spi_frequency(unsigned int freq) +{ + if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + _decode_spi_frequency_500_series(freq); + else + _decode_spi_frequency(freq); +} + static void decode_component_density(unsigned int density) { switch (density) { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index fb3de2f..0842924 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -63,6 +63,14 @@ SPI_FREQUENCY_17MHZ = 6, }; +enum spi_frequency_500_series { + SPI_FREQUENCY_100MHZ = 0, + SPI_FREQUENCY_50MHZ = 1, + SPI_FREQUENCY_500SERIES_33MHZ = 3, + SPI_FREQUENCY_25MHZ = 4, + SPI_FREQUENCY_14MHZ = 6, +}; + enum component_density { COMPONENT_DENSITY_512KB = 0, COMPONENT_DENSITY_1MB = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/44819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e Gerrit-Change-Number: 44819 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCH
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44818 ) Change subject: util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCH ...................................................................... util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCH BUG=b:153888802 TEST=Able to dump FLMAP3 for Volteer platform with TGP > ifdtool -d coreboot.rom FLMAP3: 0x00000000 Minor Revision ID: 0x0000 Major Revision ID: 0x0000 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787 --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44818/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 4de1205..ac86441 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -813,6 +813,12 @@ printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); } + if (chipset == CHIPSET_500_SERIES_TIGER_POINT) { + printf("FLMAP3: 0x%08x\n", fdb->flmap3); + printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); + printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); + } + char *flumap = find_flumap(image, size); uint32_t flumap1 = *(uint32_t *)flumap; printf("FLUMAP1: 0x%08x\n", flumap1); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index a113d29..fb3de2f 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -81,6 +81,7 @@ uint32_t flmap0; uint32_t flmap1; uint32_t flmap2; + uint32_t flmap3; // Exist for 500 series onwards } __attribute__((packed)) fdbar_t; // regions -- To view, visit https://review.coreboot.org/c/coreboot/+/44818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787 Gerrit-Change-Number: 44818 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44817 ) Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ...................................................................... util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nouniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH BUG=b:153888802 TEST=Dump FD for Hatch platform as below > ifdtool -d coreboot.rom PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 --- M util/ifdtool/ifdtool.c 1 file changed, 37 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44817/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index b15b163..4de1205 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -518,6 +518,17 @@ return 0; } + +/* FLMAP0 register bit 24 onwards are reserved from SPT PCH */ +static int is_platform_with_100x_series_pch(void) +{ + if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && + chipset <= CHIPSET_500_SERIES_TIGER_POINT) + return 1; + + return 0; +} + static void dump_fcba(const fcba_t *fcba) { printf("\nFound Component Section\n"); @@ -560,9 +571,21 @@ (fcba->flill >> 8) & 0xff); printf(" Invalid Instruction 0: 0x%02x\n", fcba->flill & 0xff); - printf("FLPB 0x%08x\n", fcba->flpb); - printf(" Flash Partition Boundary Address: 0x%06x\n\n", - (fcba->flpb & 0xfff) << 12); + if (is_platform_with_100x_series_pch()) { + printf("FLILL1 0x%08x\n", fcba->flpb); + printf(" Invalid Instruction 7: 0x%02x\n", + (fcba->flpb >> 24) & 0xff); + printf(" Invalid Instruction 6: 0x%02x\n", + (fcba->flpb >> 16) & 0xff); + printf(" Invalid Instruction 5: 0x%02x\n", + (fcba->flpb >> 8) & 0xff); + printf(" Invalid Instruction 4: 0x%02x\n", + fcba->flpb & 0xff); + } else { + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); + } } static void dump_fpsba(const fdbar_t *fdb, const fpsba_t *fpsba) @@ -769,20 +792,26 @@ else printf("ICH Revision: %s\n", ich_chipset_names[chipset]); printf("FLMAP0: 0x%08x\n", fdb->flmap0); - printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + if (!is_platform_with_100x_series_pch()) + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4); printf("FLMAP1: 0x%08x\n", fdb->flmap1); - printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + if (is_platform_with_100x_series_pch()) + printf(" PSL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + else + printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4); - printf("FLMAP2: 0x%08x\n", fdb->flmap2); - printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); - printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + if (!is_platform_with_100x_series_pch()) { + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + } char *flumap = find_flumap(image, size); uint32_t flumap1 = *(uint32_t *)flumap; -- To view, visit https://review.coreboot.org/c/coreboot/+/44817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 Gerrit-Change-Number: 44817 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: util/ifdtool: Identify between ICH and PCH Revision
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44816 ) Change subject: util/ifdtool: Identify between ICH and PCH Revision ...................................................................... util/ifdtool: Identify between ICH and PCH Revision Consider IBEX_PEAK onwards all chipsets are belong to PCH family. BUG=b:153888802 TEST=Able to print correct PCH revision on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point With this CL : PCH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4 --- M util/ifdtool/ifdtool.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44816/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 1880900..b15b163 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -511,6 +511,13 @@ } } +static int is_platform_with_pch(void) +{ + if (chipset >= CHIPSET_5_SERIES_IBEX_PEAK) + return 1; + + return 0; +} static void dump_fcba(const fcba_t *fcba) { printf("\nFound Component Section\n"); @@ -757,7 +764,10 @@ if (!fdb) exit(EXIT_FAILURE); - printf("ICH Revision: %s\n", ich_chipset_names[chipset]); + if (is_platform_with_pch()) + printf("PCH Revision: %s\n", ich_chipset_names[chipset]); + else + printf("ICH Revision: %s\n", ich_chipset_names[chipset]); printf("FLMAP0: 0x%08x\n", fdb->flmap0); printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/44816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4 Gerrit-Change-Number: 44816 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/sarien/Kconfig: Drop redundant 'select TPM2'
by HAOUAS Elyes (Code Review) 02 Sep '20

02 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44933 ) Change subject: mb/google/sarien/Kconfig: Drop redundant 'select TPM2' ...................................................................... mb/google/sarien/Kconfig: Drop redundant 'select TPM2' TPM2 set to yes by MAINBOARD_HAS_TPM2 at security/tpm/Kconfig file. Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44933/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 53b9243..31a770a 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -23,7 +23,6 @@ select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_SARIEN select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_ARCADA - select TPM2 select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_SARIEN select USE_SAR -- To view, visit https://review.coreboot.org/c/coreboot/+/44933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d Gerrit-Change-Number: 44933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src: Drop redundant 'select BOOTBLOCK_CONSOLE'
by HAOUAS Elyes (Code Review) 02 Sep '20

02 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44928 ) Change subject: src: Drop redundant 'select BOOTBLOCK_CONSOLE' ...................................................................... src: Drop redundant 'select BOOTBLOCK_CONSOLE' BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/padmelon/Kconfig M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/google/asurada/Kconfig M src/northbridge/intel/haswell/Kconfig M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/sc7180/Kconfig 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44928/1 diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index cbbeb47..894df57 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -12,7 +12,6 @@ select GFXUMA select STONEYRIDGE_LEGACY_FREE select ONBOARD_VGA_IS_PRIMARY - select BOOTBLOCK_CONSOLE select SUPERIO_FINTEK_F81803A select SUPERIO_FINTEK_COMMON_PRE_RAM select SUPERIO_FINTEK_FAN_CONTROL diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 368f7f3..e60a4d3 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -13,7 +13,6 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARCH_TIMER select BOARD_ROMSIZE_KB_4096 - select BOOTBLOCK_CONSOLE select BOOTBLOCK_CUSTOM select BOOT_DEVICE_NOT_SPI_FLASH select CONSOLE_SERIAL diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index f5ffb3c..51e42a8 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BOOTBLOCK_CONSOLE select SOC_MEDIATEK_MT8192 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 952cc7b..84be33d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -6,7 +6,6 @@ select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 0dc96ba..bad62b2 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select ARM64_USE_ARCH_TIMER select HAVE_UART_SPECIAL diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d3dab7a..db7350f 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -12,7 +12,6 @@ select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON select HAVE_UART_SPECIAL - select BOOTBLOCK_CONSOLE if SOC_QUALCOMM_SC7180 -- To view, visit https://review.coreboot.org/c/coreboot/+/44928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Gerrit-Change-Number: 44928 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a)
by HAOUAS Elyes (Code Review) 02 Sep '20

02 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44924 ) Change subject: nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a) ...................................................................... nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a) Also order and add missing includes. Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/memmap.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44924/1 diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb..2618754 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,11 +4,12 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <commonlib/helpers.h> +#include <cbmem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <types.h> + #include "haswell.h" static uintptr_t smm_region_start(void) @@ -18,7 +19,7 @@ * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return tom & ~((1 << 20) - 1); + return ALIGN_DOWN(tom, 1 * MiB); } void *cbmem_top_chipset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I049441dd9074659effc1092dce08224974d60a2c Gerrit-Change-Number: 44924 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
by Subrata Banik (Code Review) 02 Sep '20

02 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44857 ) Change subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock ...................................................................... Patch Set 2: (10 comments) https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/Kc… File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/Kc… PS2, Line 131: 0xe00 > 0x1400 is typical Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… File src/soc/intel/alderlake/bootblock/cpu.c: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… PS2, Line 16: only booting from SPI device > "SPI flash" Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… File src/soc/intel/alderlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… PS2, Line 102: uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); > nit: const Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… PS2, Line 5: 619362 > This is the ADL-S EDS doc is same https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… PS2, Line 99: PCI_DEVICE_ID_INTEL_ADL_S_GT1 > Would any ADL-P SoC have the ADL-S GT1 IGD ? Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/bo… PS2, Line 136: aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; : txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; : vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; > suggestion: you could use !!(cpu_feature_flag & CPUID... […] Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… File src/soc/intel/alderlake/include/soc/espi.h: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… PS2, Line 5: 621483 > this is ADL-S, is there going to be a separate EDS for -P? doc is same https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… PS2, Line 12: #include <stdint.h> > not used here Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… PS2, Line 65: > What about IOM_BASE_ADDRESS ? Ack https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… File src/soc/intel/alderlake/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/44857/2/src/soc/intel/alderlake/in… PS2, Line 14: */ > SDCX controller ? actually its unused un tgl too, i will remove from tgl too -- To view, visit https://review.coreboot.org/c/coreboot/+/44857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Gerrit-Change-Number: 44857 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Sep 2020 06:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit September 2020