coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/volteer/variant/lindar: Update memory settings.
by Rasheed Hsueh (Code Review) 03 Sep '20

03 Sep '20

Rasheed Hsueh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44848 ) Change subject: mb/google/volteer/variant/lindar: Update memory settings. ...................................................................... mb/google/volteer/variant/lindar: Update memory settings. Based on the Lindar's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: rasheed.hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 --- A src/mainboard/google/volteer/variants/lindar/memory.c A src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 4 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44848/1 diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c new file mode 100644 index 0000000..ea81216 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg lindar_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &lindar_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc new file mode 100644 index 0000000..4c95819 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt new file mode 100644 index 0000000..9bf0bd9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt new file mode 100644 index 0000000..a226d2f --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/44848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 Gerrit-Change-Number: 44848 Gerrit-PatchSet: 1 Gerrit-Owner: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google/puff: Select INTEL_GMA_HAVE_VBT
by Edward O'Callaghan (Code Review) 03 Sep '20

03 Sep '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45060 ) Change subject: mb/google/puff: Select INTEL_GMA_HAVE_VBT ...................................................................... mb/google/puff: Select INTEL_GMA_HAVE_VBT NOT-FOR-MERGE, maybe we need the vbios for GOB to function correctly? Change-Id: Ied88d582a99ba871fc7dc9c8a0f4d5336c21fa9c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45060/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ee9210d..c6e29ce 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -14,6 +14,7 @@ select SOC_INTEL_CSE_LITE_SKU select DRIVERS_INTEL_DPTF select DPTF_USE_EISA_HID + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_HATCH_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/45060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied88d582a99ba871fc7dc9c8a0f4d5336c21fa9c Gerrit-Change-Number: 45060 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/picasso: Move DRAM end to after transfer buffer
by Josie Nordrum (Code Review) 03 Sep '20

03 Sep '20

Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45045 ) Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ...................................................................... soc/amd/picasso: Move DRAM end to after transfer buffer Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 --- M src/soc/amd/picasso/memlayout_x86.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45045/1 diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 7930793..65c6cab 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -78,7 +78,6 @@ _transfer_buffer = .; REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) - PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) @@ -86,6 +85,7 @@ FMAP_CACHE(., FMAP_SIZE) #if CONFIG(VBOOT) _etransfer_buffer = .; + PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/45045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Gerrit-Change-Number: 45045 Gerrit-PatchSet: 1 Gerrit-Owner: Josie Nordrum <josienordrum(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
by Subrata Banik (Code Review) 03 Sep '20

03 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44857 ) Change subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/44857/3/src/soc/intel/alderlake/bo… File src/soc/intel/alderlake/bootblock/cpu.c: https://review.coreboot.org/c/coreboot/+/44857/3/src/soc/intel/alderlake/bo… PS3, Line 16: memory > memory mapped Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/44857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Gerrit-Change-Number: 44857 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Sep 2020 03:45:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
by Subrata Banik (Code Review) 03 Sep '20

03 Sep '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44857 to look at the new patch set (#4). Change subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock ...................................................................... soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include ADL-P related DID, BDF Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 --- A src/soc/intel/alderlake/Kconfig A src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/bootblock/bootblock.c A src/soc/intel/alderlake/bootblock/cpu.c A src/soc/intel/alderlake/bootblock/pch.c A src/soc/intel/alderlake/bootblock/report_platform.c A src/soc/intel/alderlake/include/soc/bootblock.h A src/soc/intel/alderlake/include/soc/espi.h A src/soc/intel/alderlake/include/soc/iomap.h A src/soc/intel/alderlake/include/soc/p2sb.h A src/soc/intel/alderlake/include/soc/pch.h A src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcr_ids.h A src/soc/intel/alderlake/include/soc/pm.h A src/soc/intel/alderlake/include/soc/smbus.h 15 files changed, 1,136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44857/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Gerrit-Change-Number: 44857 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork: update DRAM table for berknip
by Kevin Chiu (Code Review) 03 Sep '20

03 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44862 ) Change subject: mb/google/zork: update DRAM table for berknip ...................................................................... mb/google/zork: update DRAM table for berknip Two DDR4 DRAM add ID9: CH2 DDR4 Hynix H5AN8G6NDJR-XNC 8Gb x 8 IDA: CH2 DDR4 Samsung K4AAG165WA-BCTD 16Gb x 8 BUG=b:165956925 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ia21a561e9b89feeccb6509d9280eaf52cfc2f5a3 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/spd/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44862/1 diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index f53e662..16e982f 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -18,8 +18,8 @@ APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0110 APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x2 # 0b1001 +APCB_SOURCES += samsung-K4AAG165WA-BCTD_x2 # 0b1010 APCB_SOURCES += empty # 0b1011 APCB_SOURCES += empty # 0b1100 APCB_SOURCES += empty # 0b1101 -- To view, visit https://review.coreboot.org/c/coreboot/+/44862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia21a561e9b89feeccb6509d9280eaf52cfc2f5a3 Gerrit-Change-Number: 44862 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: trogdor: Assert EN_PP3300_HUB
by Julius Werner (Code Review) 03 Sep '20

03 Sep '20

Hello Matthias Kaehlcke, Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44744 to review the following change. Change subject: trogdor: Assert EN_PP3300_HUB ...................................................................... trogdor: Assert EN_PP3300_HUB Some Trogdor variants power their USB hub from a PMIC LDO that is already enabled by QcLib, and some have a discrete LDO that is controlled by GPIO_84. For the latter, let's make sure we assert that GPIO on boot. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9d206cd7154ded3bf179e68c2b1421d0a8ee89f2 --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/44744/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index c82eaa0..4d6e352 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -12,6 +12,9 @@ static void setup_usb(void) { + /* Assert EN_PP3300_HUB for those board variants that use it. */ + gpio_output(GPIO(84), 1); + setup_usb_host0(&usb0_board_data); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d206cd7154ded3bf179e68c2b1421d0a8ee89f2 Gerrit-Change-Number: 44744 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matthias Kaehlcke <mka(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: trogdor: Shuffle RAM and SKU ID pins (again)
by Julius Werner (Code Review) 03 Sep '20

03 Sep '20

Hello Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44949 to review the following change. Change subject: trogdor: Shuffle RAM and SKU ID pins (again) ...................................................................... trogdor: Shuffle RAM and SKU ID pins (again) We're moving a lot of pins around on Trogdor again. For firmware this only affects the RAM and SKU strapping ID pins. Since there are quite a few of the old devices in circulation this time and some people seem to care about mosys RAM information working, let's actually check the board revision and support both cases this time. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If7728d8ea4b7f6e7ff6721ade90f975f6efd5ddd --- M src/mainboard/google/trogdor/boardid.c 1 file changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44949/1 diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index c1a4892..f60dddbe 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -2,6 +2,7 @@ #include <boardid.h> #include <gpio.h> +#include <types.h> uint32_t board_id(void) { @@ -15,14 +16,27 @@ return id; } +/* Whether a revision was built before or after the great pin migration of August 2020. */ +static bool use_old_pins(void) +{ + return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || + (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() < 3) || + (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); +} + uint32_t ram_code(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t old_pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t pins[] = {[2] = GPIO(5), [1] = GPIO(3), [0] = GPIO(1)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } @@ -31,10 +45,15 @@ { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t old_pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t pins[] = {[2] = GPIO(2), [1] = GPIO(90), [0] = GPIO(58)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7728d8ea4b7f6e7ff6721ade90f975f6efd5ddd Gerrit-Change-Number: 44949 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/puff/var/noibat: Update DPTF parameters for noibat
by Chen Wisley (Code Review) 03 Sep '20

03 Sep '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45020 ) Change subject: mb/google/puff/var/noibat: Update DPTF parameters for noibat ...................................................................... mb/google/puff/var/noibat: Update DPTF parameters for noibat 1. Update paramerters form thermal team. 2. Update PL2 Max/Min to 51W/15W. BUG=none TEST=build noibat and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b --- M src/mainboard/google/hatch/variants/noibat/overridetree.cb 1 file changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45020/1 diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index de49462..3b9e93c 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/cannonlake + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -197,29 +201,27 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(52, 80), + TEMP_PCT(50, 70), + TEMP_PCT(48, 60), + TEMP_PCT(46, 50), + TEMP_PCT(44, 40), + TEMP_PCT(42, 0),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, @@ -227,8 +229,8 @@ .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .min_power = 15000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" -- To view, visit https://review.coreboot.org/c/coreboot/+/45020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b Gerrit-Change-Number: 45020 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Update DPTF parameters and TCC offset for faffy
by David Wu (Code Review) 03 Sep '20

03 Sep '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45021 ) Change subject: mb/google/puff: Update DPTF parameters and TCC offset for faffy ...................................................................... mb/google/puff: Update DPTF parameters and TCC offset for faffy 1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 --- M src/mainboard/google/hatch/variants/faffy/overridetree.cb 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45021/1 diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index a5c8eff..a9e98d9 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -1,4 +1,10 @@ chip soc/intel/cannonlake + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -276,16 +282,16 @@ device pci 04.0 on chip drivers/intel/dptf ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 5000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" ## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval - # 25-51W PL2 in 1000mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 10000, .max_power = 15000, @@ -293,18 +299,12 @@ .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, + .min_power = 15000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - device generic 0 on end end end # DPTF 0x1903 -- To view, visit https://review.coreboot.org/c/coreboot/+/45021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Gerrit-Change-Number: 45021 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020