coreboot-gerrit September 2020

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Change in coreboot[master]: soc/picasso: Set max_speed_mts and configured_speed_mts
by Rob Barnes (Code Review) 04 Sep '20

04 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44984 ) Change subject: soc/picasso: Set max_speed_mts and configured_speed_mts ...................................................................... soc/picasso: Set max_speed_mts and configured_speed_mts ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 --- M src/soc/amd/picasso/dmi.c 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44984/1 diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c index 3988616..5189cd6 100644 --- a/src/soc/amd/picasso/dmi.c +++ b/src/soc/amd/picasso/dmi.c @@ -28,14 +28,12 @@ dimm->ddr_type = dmi17->MemoryType; /** - * Based on the name, ddr_frequency should hold the memory clock - * frequency in MHz. However it is interpreted as MT/s in SMBIOS - * downstream. So multiply by 2 to translate to memory speed in MT/s. - * ddr_frequency is used for setting both config speed and max - * speed. Using config speed so we don't get the false impression - * that the RAM is running faster than it actually is. + * TYPE17_DMI_INFO holds speed in MHz. + * Change to MT/s by multiplying by 2. */ - dimm->ddr_frequency = 2 * dmi17->ConfigSpeed; + dimm->configured_speed_mts = 2 * dmi17->ConfigSpeed; + + dimm->max_speed_mts = 2 * dmi17->Speed; dimm->rank_per_dimm = dmi17->Attributes; -- To view, visit https://review.coreboot.org/c/coreboot/+/44984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Gerrit-Change-Number: 44984 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Allow using the remaining Comet Lake FSPs
by 9elements QA (Code Review) 04 Sep '20

04 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44954 ) Change subject: soc/intel/cnl: Allow using the remaining Comet Lake FSPs ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17753 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17752 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/17751 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17750 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/17749 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/17756 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17755 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17754 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/44954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Gerrit-Change-Number: 44954 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 03 Sep 2020 22:21:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: enable TPM2
by Jeremy Soller (Code Review) 04 Sep '20

04 Sep '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43626 ) Change subject: mb/system76/lemp9: enable TPM2 ...................................................................... mb/system76/lemp9: enable TPM2 Tested on lemp9, TPM2 shows up in coreboot console Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I7878c8806c453369bc14d69ecd2bf2533d8821d9 --- M src/mainboard/system76/lemp9/Kconfig M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/lemp9/gpio.h 3 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43626/1 diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index c606d91..8286ba3 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -11,9 +11,8 @@ select GENERIC_SPD_BIN select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE -# Chip select 2 is not yet supported by intel fast_spi -# select MAINBOARD_HAS_SPI_TPM_CR50 -# select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA @@ -90,13 +89,4 @@ bool default n -# Chip select 2 is not yet supported by intel fast_spi -#config DRIVER_TPM_SPI_BUS -# hex -# default 0x0 -# -#config DRIVER_TPM_SPI_CHIP -# int -# default 2 - endif diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 8d77aa9..2ad0904 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -259,7 +259,11 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Interface + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index e71197c..881bd36 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -76,7 +76,7 @@ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // GSPI0 - // TODO - TPM_PIRQ# + // TPM_PIRQ# PAD_CFG_NC(GPP_A7), // LPC -- To view, visit https://review.coreboot.org/c/coreboot/+/43626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7878c8806c453369bc14d69ecd2bf2533d8821d9 Gerrit-Change-Number: 43626 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by build bot (Jenkins) (Code Review) 03 Sep '20

03 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/5/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/43494/5/src/soc/intel/common/block… PS5, Line 58: This config suppport INTEL_CAR_NEM_ENHANCED mode on 'suppport' may be misspelled - perhaps 'support'? -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Thu, 03 Sep 2020 21:46:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/acpi: Fix hang caused by IVRS
by Jason Glenesk (Code Review) 03 Sep '20

03 Sep '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45050 to review the following change. Change subject: soc/amd/picasso/acpi: Fix hang caused by IVRS ...................................................................... soc/amd/picasso/acpi: Fix hang caused by IVRS Previous commit misinterpreted spec as requiring size alignment on all IVHD device entries. The correct requirement specifies only for 4-byte entries. Additionally, the MADT was missing an entry for the second ioapic described in the IVRS. Remove 8-byte entry alignment and add second ioapic to MADT. BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. Confirm IVRS contains no alignment gaps/corruption. Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/smu.h 3 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45050/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1b9c0ca..1aacf5d 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -26,6 +26,7 @@ #include <soc/gpio.h> #include <version.h> #include "chip.h" +#include <soc/smu.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -45,14 +46,23 @@ unsigned int i; uint8_t irq; uint8_t flags; + uint32_t nb_ioapic_base; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write Kern IOAPIC, only one */ + /* Write FCH IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + /* Read base address assigned to gnb ioapic */ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, REG_NB_IOAPIC_BASE); + nb_ioapic_base = pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); + + /* Write GNB IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS + 1, nb_ioapic_base, 32); + /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index a651d6e..c76e943 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -47,8 +47,6 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); @@ -75,8 +73,6 @@ static unsigned long ivhd_describe_hpet(unsigned long current) { - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; @@ -93,8 +89,6 @@ static unsigned long ivhd_describe_f0_device(unsigned long current, uint16_t dev_id, uint8_t datasetting) { - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - current = ALIGN_UP(current, 8); ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *) current; ivhd_f0->type = IVHD_DEV_VARIABLE; @@ -154,8 +148,6 @@ ivhd_entry->dte_setting = data; *current += sizeof(ivrs_ivhd_generic_t); } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { - /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ - *current = ALIGN_UP(*current, 8); ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; ivhd_entry->type = type; diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index 128f4c4..bc9f4f3 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -12,6 +12,7 @@ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 #define REG_ADDR_MESG_ARGS_BASE 0x0b10998 +#define REG_NB_IOAPIC_BASE 0x13b102f0 /* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Gerrit-Change-Number: 45050 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: memory_info: Rename ddr_frequency to ddr_speed_mts
by Rob Barnes (Code Review) 03 Sep '20

03 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44549 ) Change subject: memory_info: Rename ddr_frequency to ddr_speed_mts ...................................................................... memory_info: Rename ddr_frequency to ddr_speed_mts This is correcting a legacy misnaming of this field. From SMBIOS 3.0 spec: Memory speed is expressed in megatransfers per second (MT/s). Previous revisions (3.0.0 and earlier) of this specification used MHz to indicate clock speed. With double data rate memory, clock speed is distinct from transfer rate, since data is transferred on both the rising and the falling edges of the clock signal. This maintains backward compatibility with observed DDR implementations prior to this revision, which already reported transfer rate instead of clock speed, e.g., DDR4-2133 (PC4-17000) memory was reported as 2133 instead of 1066. This change is symantec only, no logical change. Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/arch/x86/smbios.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/include/memory_info.h M src/mainboard/google/cyan/spd/spd.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/picasso/dmi.c M src/soc/intel/broadwell/include/soc/pei_data.h M src/soc/intel/common/smbios.c M src/soc/intel/denverton_ns/hob_mem.c 10 files changed, 24 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44549/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 6c92d03..a49e91e 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -281,8 +281,8 @@ memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; - t->clock_speed = dimm->ddr_frequency; - t->speed = dimm->ddr_frequency; + t->clock_speed = dimm->ddr_speed_mts; + t->speed = dimm->ddr_speed_mts; t->type = SMBIOS_MEMORY_DEVICE; if (dimm->dimm_size < 0x7fff) { t->size = dimm->dimm_size; diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 461fb65..1d529b1 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -536,7 +536,7 @@ dimm = &mem_info->dimm[mem_info->dimm_cnt]; if (info->size_mb) { dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = selected_freq; + dimm->ddr_speed_mts = selected_freq; dimm->dimm_size = info->size_mb; dimm->channel_num = channel; dimm->rank_per_dimm = info->ranks; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 429a9d2..41690e1 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -211,7 +211,7 @@ dimm = &mem_info->dimm[mem_info->dimm_cnt]; if (info->size_mb) { dimm->ddr_type = MEMORY_TYPE_DDR4; - dimm->ddr_frequency = selected_freq; + dimm->ddr_speed_mts = selected_freq; dimm->dimm_size = info->size_mb; dimm->channel_num = channel; dimm->rank_per_dimm = info->ranks; diff --git a/src/include/memory_info.h b/src/include/memory_info.h index f4a2009..26b42f4 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -28,7 +28,12 @@ * See the smbios.h smbios_memory_type enum. */ uint16_t ddr_type; - uint16_t ddr_frequency; + /* + * This field used to be called ddr_frequency, however it is actually + * being used used to store ddr speed in MT/s. SMBIOS version 3.0 made + * this change offical. + */ + uint16_t ddr_speed_mts; uint8_t rank_per_dimm; uint8_t channel_num; uint8_t dimm_num; diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 1c08d90..e62b0a5 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -122,10 +122,10 @@ hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); if (hob_ptr != NULL) { memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); - dimm->ddr_frequency = memory_info_hob->MemoryFrequencyInMHz; + dimm->ddr_speed_mts = memory_info_hob->MemoryFrequencyInMHz; } else { printk(BIOS_ERR, "Can't get memory info hob pointer\n"); - dimm->ddr_frequency = 0; + dimm->ddr_speed_mts = 0; } /* Parse the SPD data to determine the DIMM information */ diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 25aaea3..0daad16 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -28,11 +28,11 @@ dimm->ddr_type = dmi17->MemoryType; /* - * dimm_info uses ddr_frequency for setting both config speed and max + * dimm_info uses ddr_speed_mts for setting both config speed and max * speed. Lets use config speed so we don't get the false impression * that the RAM is running faster than it actually is. */ - dimm->ddr_frequency = dmi17->ConfigSpeed; + dimm->ddr_speed_mts = dmi17->ConfigSpeed; dimm->rank_per_dimm = dmi17->Attributes; @@ -55,7 +55,7 @@ "CBMEM_ID_MEMINFO:\n" " dimm_size: %u\n" " ddr_type: 0x%hx\n" - " ddr_frequency: %hu\n" + " ddr_speed_mts: %hu\n" " rank_per_dimm: %hhu\n" " channel_num: %hhu\n" " dimm_num: %hhu\n" @@ -67,7 +67,7 @@ " module_part_number(%zu): %s\n", dimm->dimm_size, dimm->ddr_type, - dimm->ddr_frequency, + dimm->ddr_speed_mts, dimm->rank_per_dimm, dimm->channel_num, dimm->dimm_num, diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c index d3101b7..a3b8a1a 100644 --- a/src/soc/amd/picasso/dmi.c +++ b/src/soc/amd/picasso/dmi.c @@ -28,14 +28,12 @@ dimm->ddr_type = dmi17->MemoryType; /** - * Based on the name, ddr_frequency should hold the memory clock - * frequency in Mhz. However it is interpreted as MT/s in SMBIOS - * downstream. So multiply by 2 to translate to memory speed in MT/s. - * ddr_frequency is used for setting both config speed and max + * Multiply by 2 to translate MHz to memory speed in MT/s. + * ddr_speed_mts is used for setting both config speed and max * speed. Using config speed so we don't get the false impression * that the RAM is running faster than it actually is. */ - dimm->ddr_frequency = dmi17->ConfigSpeed*2; + dimm->ddr_speed_mts = 2 * dmi17->ConfigSpeed; dimm->rank_per_dimm = dmi17->Attributes; @@ -58,7 +56,7 @@ "CBMEM_ID_MEMINFO:\n" " dimm_size: %u\n" " ddr_type: 0x%hx\n" - " ddr_frequency: %hu\n" + " ddr_speed_mts: %hu\n" " rank_per_dimm: %hhu\n" " channel_num: %hhu\n" " dimm_num: %hhu\n" @@ -70,7 +68,7 @@ " module_part_number(%zu): %s\n", dimm->dimm_size, dimm->ddr_type, - dimm->ddr_frequency, + dimm->ddr_speed_mts, dimm->rank_per_dimm, dimm->channel_num, dimm->dimm_num, diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h index 39c48d3..85b9b1d 100644 --- a/src/soc/intel/broadwell/include/soc/pei_data.h +++ b/src/soc/intel/broadwell/include/soc/pei_data.h @@ -82,7 +82,7 @@ * See the smbios.h smbios_memory_device_type enum. */ uint16_t ddr_type; - uint16_t ddr_frequency; + uint16_t ddr_speed_mts; uint8_t rank_per_dimm; uint8_t channel_num; uint8_t dimm_num; diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 5e3560c..07d2d93 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -39,7 +39,7 @@ } dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; - dimm->ddr_frequency = frequency; + dimm->ddr_speed_mts = frequency; dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index 326e716..3642b9e 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -62,7 +62,7 @@ dimm_info->SizeInMb; mem_info->dimm[index].ddr_type = memory_info_hob->MemoryType; - mem_info->dimm[index].ddr_frequency = + mem_info->dimm[index].ddr_speed_mts = memory_info_hob->MemoryFrequencyInMHz; mem_info->dimm[index].channel_num = channel_info->ChannelId; -- To view, visit https://review.coreboot.org/c/coreboot/+/44549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Gerrit-Change-Number: 44549 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

9 39

Change in coreboot[master]: soc/intel/cnl: Allow using the remaining Comet Lake FSPs
by Michael Niewöhner (Code Review) 03 Sep '20

03 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44954 ) Change subject: soc/intel/cnl: Allow using the remaining Comet Lake FSPs ...................................................................... soc/intel/cnl: Allow using the remaining Comet Lake FSPs To allow using the 3 remaining Comet Lake SoCs, add a new Kconfig option for each of them and configure the paths to FSP header files and FSP binary. Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Michael Niewöhner --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4826a35..9ff2827 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -51,6 +51,18 @@ bool select SOC_INTEL_COMETLAKE +config SOC_INTEL_COMETLAKE_2 + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_S + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_V + bool + select SOC_INTEL_COMETLAKE + config SOC_INTEL_CANNONLAKE_PCH_H bool help @@ -318,11 +330,17 @@ config FSP_HEADER_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/44954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Gerrit-Change-Number: 44954 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: 3rdparty/fsp: Update submodule pointer to current master
by Michael Niewöhner (Code Review) 03 Sep '20

03 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44953 ) Change subject: 3rdparty/fsp: Update submodule pointer to current master ...................................................................... 3rdparty/fsp: Update submodule pointer to current master Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner --- M 3rdparty/fsp M src/soc/intel/cannonlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/3rdparty/fsp b/3rdparty/fsp index 0bc2b07..eb25f19 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 +Subproject commit eb25f19ef7fbe88fb207c6896a37a2035bba9bc5 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5b6295a..4826a35 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -322,7 +322,7 @@ config FSP_FD_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE_1 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1 config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/44953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c Gerrit-Change-Number: 44953 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cnl: Add new Kconfig option which matches its FSPs name
by Michael Niewöhner (Code Review) 03 Sep '20

03 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44952 ) Change subject: soc/intel/cnl: Add new Kconfig option which matches its FSPs name ...................................................................... soc/intel/cnl: Add new Kconfig option which matches its FSPs name Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/system76/lemp9/Kconfig M src/soc/intel/cannonlake/Kconfig 5 files changed, 10 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index df67a8d..ae10b78 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -16,7 +16,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ee9210d..690acd1 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -39,7 +39,7 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT if BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 519cd50..e03e862 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -14,4 +14,4 @@ select SOC_INTEL_COFFEELAKE config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index ef7c89a..6f2bee7 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -13,7 +13,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..5b6295a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -47,6 +47,10 @@ help Intel Cometlake support +config SOC_INTEL_COMETLAKE_1 + bool + select SOC_INTEL_COMETLAKE + config SOC_INTEL_CANNONLAKE_PCH_H bool help @@ -313,12 +317,12 @@ config FSP_HEADER_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1 default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE_1 config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/44952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Gerrit-Change-Number: 44952 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cnl: Add new Kconfig option which matches its FSPs name
by Michael Niewöhner (Code Review) 03 Sep '20

03 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44952 ) Change subject: soc/intel/cnl: Add new Kconfig option which matches its FSPs name ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Gerrit-Change-Number: 44952 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 03 Sep 2020 21:04:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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