coreboot-gerrit September 2020

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Change in coreboot[master]: soc/amd/picasso: Add config for PSP verstage signing token
by Martin Roth (Code Review) 03 Sep '20

03 Sep '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44989 ) Change subject: soc/amd/picasso: Add config for PSP verstage signing token ...................................................................... soc/amd/picasso: Add config for PSP verstage signing token This allows a platform to specify the location of the signing token for the PSP verstage, and build it into the firmware image. BUG=b:166108929 TEST=Build file into PSP firmware, verify that it's present and has the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44989/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 33db89b..ec5ff76 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -497,6 +497,13 @@ help Add psp_verstage file to the build & PSP Directory Table +config PSP_VERSTAGE_SIGNING_TOKEN + string "Specify the PSP_verstage Signature Token file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "" + help + Add psp_verstage signature token to the build & PSP Directory Table + endmenu diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e64ab0a..f7f64ef 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -250,6 +250,7 @@ # type = 0x52 - PSP Bootloader Userspace Application (verstage) PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) @@ -301,6 +302,7 @@ OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ @@ -439,6 +441,7 @@ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd @@ -448,6 +451,7 @@ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB0_NV_SIZE) \ $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 Gerrit-Change-Number: 44989 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Allow use of pre-built PSP verstage
by Martin Roth (Code Review) 03 Sep '20

03 Sep '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44988 ) Change subject: soc/amd/picasso: Allow use of pre-built PSP verstage ...................................................................... soc/amd/picasso: Allow use of pre-built PSP verstage To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44988/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 642935f..33db89b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -490,6 +490,13 @@ help Select this item to enable secure debug options in PSP. +config PSP_VERSTAGE_FILE + string "Specify the PSP_verstage file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "$(obj)/psp_verstage.bin" + help + Add psp_verstage file to the build & PSP Directory Table + endmenu diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 970ff33..e64ab0a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -249,7 +249,7 @@ endif # type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) -- To view, visit https://review.coreboot.org/c/coreboot/+/44988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Gerrit-Change-Number: 44988 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: Add PSP verstage signature entry
by Martin Roth (Code Review) 03 Sep '20

03 Sep '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44987 ) Change subject: util/amdfwtool: Add PSP verstage signature entry ...................................................................... util/amdfwtool: Add PSP verstage signature entry Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44987/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 299ed0c..f385068 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -308,6 +308,7 @@ AMD_FW_PSP_WHITELIST = 0x3a, AMD_FW_L2_PTR = 0x40, AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, @@ -364,6 +365,7 @@ { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, + { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, }; @@ -1085,8 +1087,8 @@ LONGOPT_SPI_MICRON_FLAG = 258, }; -// Unused values: DE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:"; +// Unused values: D +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1119,6 +1121,7 @@ {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, {"verstage", required_argument, 0, 'Z' }, + {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ {"instance", required_argument, 0, 'I' }, {"apcb", required_argument, 0, 'a' }, @@ -1536,6 +1539,10 @@ register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'E': + register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + sub = instance = 0; + break; case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 Gerrit-Change-Number: 44987 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google/tmpl/puff: Update DPTF to the new implementation
by Paul Fagerburg (Code Review) 03 Sep '20

03 Sep '20

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45073 ) Change subject: util/mb/google/tmpl/puff: Update DPTF to the new implementation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Gerrit-Change-Number: 45073 Gerrit-PatchSet: 2 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Comment-Date: Thu, 03 Sep 2020 16:13:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
by Tim Wawrzynczak (Code Review) 03 Sep '20

03 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44857 ) Change subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock ...................................................................... Patch Set 4: Code-Review+2 Thanks Subrata! -- To view, visit https://review.coreboot.org/c/coreboot/+/44857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Gerrit-Change-Number: 44857 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Sep 2020 15:59:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/device/pci_def.h: Re-order PCIE Extended capabilitys
by HAOUAS Elyes (Code Review) 03 Sep '20

03 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45081 ) Change subject: include/device/pci_def.h: Re-order PCIE Extended capabilitys ...................................................................... include/device/pci_def.h: Re-order PCIE Extended capabilitys Change-Id: I542251101c42f1b49ff2b50de4310fb2efe8a040 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/pci_def.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45081/1 diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 2a13e2a..7417c86 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -464,8 +464,8 @@ /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 #define PCIE_EXT_CAP_AER_ID 0x0001 -#define PCIE_EXT_CAP_L1SS_ID 0x001E #define PCIE_EXT_CAP_LTR_ID 0x0018 +#define PCIE_EXT_CAP_L1SS_ID 0x001E /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542251101c42f1b49ff2b50de4310fb2efe8a040 Gerrit-Change-Number: 45081 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google/tmpl/puff: Update DPTF to the new implementation
by Edward O'Callaghan (Code Review) 03 Sep '20

03 Sep '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45073 ) Change subject: util/mb/google/tmpl/puff: Update DPTF to the new implementation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Gerrit-Change-Number: 45073 Gerrit-PatchSet: 2 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Sep 2020 12:58:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/mb/google/tmpl/puff: Update DPTF to the new implementation
by Sam McNally (Code Review) 03 Sep '20

03 Sep '20

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45073 ) Change subject: util/mb/google/tmpl/puff: Update DPTF to the new implementation ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Gerrit-Change-Number: 45073 Gerrit-PatchSet: 2 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Sep 2020 12:49:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_class.c: Update Sub-Class
by HAOUAS Elyes (Code Review) 03 Sep '20

03 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45071 ) Change subject: device/pci_class.c: Update Sub-Class ...................................................................... device/pci_class.c: Update Sub-Class Change-Id: I1fbc832972feb4dbcba02713961f3c96e77a46b2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_class.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45071/1 diff --git a/src/device/pci_class.c b/src/device/pci_class.c index 460d853..621a76b 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -66,6 +66,7 @@ static const PCI_SUBCLASS memory[] = { { 0x00, "RAM memory" }, { 0x01, "FLASH memory" }, + { 0x02, "CXL Memory Device" }, { 0x80, "Memory controller" } }; @@ -168,7 +169,8 @@ { 0x01, "Satellite TV controller" }, { 0x02, "Satellite audio communication controller" }, { 0x03, "Satellite voice communication controller" }, - { 0x04, "Satellite data communication controller" } + { 0x04, "Satellite data communication controller" }, + { 0x80, "Satellite communication controller" } }; static const PCI_SUBCLASS encryption[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbc832972feb4dbcba02713961f3c96e77a46b2 Gerrit-Change-Number: 45071 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by Ravi kumar (Code Review) 03 Sep '20

03 Sep '20

Ravi kumar has uploaded a new patch set (#85) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... HACK trogdor: optimize coreboot.rom for T32 flash script HACK Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/security/vboot/Makefile.inc A util/qualcomm/optimize_coreboot 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36278/85 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 85 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2020