coreboot-gerrit September 2020

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Change in coreboot[master]: mb/system76/lemp9: Fix GPIO comments
by Jeremy Soller (Code Review) 03 Sep '20

03 Sep '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43627 ) Change subject: mb/system76/lemp9: Fix GPIO comments ...................................................................... mb/system76/lemp9: Fix GPIO comments Only a comment change, some GPIOs were incorrectly named Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I1f45f93c3900fab2eb3c1c4bc7a491541a84661f --- M src/mainboard/system76/lemp9/gpio.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/43627/1 diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index 881bd36..312cd87 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -151,11 +151,11 @@ PAD_CFG_NC(GPP_B6), // WLAN_CLKREQ# PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - // LAN_CLKREQ# + // CARD_CLKREQ# PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - // TBT_CLKREQ# + // SSD2_CLKREQ# PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - // SSD_CLKREQ# + // SSD1_CLKREQ# PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // Power Management -- To view, visit https://review.coreboot.org/c/coreboot/+/43627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f45f93c3900fab2eb3c1c4bc7a491541a84661f Gerrit-Change-Number: 43627 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer: route GPP_F14 via APIC
by Alex Levin (Code Review) 03 Sep '20

03 Sep '20

Alex Levin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44948 ) Change subject: mb/google/volteer/variants/volteer: route GPP_F14 via APIC ...................................................................... mb/google/volteer/variants/volteer: route GPP_F14 via APIC GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162722965 TEST=verified on a volteer Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905 Signed-off-by: Alex Levin <levinale(a)google.com> --- M src/mainboard/google/volteer/variants/volteer/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44948/1 diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index fd355a8..2d0d5e0 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -125,7 +125,7 @@ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, INVERT), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905 Gerrit-Change-Number: 44948 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Add new Kconfig option which matches its FSPs name
by Felix Singer (Code Review) 03 Sep '20

03 Sep '20

Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44952 to look at the new patch set (#2). Change subject: soc/intel/cnl: Add new Kconfig option which matches its FSPs name ...................................................................... soc/intel/cnl: Add new Kconfig option which matches its FSPs name Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/system76/lemp9/Kconfig M src/soc/intel/cannonlake/Kconfig 5 files changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44952/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Gerrit-Change-Number: 44952 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: crossgcc: Ensure that GMP is built for a generic CPU on x86
by Patrick Georgi (Code Review) 03 Sep '20

03 Sep '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45044 ) Change subject: crossgcc: Ensure that GMP is built for a generic CPU on x86 ...................................................................... crossgcc: Ensure that GMP is built for a generic CPU on x86 While GMP supports fat builds on x86 that adapt to the CPU's capabilities, by default it builds for the CPU of the builder. Running that binary on an older CPU then can fail. Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A util/crossgcc/patches/gmp-6.2.0_generic-build.patch 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/45044/1 diff --git a/util/crossgcc/patches/gmp-6.2.0_generic-build.patch b/util/crossgcc/patches/gmp-6.2.0_generic-build.patch new file mode 100644 index 0000000..a05635f --- /dev/null +++ b/util/crossgcc/patches/gmp-6.2.0_generic-build.patch @@ -0,0 +1,20 @@ +Ensure that GMP is built for a generic CPU on x86 + +While GMP supports fat builds on x86 that adapt to the CPU's +capabilities, by default it builds for the CPU of the builder. +Running that binary on an older CPU then can fail. +--- gmp-6.2.0/config.guess~ 2020-09-02 19:23:01.817510842 +0200 ++++ gmp-6.2.0/config.guess 2020-09-02 19:24:55.742325907 +0200 +@@ -1029,6 +1029,12 @@ + virtualisers allow guests to set a broken state. */ + suffix = "noavx"; + ++ if (cpuid_64bit) { ++ modelstr="x86_64"; ++ } else { ++ modelstr="pentium"; ++ } ++ suffix=""; + printf ("%s%s", modelstr, suffix); + return 0; + } -- To view, visit https://review.coreboot.org/c/coreboot/+/45044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74 Gerrit-Change-Number: 45044 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/tpm/tis.c: Remove unused TPM_CMD_ORDINAL_BYTE macro
by HAOUAS Elyes (Code Review) 03 Sep '20

03 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45090 ) Change subject: drivers/i2c/tpm/tis.c: Remove unused TPM_CMD_ORDINAL_BYTE macro ...................................................................... drivers/i2c/tpm/tis.c: Remove unused TPM_CMD_ORDINAL_BYTE macro Change-Id: I54392a99d788b64d75f29682794dd1e9cc4bc1c5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/i2c/tpm/tis.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45090/1 diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 217d8c6..99a1ecd 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -17,7 +17,6 @@ static struct tpm_chip chip; #define TPM_CMD_COUNT_BYTE 2 -#define TPM_CMD_ORDINAL_BYTE 6 int tis_open(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54392a99d788b64d75f29682794dd1e9cc4bc1c5 Gerrit-Change-Number: 45090 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: tpm/tss/tcg-2.0/tss_marshaling.c: Remove unused unmarshal_TPM_HANDLE ...
by HAOUAS Elyes (Code Review) 03 Sep '20

03 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45089 ) Change subject: tpm/tss/tcg-2.0/tss_marshaling.c: Remove unused unmarshal_TPM_HANDLE macro ...................................................................... tpm/tss/tcg-2.0/tss_marshaling.c: Remove unused unmarshal_TPM_HANDLE macro Found-by: gcc using -Wunused-macros warning option Change-Id: I6276419d913dd45e75d574ebd7e41e8f581f07ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45089/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f31c7d0..8b35d40 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -13,7 +13,6 @@ #define unmarshal_TPM_CAP(a, b) ibuf_read_be32(a, b) #define unmarshal_TPM_CC(a, b) ibuf_read_be32(a, b) #define unmarshal_TPM_PT(a, b) ibuf_read_be32(a, b) -#define unmarshal_TPM_HANDLE(a, b) ibuf_read_be32(a, b) #define marshal_TPM_HANDLE(a, b) obuf_write_be32(a, b) #define marshal_TPMI_ALG_HASH(a, b) obuf_write_be16(a, b) -- To view, visit https://review.coreboot.org/c/coreboot/+/45089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6276419d913dd45e75d574ebd7e41e8f581f07ac Gerrit-Change-Number: 45089 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: Fix warning taking address of packed struct member
by Martin Roth (Code Review) 03 Sep '20

03 Sep '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44986 ) Change subject: util/amdfwtool: Fix warning taking address of packed struct member ...................................................................... util/amdfwtool: Fix warning taking address of packed struct member GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44986/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 499a1bd..299ed0c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -888,6 +888,8 @@ unsigned int i, count; int level; int apob_idx; + uint32_t size; + uint64_t source; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -996,10 +998,11 @@ break; case AMD_BIOS_BIN: /* Don't make a 2nd copy, point to the same one */ - if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, - &biosdir->entries[count].source, - &biosdir->entries[count].size)) + if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { + biosdir->entries[count].source = source; + biosdir->entries[count].size = size; break; + } /* level 2, or level 1 and no copy found in level 2 */ biosdir->entries[count].source = fw_table[i].src; -- To view, visit https://review.coreboot.org/c/coreboot/+/44986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Gerrit-Change-Number: 44986 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST-ONLY: mb/google/dedede: Add ACPI support for camera in waddledee
by Evan Green (Code Review) 03 Sep '20

03 Sep '20

Hello Varshit B Pandya, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45080 to review the following change. Change subject: TEST-ONLY: mb/google/dedede: Add ACPI support for camera in waddledee ...................................................................... TEST-ONLY: mb/google/dedede: Add ACPI support for camera in waddledee 1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI9734 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor EVAN: Replace instances of I2C3 with I2C5 in cam0.asl BUG=None BRANCH=None TEST=Build and Boot waddledee board and able to capture image using world facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: Ic3530beb74dcfc26ddd12f39097dc46571b1c224 --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl 6 files changed, 572 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/45080/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 40738a0..d4a2139 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -49,6 +49,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WHEELIE bool "Wheelie" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl new file mode 100644 index 0000000..03e62f7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C5) +{ + Name (STA0, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + IF(!STA1) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* Deassert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA0 = 1 + } + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + IF(!STA1) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA0 = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hadware ID */ + + Name (_UID, 0x03) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ + { + FCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package(0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..6a75870 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(0, 1) /* Clock 0, 19.2MHz */ + /* Check if another sensor is ON */ + IF(!STA0) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D15) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D15) + Sleep(5) /* 5 us */ + STA1 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(0) /* Clock 0 */ + /* Assert Reset */ + CTXS(GPP_D15) + IF(!STA0) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA1 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA1) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI9734") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x0ABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl new file mode 100644 index 0000000..51b4ebc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..a502139 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..34c3d4b --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3530beb74dcfc26ddd12f39097dc46571b1c224 Gerrit-Change-Number: 45080 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/cavium/common/ecam.c: Use 'PCI_*' macros instead of magic number
by HAOUAS Elyes (Code Review) 03 Sep '20

03 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44827 ) Change subject: soc/cavium/common/ecam.c: Use 'PCI_*' macros instead of magic number ...................................................................... soc/cavium/common/ecam.c: Use 'PCI_*' macros instead of magic number Change-Id: Ie0657123b0eab4bf63f34aea751e632bf091abc5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/cavium/common/ecam.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44827/1 diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index 88368178..596501a 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -20,7 +20,7 @@ */ uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) { - size_t cap_offset = pci_s_find_capability(dev, 0x14); + size_t cap_offset = pci_s_find_capability(dev, PCI_BASE_ADDRESS_1); uint64_t h, l, ret = 0; if (cap_offset) { /* Found EA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0657123b0eab4bf63f34aea751e632bf091abc5 Gerrit-Change-Number: 44827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/amd/picasso: Only build PSP bootloader & verstage into RO
by Martin Roth (Code Review) 03 Sep '20

03 Sep '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44990 ) Change subject: soc/amd/picasso: Only build PSP bootloader & verstage into RO ...................................................................... soc/amd/picasso: Only build PSP bootloader & verstage into RO The PSP bootloader and verstage are only used out of the RO region, so don't build them into the RW sections. BUG=None TEST=Build & Boot BRANCH=zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44990/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f7f64ef..f4ec6c9 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -335,7 +335,6 @@ endif AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ $(OPT_PSPSCUREOS_FILE) \ $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_SMUFW1_SUB2_FILE) \ @@ -374,7 +373,6 @@ $(OPT_PSP_S0I3_FILE) \ $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ - $(OPT_VERSTAGE_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ --combo-capable \ @@ -448,9 +446,11 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB0_NV_SIZE) \ $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c Gerrit-Change-Number: 44990 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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