coreboot-gerrit September 2020

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Change in coreboot[master]: Documentation: Add ASan documentation
by Paul Menzel (Code Review) 05 Sep '20

05 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 ) Change subject: Documentation: Add ASan documentation ...................................................................... Patch Set 6: Code-Review+1 Very nice! -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 6 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Sep 2020 07:49:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add ASan documentation
by Harshit Sharma (Code Review) 05 Sep '20

05 Sep '20

Hello Patrick Georgi, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44814 to look at the new patch set (#6). Change subject: Documentation: Add ASan documentation ...................................................................... Documentation: Add ASan documentation Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A Documentation/technotes/asan.md M Documentation/technotes/index.md 2 files changed, 302 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44814/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 6 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Add ASan documentation
by Harshit Sharma (Code Review) 05 Sep '20

05 Sep '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 ) Change subject: Documentation: Add ASan documentation ...................................................................... Patch Set 5: (5 comments) > Patch Set 4: > > (3 comments) > > Thank you for writing this. https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… File Documentation/technotes/asan.md: https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… PS4, Line 9: Address Sanitizer > Add a link to its Web site? Done https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… PS4, Line 93: Now, we have to use `ip` to retrieve the instruction which causes the error. : For this, first subtract the start address of the stage from `ip`. Now, : read the section headers from `<stage>.debug` file to determine the offset of : the text segment. Add this offset to the difference you calculated earlier. : Let's call the resultant address `ip'`. : : Next, read the contents of the symbol table and search for a function having : an address closest to `ip'`. This is the function in which our memory bug is : present. Let's denote the address of this function by `ip''`. (To get the : symbols in a sorted fashion. you should use `readelf` instead of `objdump`.) : : Finally, read the assembly contents of the object file where this function is : present. Look for the affected function. Here, the instruction which exists at : the offset `ip' - ip''` corresponds to the address `ip`. Therefore, the very : next instruction is the one which causes the error. > This is nice written. […] Done https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… PS4, Line 126: Apollolake > Apollo Lake Done https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… PS4, Line 130: ``` > Probably it is hard to keep this list updated. […] Done https://review.coreboot.org/c/coreboot/+/44814/4/Documentation/technotes/as… PS4, Line 145: platform. > Maybe add something the like: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 5 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 05 Sep 2020 02:38:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Nico Huber (Code Review) 05 Sep '20

05 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45112/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45112/2/src/soc/intel/cannonlake/f… PS2, Line 376: params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; Why the indirection when we can have a simple if/else here? Or can't we? -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Sep 2020 22:33:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL'
by HAOUAS Elyes (Code Review) 04 Sep '20

04 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44976 ) Change subject: mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL' ...................................................................... mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL' CPU_INTEL_HASWELL is already selected at nb/intel/haswell/Kconfig. Change-Id: I608286aae72bc740be642a72109472fb235f37bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig 7 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/44976/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 0a13281..844604a 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 6203610..6406417 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 0c9311f..0ac6805 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO def_bool n - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 37c11e0..931d3ce 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY def_bool n select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 8268891..b2d0653 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 32dde6f..b84576d 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -3,7 +3,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 - select CPU_INTEL_HASWELL select EC_LENOVO_H8 select H8_HAS_PRIMARY_FN_KEYS select EC_LENOVO_PMH7 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index dde9bc1..598fbbe 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select CPU_INTEL_HASWELL select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/44976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I608286aae72bc740be642a72109472fb235f37bf Gerrit-Change-Number: 44976 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/xhci: Fix Slot State field width definition
by Nico Huber (Code Review) 04 Sep '20

04 Sep '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45023 ) Change subject: libpayload/xhci: Fix Slot State field width definition ...................................................................... libpayload/xhci: Fix Slot State field width definition According to the xHCI spec, the Slot State field in the Slot Context Data Structure is 5 bits wide. So, fix the code to match. ref. xHCI spec 1.2 section 6.2.2, Figure 6-2: Slot Context Data Structure BUG=none TEST=xHCI compiles Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45023 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/drivers/usb/xhci_private.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index b4c8825..137c88e 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -204,7 +204,7 @@ #define SC_UADDR_LEN 8 #define SC_STATE_FIELD f4 /* STATE - Slot State */ #define SC_STATE_START 27 -#define SC_STATE_LEN 8 +#define SC_STATE_LEN 5 #define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN) #define SC_GET(tok, sc) (((sc)->SC_##tok##_FIELD & SC_MASK(tok)) \ >> SC_##tok##_START) -- To view, visit https://review.coreboot.org/c/coreboot/+/45023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Gerrit-Change-Number: 45023 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/xhci: Fix Slot State field width definition
by Nico Huber (Code Review) 04 Sep '20

04 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45023 ) Change subject: libpayload/xhci: Fix Slot State field width definition ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1 Gerrit-Change-Number: 45023 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Sep 2020 19:13:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_...
by HAOUAS Elyes (Code Review) 04 Sep '20

04 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44931 ) Change subject: soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_COMMON_SMM' ...................................................................... soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_COMMON_SMM' CPU_INTEL_COMMON_SMM is set to yes if CPU_INTEL_COMMON at cpu/intel/common/Kconfig. Change-Id: I7c8e1bb6b7c3199a24711b64a6cbba4de190c6d9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44931/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index fd5648f..15dc1b3 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -36,7 +36,6 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..182c5ad 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -36,7 +36,6 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/44931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8e1bb6b7c3199a24711b64a6cbba4de190c6d9 Gerrit-Change-Number: 44931 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb: remove duplicated Make code for spd.bin generation
by Nico Huber (Code Review) 04 Sep '20

04 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44774 ) Change subject: mb: remove duplicated Make code for spd.bin generation ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Gerrit-Change-Number: 44774 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Sep 2020 18:48:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/roda/rk9/Kconfig: Drop redundant 'select CARDBUS_PLUGIN_SUPPORT'
by HAOUAS Elyes (Code Review) 04 Sep '20

04 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44932 ) Change subject: mb/roda/rk9/Kconfig: Drop redundant 'select CARDBUS_PLUGIN_SUPPORT' ...................................................................... mb/roda/rk9/Kconfig: Drop redundant 'select CARDBUS_PLUGIN_SUPPORT' CARDBUS_PLUGIN_SUPPORT is set to yes at device/Kconfig file. Change-Id: Ief8664649c9dd58bcd1135b7251105c965c8e33e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/roda/rk9/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44932/1 diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index f45f255..182fee4 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -10,7 +10,6 @@ select BOARD_ROMSIZE_KB_4096 select DRIVERS_GENERIC_IOAPIC select HAVE_MP_TABLE - select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select EC_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/44932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8664649c9dd58bcd1135b7251105c965c8e33e Gerrit-Change-Number: 44932 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020