coreboot-gerrit September 2020

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Change in coreboot[master]: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY
by Felix Singer (Code Review) 06 Sep '20

06 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45125 ) Change subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY ...................................................................... Patch Set 1: Code-Review+1 (4 comments) https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/halvor/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/google/volte… PS1, Line 17: Remove this empty line here. https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/prodrive/her… File src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/prodrive/her… PS1, Line 121: # unused Drop this. https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… File src/mainboard/supermicro/x11-lga1151-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… PS1, Line 42: # USB : register "usb2_ports" = "{ Drop this. https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… PS1, Line 59: register "usb3_ports" = "{ Drop this. -- To view, visit https://review.coreboot.org/c/coreboot/+/45125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Gerrit-Change-Number: 45125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Sep 2020 00:59:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Felix Singer (Code Review) 06 Sep '20

06 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Sep 2020 22:45:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Christian Walter, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45112 to look at the new patch set (#5). Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Note: this changes the boards' ports where USBx_PORT_EMPTY is already missing. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 50 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45112/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "soc/intel/cnl: Enable HECI3 depending on devicetree"
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44994 to review the following change. Change subject: Revert "soc/intel/cnl: Enable HECI3 depending on devicetree" ...................................................................... Revert "soc/intel/cnl: Enable HECI3 depending on devicetree" This reverts commit d9e459428de519c89b23f9a7465bcb7b835c08a0. Reason for revert: the Fsp option is not meant to be set that way Change-Id: I1469ce3443e70c1ee5c841846ddeae7d4eebb9e5 --- M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44994/1 diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 5615554..69323f2 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -28,7 +28,7 @@ register "HeciEnabled" = "1" end device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 off end # Management Engine Interface 3 + device pci 16.4 on end # Management Engine Interface 3 device pci 17.0 on end # SATA device pci 1d.6 on # PCIe root port 15 device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index b85e10f..fc3f418 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -277,7 +277,9 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index e9e3aa3..c07b687 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -201,7 +201,9 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 9e7aa45..e5ceac9 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -228,6 +228,7 @@ uint8_t PchIshEnable; /* Heci related */ + uint8_t Heci3Enabled; uint8_t DisableHeciRetry; /* Gfx related */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 615a94f..51ed2a8 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -525,8 +525,7 @@ else params->ScsUfsEnabled = dev->enabled; - dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); - params->Heci3Enabled = is_dev_enabled(dev); + params->Heci3Enabled = config->Heci3Enabled; #if !CONFIG(HECI_DISABLE_USING_SMM) dev = pcidev_path_on_root(PCH_DEVFN_CSE); params->Heci1Disabled = !is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/44994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1469ce3443e70c1ee5c841846ddeae7d4eebb9e5 Gerrit-Change-Number: 44994 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45112/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45112/3//COMMIT_MSG@11 PS3, Line 11: this case. > Please mention that this changes the behaviour of some hidden FSP […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Sep 2020 20:33:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Christian Walter, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45112 to look at the new patch set (#4). Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 50 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45112/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: edid_fill_fb: Add row_alignment argument
by Patrick Rudolph (Code Review) 05 Sep '20

05 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39430 ) Change subject: edid_fill_fb: Add row_alignment argument ...................................................................... edid_fill_fb: Add row_alignment argument Calculate bytes_per_line internally if not set by using a new row_alignment argument in bytes. If row_alignment is set to 0 the bytes_per_line will not be aligned. Future patches will get rid of externally provided bytes_per_line. Change-Id: I4ce88193c5e324a2a7b04e0a7e3438172afca038 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/gma/gma-gfx_init.ads M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb M src/drivers/xgi/common/xgi_coreboot.c M src/include/edid.h M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/northbridge/intel/i945/gma.c M src/soc/nvidia/tegra124/display.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3399/display.c 21 files changed, 56 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39430/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 660b5f0..fe15c48 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -377,6 +377,7 @@ le16_to_cpu(mode_info.vesa.y_resolution), le16_to_cpu(mode_info.vesa.bytes_per_scanline), mode_info.vesa.bits_per_pixel, + 0, mode_info.vesa.reserved_mask_pos, mode_info.vesa.reserved_mask_size, mode_info.vesa.red_mask_pos, diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index e7faf9a..cb7d5b6 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -761,6 +761,7 @@ le16_to_cpu(mode_info.vesa.y_resolution), le16_to_cpu(mode_info.vesa.bytes_per_scanline), mode_info.vesa.bits_per_pixel, + 0, mode_info.vesa.reserved_mask_pos, mode_info.vesa.reserved_mask_size, mode_info.vesa.red_mask_pos, diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2ec85ac..f9a02e3 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -247,7 +247,7 @@ ast_hide_cursor(&crtc); /* Advertise new mode */ - set_vbe_mode_info_valid(&edid, fb.mmio_addr); + set_vbe_mode_info_valid(&edid, fb.mmio_addr, 8); /* Clear display */ memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d9e4ce1..91aa413 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -118,7 +118,7 @@ edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + set_vbe_mode_info_valid(&edid, addr, 0); } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 6b1968c..4968613 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -318,7 +318,7 @@ edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + set_vbe_mode_info_valid(&edid, addr, 0); } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index e2c6336..7fcb1c3 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -36,7 +36,8 @@ vbt_gop->GraphicsMode.HorizontalResolution, vbt_gop->GraphicsMode.VerticalResolution, vbt_gop->GraphicsMode.PixelsPerScanLine * 4, - 32); + 32, + 0); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 3d06336..f5a2d2e 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -110,6 +110,7 @@ ginfo->vertical_resolution, ginfo->pixels_per_scanline * 4, 32, + 0, fbinfo->rsvd.pos, fbinfo->rsvd.size, fbinfo->red.pos, diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads index 31ab5cf..f9e0fe4 100644 --- a/src/drivers/intel/gma/gma-gfx_init.ads +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -16,7 +16,8 @@ x_resolution : word32; y_resolution : word32; bytes_per_line : word32; - bits_per_pixel : word8) + bits_per_pixel : word8; + row_alignment : word32) return Interfaces.C.int; pragma import (C, c_fb_set_framebuffer_info, "fb_set_framebuffer_info"); diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 0ecf14f..2980232 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -21,7 +21,8 @@ x_resolution : word32; y_resolution : word32; bytes_per_line : word32; - bits_per_pixel : word8) + bits_per_pixel : word8; + row_alignment : word32) is use type word32; ignored : Interfaces.C.int; @@ -30,7 +31,8 @@ x_resolution, y_resolution, bytes_per_line, - bits_per_pixel + bits_per_pixel, + row_alignment ); end fb_set_framebuffer_info; @@ -102,7 +104,8 @@ word32(fb.Width), word32(fb.Height), 4 * word32 (fb.Stride), - 32); + 32, + 16); end if; end if; end if; diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 9c60e3a..b52cad0 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -363,7 +363,8 @@ xgifb_info->video_width, xgifb_info->video_height, xgifb_info->video_width * xgifb_info->video_bpp, - xgifb_info->video_bpp); + xgifb_info->video_bpp, + 0); } else { /* * FIXME diff --git a/src/include/edid.h b/src/include/edid.h index 70d21eb..b630b14 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -109,7 +109,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -struct fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); +struct fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr, + uint32_t row_alignment); void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 70ec11c..1bdffe0 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -28,15 +28,15 @@ bool fb_fill_framebuffer_info_ex(struct fb_info *info, uintptr_t fb_addr, uint32_t x_resolution, uint32_t y_resolution, uint32_t bytes_per_line, - uint8_t bits_per_pixel, uint8_t reserved_mask_pos, - uint8_t reserved_mask_size, uint8_t red_mask_pos, - uint8_t red_mask_size, uint8_t green_mask_pos, - uint8_t green_mask_size, uint8_t blue_mask_pos, - uint8_t blue_mask_size); + uint8_t bits_per_pixel, uint32_t row_alignment, + uint8_t reserved_mask_pos, uint8_t reserved_mask_size, + uint8_t red_mask_pos, uint8_t red_mask_size, + uint8_t green_mask_pos, uint8_t green_mask_size, + uint8_t blue_mask_pos, uint8_t blue_mask_size); struct fb_info *fb_set_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution, uint32_t y_resolution, uint32_t bytes_per_line, - uint8_t bits_per_pixel); + uint8_t bits_per_pixel, uint32_t row_alignment); void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation); diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 8a1613e..89a62b2 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -56,11 +56,11 @@ bool fb_fill_framebuffer_info_ex(struct fb_info *info, uintptr_t fb_addr, uint32_t x_resolution, uint32_t y_resolution, uint32_t bytes_per_line, - uint8_t bits_per_pixel, uint8_t reserved_mask_pos, - uint8_t reserved_mask_size, uint8_t red_mask_pos, - uint8_t red_mask_size, uint8_t green_mask_pos, - uint8_t green_mask_size, uint8_t blue_mask_pos, - uint8_t blue_mask_size) + uint8_t bits_per_pixel, uint32_t row_alignment, + uint8_t reserved_mask_pos, uint8_t reserved_mask_size, + uint8_t red_mask_pos, uint8_t red_mask_size, + uint8_t green_mask_pos, uint8_t green_mask_size, + uint8_t blue_mask_pos, uint8_t blue_mask_size) { /* Validate */ if (!info) @@ -77,6 +77,14 @@ y_resolution, (bytes_per_line * y_resolution), (void *)fb_addr); + if (!row_alignment) + row_alignment = 1; + + if (!bytes_per_line) + bytes_per_line = x_resolution * bits_per_pixel / 8; + + bytes_per_line = ALIGN_UP(bytes_per_line, row_alignment); + /* Update */ info->edid_fb.physical_address = fb_addr; info->edid_fb.x_resolution = x_resolution; @@ -107,8 +115,8 @@ */ struct fb_info * fb_set_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution, - uint32_t y_resolution, uint32_t bytes_per_line, - uint8_t bits_per_pixel) + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel, uint32_t row_alignment) { struct fb_info *info = fb_new_framebuffer_info(); if (!info) @@ -119,7 +127,8 @@ case 24: /* packed into 4-byte words */ if (!fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, - bytes_per_line, bits_per_pixel, 24, 8, 16, 8, 8, 8, 0, 8)) { + bytes_per_line, bits_per_pixel, row_alignment, 24, 8, 16, 8, 8, 8, + 0, 8)) { printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__); free(info); return NULL; @@ -128,7 +137,8 @@ case 16: /* packed into 2-byte words */ if (!fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, - bytes_per_line, bits_per_pixel, 0, 0, 11, 5, 5, 6, 0, 5)) { + bytes_per_line, bits_per_pixel, row_alignment, 0, 0, 11, 5, 5, 6, + 0, 5)) { printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__); free(info); return NULL; @@ -155,10 +165,11 @@ /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -struct fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr, + uint32_t row_alignment) { return fb_set_framebuffer_info(fb_addr, edid->x_resolution, edid->y_resolution, - edid->bytes_per_line, edid->framebuffer_bits_per_pixel); + edid->bytes_per_line, edid->framebuffer_bits_per_pixel, row_alignment); } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805..05479ed 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -277,7 +277,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr, 0); lcd_vdd(); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 47aa40c..436be30 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -173,7 +173,7 @@ return false; } mtk_ddp_mode_set(edid); - struct fb_info *info = set_vbe_mode_info_valid(edid, 0); + struct fb_info *info = set_vbe_mode_info_valid(edid, 0, 0); if (info) fb_set_orientation(info, panel->s->orientation); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..7fe0408 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -238,7 +238,7 @@ } mtk_ddp_mode_set(&edid); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + set_vbe_mode_info_valid(&edid, (uintptr_t)0, 0); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2ad..3b1c8b0 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -416,7 +416,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr, 0); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98e30e7..f1d20f2 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -386,7 +386,7 @@ (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); - set_vbe_mode_info_valid(&edid, pgfx); + set_vbe_mode_info_valid(&edid, pgfx, 64); } else { vga_misc_write(0x67); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 6fa3bdf..d54c3f0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -330,5 +330,5 @@ edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, config->framebuffer_bits_per_pixel, 32); - set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); + set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB), 32); } diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..54aac15 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -138,5 +138,5 @@ break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase, 0); } diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..401c917 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -174,7 +174,7 @@ break; } mainboard_power_on_backlight(); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + set_vbe_mode_info_valid(&edid, (uintptr_t)0, 0); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ce88193c5e324a2a7b04e0a7e3438172afca038 Gerrit-Change-Number: 39430 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 30

Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Nico Huber (Code Review) 05 Sep '20

05 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/45112/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45112/3//COMMIT_MSG@11 PS3, Line 11: this case. Please mention that this changes the behaviour of some hidden FSP pad configuration logic. e.g. "If an OC pin is not mentioned, FSP won't override its pad configuration." -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Sep 2020 16:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45125 ) Change subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Gerrit-Change-Number: 45125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 05 Sep 2020 11:50:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 05 Sep '20

05 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45112/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45112/2/src/soc/intel/cannonlake/f… PS2, Line 376: params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; > oh, I just realized it's a bad idea to skip programming the other settings (variant 3), since then w […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Sep 2020 11:43:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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coreboot-gerrit September 2020