coreboot-gerrit September 2020

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Change in coreboot[master]: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID
by Johnny Lin (Code Review) 07 Sep '20

07 Sep '20

Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44545 to look at the new patch set (#7). Change subject: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID ...................................................................... mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the SPD register vendor ID String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44545/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/44545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Gerrit-Change-Number: 44545 Gerrit-PatchSet: 7 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/mb/google/tmpl/puff: Update DPTF to the new implementation
by Edward O'Callaghan (Code Review) 07 Sep '20

07 Sep '20

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45073 ) Change subject: util/mb/google/tmpl/puff: Update DPTF to the new implementation ...................................................................... util/mb/google/tmpl/puff: Update DPTF to the new implementation Apply the change in CB:44905 to the puff template, moving DPTF policies from static ASL files into the new SSDT-based DPTF implementation. BUG=b:158986928 BRANCH=puff TEST=None Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Signed-off-by: Sam McNally <sammc(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- D util/mainboard/google/puff/template/include/variant/acpi/dptf.asl M util/mainboard/google/puff/template/overridetree.cb 2 files changed, 65 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Paul Fagerburg: Looks good to me, approved diff --git a/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl b/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 244e678..adb00e4 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -204,6 +204,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793 Gerrit-Change-Number: 45073 Gerrit-PatchSet: 3 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: treewide: stop using hexdumps for spd files
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Frans Hendriks, Jeremy Soller, Angel Pons, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, David Guckian, Martin Roth, Vanessa Eusebio, Alexander Couzens, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44775 to look at the new patch set (#18). Change subject: treewide: stop using hexdumps for spd files ...................................................................... treewide: stop using hexdumps for spd files SPD files normally don't get edited. Keeping the files as hexdump does not have any advantage and conversion from hex to bin adds complexity with a high chance for bugs and other sorts of problems. One example for such problem is an issue that only appeared on one of my systems, where conversion of '01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03: for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1 00000000: 01 32 03 .2. The reason for this was that the syntax in lib/Makefile.inc is wrong and should have been `printf $(printf '\\%03o' 0x$c)`. Instead of fixing this, we should remove some of the aforementioned complexity to lower the probability of future encoding problems. Thus, convert all spd hexdumps to binaries and adapt the Makefiles to just concatenate them to `spd.bin`. The SPDs, manifests and Makefiles for soc/intel/{tiger,jasper}lake and mainboard/google/{dedede,volteer,zork} have been regenerated using the following commands: go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \ util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL go run util/spd_tools/lp4x/gen_spd.go src/soc/intel/tigerlake/spd/ \ util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt TGL go run util/spd_tools/lp4x/gen_spd.go src/soc/intel/jasperlake/spd/ \ util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt JSL for v in src/mainboard/google/zork/variants/*; do [ -f ${v}/spd/mem_parts_used.txt ] || continue go run util/spd_tools/ddr4/gen_part_id.go \ src/mainboard/google/zork/spd \ ${v}/spd ${v}/spd/mem_parts_used.txt done for v in src/mainboard/google/{dedede,volteer}/variants/*; do [ -f ${v}/memory/mem_list_variant.txt ] || continue for m in ddr4 lp4x; do go run ./util/spd_tools/${m}/gen_part_id.go \ src/soc/intel/tigerlake/spd ${v}/memory \ ${v}/memory/mem_list_variant.txt done done All other spd files have been converted with `grep -v "^#" | xxd -ps -r` or `xxd -rg1`, depending on the format. Documentation has been updated where needed. For all affected boards the output binary has been verified to remain identical, using timeless abuild. Exception: google/volteer/variants/lindar will have an empty spd.bin until CB:44848 gets merged. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 --- M .gitignore M Documentation/Intel/Board/board.html M Documentation/soc/amd/family17h.md M src/lib/Kconfig M src/lib/Makefile.inc A src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.bin D src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex A src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.bin D src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex A src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.bin D src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex A src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.bin D src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex A src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.bin D src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.bin D src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex A src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.bin D src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex A src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.bin D src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex M src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc A src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.bin D src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex A src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.bin D src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex M src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc A src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.bin D src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex A src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.bin D src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex M src/mainboard/google/auron/variants/gandof/spd/Makefile.inc A src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.bin D src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex A src/mainboard/google/auron/variants/gandof/spd/empty.spd.bin D src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex M src/mainboard/google/auron/variants/lulu/spd/Makefile.inc A src/mainboard/google/auron/variants/lulu/spd/empty.spd.bin D src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex A src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.bin D src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex A src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.bin D src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex A src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.bin D src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex A src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.bin D src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex A src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.bin D src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex A src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.bin D src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex A src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.bin D src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex M src/mainboard/google/auron/variants/samus/spd/Makefile.inc A src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.bin D src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex A src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.bin D src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex A src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.bin D src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex A src/mainboard/google/auron/variants/samus/spd/empty.spd.bin D src/mainboard/google/auron/variants/samus/spd/empty.spd.hex A src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.bin D src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex A src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.bin D src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex A src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.bin D src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex A src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.bin D src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex A src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.bin D src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex A src/mainboard/google/cyan/spd/empty.spd.bin D src/mainboard/google/cyan/spd/empty.spd.hex A src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.bin D src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex A src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.bin D src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex A src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.bin D src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex A src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.bin D src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex A src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.bin D src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex A src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.bin D src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex A src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.bin D src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.bin D src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.bin D src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.bin D src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.bin D src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.bin D src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex A src/mainboard/google/cyan/spd/micron_dimm_MT52L256M32D1PF-107.spd.bin D src/mainboard/google/cyan/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex A src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.bin D src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.bin D src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.bin D src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCE.spd.bin D src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCE.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.bin D src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.bin D src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex A src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.bin D src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex A src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCF.spd.bin D src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex A src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.bin D src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex M src/mainboard/google/dedede/spd/Makefile.inc M src/mainboard/google/dedede/variants/boten/memory/Makefile.inc M src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc M src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc M src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc M src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc M src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc M src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc M src/mainboard/google/drallion/spd/Makefile.inc A src/mainboard/google/drallion/spd/empty_ddr4.spd.bin D src/mainboard/google/drallion/spd/empty_ddr4.spd.hex A src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.bin D src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex A src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.bin D src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex A src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.bin D src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.bin D src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.bin D src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.bin D src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.bin D src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.bin D src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.bin D src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.bin D src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.bin D src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex A src/mainboard/google/eve/spd/empty.spd.bin D src/mainboard/google/eve/spd/empty.spd.hex A src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.bin D src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex A src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.bin D src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex A src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.bin D src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex A src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.bin D src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.hex A src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.bin D src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex A src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.bin D src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.hex A src/mainboard/google/glados/spd/empty.spd.bin D src/mainboard/google/glados/spd/empty.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.bin D src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex A src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.bin D src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex A src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.bin D src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex A src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.bin D src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex A src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.bin D src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex A src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.bin D src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCG.spd.bin D src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex A src/mainboard/google/hatch/spd/16G_2400.spd.bin D src/mainboard/google/hatch/spd/16G_2400.spd.hex A src/mainboard/google/hatch/spd/16G_2666.spd.bin D src/mainboard/google/hatch/spd/16G_2666.spd.hex A src/mainboard/google/hatch/spd/16G_2666_2bg.spd.bin D src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex A src/mainboard/google/hatch/spd/16G_3200.spd.bin D src/mainboard/google/hatch/spd/16G_3200.spd.hex A src/mainboard/google/hatch/spd/16G_3200_4bg.spd.bin D src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex A src/mainboard/google/hatch/spd/4G_2400.spd.bin D src/mainboard/google/hatch/spd/4G_2400.spd.hex A src/mainboard/google/hatch/spd/8G_2400.spd.bin D src/mainboard/google/hatch/spd/8G_2400.spd.hex A src/mainboard/google/hatch/spd/8G_2666.spd.bin D src/mainboard/google/hatch/spd/8G_2666.spd.hex A src/mainboard/google/hatch/spd/8G_3200.spd.bin D src/mainboard/google/hatch/spd/8G_3200.spd.hex A src/mainboard/google/hatch/spd/LP_16G_2133.spd.bin D src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex A src/mainboard/google/hatch/spd/LP_4G_2133.spd.bin D src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex A src/mainboard/google/hatch/spd/LP_8G_2133.spd.bin D src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex A src/mainboard/google/hatch/spd/empty_ddr4.spd.bin D src/mainboard/google/hatch/spd/empty_ddr4.spd.hex A src/mainboard/google/kahlee/spd/empty.spd.bin D src/mainboard/google/kahlee/spd/empty.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex A src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.bin D src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex A src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.bin D src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex A src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.bin D src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex A src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.bin D src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex A src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.bin D src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex A src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.bin D src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.bin D src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex A src/mainboard/google/link/spd/elpida_4Gb_1600_x16.spd.bin D src/mainboard/google/link/spd/elpida_4Gb_1600_x16.spd.hex A src/mainboard/google/link/spd/micron_4Gb_1600_1.35v_x16.spd.bin D src/mainboard/google/link/spd/micron_4Gb_1600_1.35v_x16.spd.hex A src/mainboard/google/link/spd/samsung_4Gb_1600_1.35v_x16.spd.bin D src/mainboard/google/link/spd/samsung_4Gb_1600_1.35v_x16.spd.hex M src/mainboard/google/poppy/spd/Makefile.inc A src/mainboard/google/poppy/spd/empty.spd.bin D src/mainboard/google/poppy/spd/empty.spd.hex A src/mainboard/google/poppy/spd/empty_ddr4.spd.bin D src/mainboard/google/poppy/spd/empty_ddr4.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NAFR-UHC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NAFR-UHC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NBJR-UHC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NBJR-UHC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NAFR-UHC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NAFR-UHC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAMR-UHC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAMR-UHC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.bin D src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16GE-083E.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16GE-083E.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16LY-075F.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16LY-075F.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16LY-075E.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16LY-075E.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.bin D src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex A src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.bin D src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K3QFAFA0CM-AGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K3QFAFA0CM-AGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4A4G165WE-BCRC.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4A4G165WE-BCRC.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WB-BCRC.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WB-BCRC.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WC-BCTD.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EB-EGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EC-EGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EC-EGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324EB-EGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EB-EGCG.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCF.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCF.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCG.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCG.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.bin D src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex A src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.bin D src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex A src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.bin D src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex A src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.bin D src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex A src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.bin D src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex A src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.bin D src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex A src/mainboard/google/rambi/spd/empty.spd.bin D src/mainboard/google/rambi/spd/empty.spd.hex A src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.bin D src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex A src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.bin D src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex A src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.bin D src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex A src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.bin D src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex A src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.bin D src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex A src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.bin D src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex A src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.bin D src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex A src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.bin D src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex A src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.bin D src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex A src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.bin D src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex A src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.bin D src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex M src/mainboard/google/slippy/variants/falco/Makefile.inc A src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.bin D src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex A src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.bin D src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex M src/mainboard/google/slippy/variants/leon/Makefile.inc A src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.bin D src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex M src/mainboard/google/slippy/variants/peppy/Makefile.inc A src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.bin D src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex A src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6CFR6A.spd.bin D src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6CFR6A.spd.hex A src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex M src/mainboard/google/slippy/variants/wolf/Makefile.inc A src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.bin D src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex A src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.bin D src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex A src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.bin D src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex M src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc M src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc M src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc M src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc M src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc M src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc M src/mainboard/google/volteer/variants/todor/memory/Makefile.inc M src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc M src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc M src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc A src/mainboard/google/zork/spd/ddr4-spd-1.bin D src/mainboard/google/zork/spd/ddr4-spd-1.hex A src/mainboard/google/zork/spd/ddr4-spd-2.bin D src/mainboard/google/zork/spd/ddr4-spd-2.hex A src/mainboard/google/zork/spd/ddr4-spd-3.bin D src/mainboard/google/zork/spd/ddr4-spd-3.hex A src/mainboard/google/zork/spd/ddr4-spd-4.bin D src/mainboard/google/zork/spd/ddr4-spd-4.hex A src/mainboard/google/zork/spd/ddr4-spd-5.bin D src/mainboard/google/zork/spd/ddr4-spd-5.hex A src/mainboard/google/zork/spd/ddr4-spd-6.bin D src/mainboard/google/zork/spd/ddr4-spd-6.hex A src/mainboard/google/zork/spd/ddr4-spd-7.bin D src/mainboard/google/zork/spd/ddr4-spd-7.hex A src/mainboard/google/zork/spd/ddr4-spd-8.bin D src/mainboard/google/zork/spd/ddr4-spd-8.hex A src/mainboard/google/zork/spd/ddr4-spd-empty.bin D src/mainboard/google/zork/spd/ddr4-spd-empty.hex M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt M src/mainboard/google/zork/variants/berknip/spd/Makefile.inc M src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc M src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc M src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc M src/mainboard/google/zork/variants/morphius/spd/Makefile.inc M src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/woomax/spd/Makefile.inc A src/mainboard/hp/snb_ivb_laptops/spd/hynix_4g.spd.bin D src/mainboard/hp/snb_ivb_laptops/spd/hynix_4g.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/empty.spd.bin D src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.bin D src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.bin D src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex A src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.bin D src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex A src/mainboard/intel/icelake_rvp/spd/empty.spd.bin D src/mainboard/intel/icelake_rvp/spd/empty.spd.hex A src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.bin D src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex A src/mainboard/intel/jasperlake_rvp/spd/empty.spd.bin D src/mainboard/intel/jasperlake_rvp/spd/empty.spd.hex A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.bin D src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex A src/mainboard/intel/kblrvp/spd/empty.spd.bin D src/mainboard/intel/kblrvp/spd/empty.spd.hex A src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.bin D src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex A src/mainboard/intel/kblrvp/spd/rvp3.spd.bin D src/mainboard/intel/kblrvp/spd/rvp3.spd.hex A src/mainboard/intel/kunimitsu/spd/empty.spd.bin D src/mainboard/intel/kunimitsu/spd/empty.spd.hex A src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.bin D src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex A src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.bin D src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex A src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.bin D 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A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.bin D src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.bin D src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex A src/mainboard/intel/tglrvp/spd/empty.spd.bin D src/mainboard/intel/tglrvp/spd/empty.spd.hex A src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.bin D src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex A src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.bin D src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex A src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.bin D src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex A src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.bin D src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex A src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.bin D src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex A src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.bin D src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex A src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.bin D src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex M src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc A src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.bin D src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex A src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.bin D src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex A src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.bin D src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex A src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.bin D src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex A src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.bin D src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex A src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.bin D src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex A src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.bin D src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex A src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.bin D src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex A src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.bin D src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.bin D src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.bin D src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.bin D src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.bin D src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/samsung/lumpy/spd/lumpy.spd.bin D src/mainboard/samsung/lumpy/spd/lumpy.spd.hex A src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.bin D src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex M src/soc/amd/picasso/Makefile.inc A src/soc/intel/jasperlake/spd/lp4x-spd-1.bin D src/soc/intel/jasperlake/spd/lp4x-spd-1.hex A src/soc/intel/jasperlake/spd/lp4x-spd-2.bin D src/soc/intel/jasperlake/spd/lp4x-spd-2.hex A src/soc/intel/jasperlake/spd/lp4x-spd-3.bin D src/soc/intel/jasperlake/spd/lp4x-spd-3.hex A src/soc/intel/jasperlake/spd/lp4x-spd-4.bin D src/soc/intel/jasperlake/spd/lp4x-spd-4.hex A src/soc/intel/jasperlake/spd/lp4x-spd-5.bin D src/soc/intel/jasperlake/spd/lp4x-spd-5.hex A src/soc/intel/jasperlake/spd/lp4x-spd-6.bin D src/soc/intel/jasperlake/spd/lp4x-spd-6.hex A src/soc/intel/jasperlake/spd/lp4x-spd-7.bin D src/soc/intel/jasperlake/spd/lp4x-spd-7.hex M src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt A src/soc/intel/tigerlake/spd/ddr4-spd-1.bin D src/soc/intel/tigerlake/spd/ddr4-spd-1.hex A src/soc/intel/tigerlake/spd/ddr4-spd-2.bin D src/soc/intel/tigerlake/spd/ddr4-spd-2.hex A src/soc/intel/tigerlake/spd/ddr4-spd-3.bin D src/soc/intel/tigerlake/spd/ddr4-spd-3.hex A src/soc/intel/tigerlake/spd/ddr4-spd-4.bin D src/soc/intel/tigerlake/spd/ddr4-spd-4.hex A src/soc/intel/tigerlake/spd/ddr4-spd-5.bin D src/soc/intel/tigerlake/spd/ddr4-spd-5.hex A src/soc/intel/tigerlake/spd/ddr4-spd-6.bin D src/soc/intel/tigerlake/spd/ddr4-spd-6.hex A src/soc/intel/tigerlake/spd/ddr4-spd-7.bin D src/soc/intel/tigerlake/spd/ddr4-spd-7.hex A src/soc/intel/tigerlake/spd/ddr4-spd-8.bin D src/soc/intel/tigerlake/spd/ddr4-spd-8.hex A src/soc/intel/tigerlake/spd/ddr4-spd-empty.bin D src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt A src/soc/intel/tigerlake/spd/lp4x-spd-1.bin D src/soc/intel/tigerlake/spd/lp4x-spd-1.hex A src/soc/intel/tigerlake/spd/lp4x-spd-2.bin D src/soc/intel/tigerlake/spd/lp4x-spd-2.hex A src/soc/intel/tigerlake/spd/lp4x-spd-3.bin D src/soc/intel/tigerlake/spd/lp4x-spd-3.hex A src/soc/intel/tigerlake/spd/lp4x-spd-4.bin D src/soc/intel/tigerlake/spd/lp4x-spd-4.hex A src/soc/intel/tigerlake/spd/lp4x-spd-5.bin D src/soc/intel/tigerlake/spd/lp4x-spd-5.hex M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt 636 files changed, 182 insertions(+), 10,841 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44775/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/44775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 Gerrit-Change-Number: 44775 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Aaron Durbin, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45131 to look at the new patch set (#4). Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... lib/Makefile.inc: fail build when SPD would be empty Add a check to be sure that at least one SPD file will be added and fail the build when the resulting spd.bin would be empty. Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/lib/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45131/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Aaron Durbin, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45131 to look at the new patch set (#3). Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... lib/Makefile.inc: fail build when SPD would be empty Add a check to be sure that at least one SPD file will be added and fail the build when the resulting spd.bin would be empty. Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/lib/Makefile.inc 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45131/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in libgfxinit[master]: baytrail: Add PLL initialisation code
by Angel Pons (Code Review) 06 Sep '20

06 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44795 ) Change subject: baytrail: Add PLL initialisation code ...................................................................... baytrail: Add PLL initialisation code Change-Id: I3f59e1cd6623f6c65cd1f8e231ea1aa1ec41bd16 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/valleyview/Makefile.inc A common/valleyview/hw-gfx-gma-plls.adb A common/valleyview/hw-gfx-gma-plls.ads 3 files changed, 648 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/95/44795/1 diff --git a/common/valleyview/Makefile.inc b/common/valleyview/Makefile.inc index c587a3e..39241c2 100644 --- a/common/valleyview/Makefile.inc +++ b/common/valleyview/Makefile.inc @@ -7,8 +7,6 @@ gfxinit-y += ../g45/hw-gfx-gma-gmch-lvds.ads gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.adb gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.ads -gfxinit-y += ../g45/hw-gfx-gma-plls.adb -gfxinit-y += ../g45/hw-gfx-gma-plls.ads gfxinit-y += ../g45/hw-gfx-gma-port_detect.adb gfxinit-y += ../g45/hw-gfx-gma-gmch.ads gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.ads @@ -18,3 +16,5 @@ gfxinit-y += hw-gfx-gma-dpio.ads gfxinit-y += hw-gfx-gma-iosf.adb gfxinit-y += hw-gfx-gma-iosf.ads +gfxinit-y += hw-gfx-gma-plls.adb +gfxinit-y += hw-gfx-gma-plls.ads diff --git a/common/valleyview/hw-gfx-gma-plls.adb b/common/valleyview/hw-gfx-gma-plls.adb new file mode 100644 index 0000000..dd3fe41 --- /dev/null +++ b/common/valleyview/hw-gfx-gma-plls.adb @@ -0,0 +1,603 @@ +-- +-- Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.Time; +with HW.GFX.GMA.Config; +with HW.GFX.GMA.DPIO; +with HW.GFX.GMA.IOSF; +with HW.GFX.GMA.Registers; + +with HW.Debug; +with GNAT.Source_Info; + +package body HW.GFX.GMA.PLLs +with + Refined_State => (State => PLLs) +is + + Debug_Clocks : constant Boolean := False; + + type Count_Range is new Natural range 0 .. 2; + + type PLL_State is record + Use_Count : Count_Range; + Used_For_DP : Boolean; + Link_Rate : DP_Bandwidth; + Mode : Mode_Type; + end record; + + type PLL_State_Array is array (DPLLs) of PLL_State; + + PLLs : PLL_State_Array; + + ---------------------------------------------------------------------------- + + subtype N_Range is Int64 range 1 .. 8; + subtype M1_Range is Int64 range 2 .. 4; + subtype M2_Range is Int64 range 11 .. 157; + subtype P1_Range is Int64 range 2 .. 4; + subtype P2_Range is Int64 range 2 .. 21; + subtype VCO_Range is Int64 range 4_000_000_000 .. 6_000_000_001; + subtype Clock_Range is HW.GFX.Frequency_Type; + + type Clock_Type is + record + N : N_Range; + M1 : M1_Range; + M2 : M2_Range; + P1 : P1_Range; + P2 : P2_Range; + VCO : VCO_Range; + Reference_Clock : Clock_Range; + Dotclock : Clock_Range; + end record; + + Invalid_Clock : constant Clock_Type := Clock_Type' + (N => N_Range'Last, + M1 => M1_Range'Last, + M2 => M2_Range'Last, + P1 => P1_Range'Last, + P2 => P2_Range'Last, + Reference_Clock => Clock_Range'Last, + VCO => VCO_Range'Last, + Dotclock => Clock_Range'Last); + + type Limits_Type is + record + N_Lower : N_Range; + N_Upper : N_Range; + M1_Lower : M1_Range; + M1_Upper : M1_Range; + M2_Lower : M2_Range; + M2_Upper : M2_Range; + P1_Lower : P1_Range; + P1_Upper : P1_Range; + P2_Lower : P2_Range; + P2_Upper : P2_Range; + VCO_Lower : VCO_Range; + VCO_Upper : VCO_Range; + end record; + + Baytrail_Limits : constant Limits_Type := Limits_Type' + (N_Lower => 1, N_Upper => 7, + M1_Lower => 2, M1_Upper => 3, + M2_Lower => 11, M2_Upper => 156, + P1_Lower => 2, P1_Upper => 3, + P2_Lower => 2, P2_Upper => 20, + VCO_Lower => 4_000_000_000, VCO_Upper => 6_000_000_000); + + ---------------------------------------------------------------------------- + + -- intel_display.c: vlv_wait_port_ready() + procedure Wait_Port_Ready (Pipe : Pipe_Index) + is + Port_Mask : constant Word32 := + (case Pipe is + when Primary => 16#0f#, + when Secondary => 16#0f# * 2 ** 4, + when others => 16#0f#); -- FIXME + begin + Registers.Wait_Unset_Mask + (Register => Registers.GMCH_DPLL_A, + Mask => Port_Mask, + TOut_MS => 1000, + Verbose => True); + + end Wait_Port_Ready; + + ---------------------------------------------------------------------------- + + procedure Verify_Parameters + (N : in N_Range; + M1 : in M1_Range; + P1 : in P1_Range; + P2 : in P2_Range; + Target_Dotclock : in Clock_Range; + Reference_Clock : in Clock_Range; + Current_Limits : in Limits_Type; + Result : out Clock_Type; + Valid : out Boolean) + with + Global => null, + Pre => True, + Post => True + is + M2 : Int64; + M : Int64; + P : Int64; + VCO : Int64; + Dotclock : Int64; + begin + pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + P := P1 * P2; + M2 := (Target_Dotclock * P * N) / (Reference_Clock * M1); + M := M1 * M2; + + if P = 0 then + pragma Debug (Debug_Clocks, Debug.Put_Line ("P value is zero!")); + Result := Invalid_Clock; + Valid := False; + return; + end if; + + VCO := (Reference_Clock * M) / N; + Dotclock := VCO / P; + + pragma Debug (Debug_Clocks and not (Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper ), Debug.Put_Line ("P1 out of range.")); + pragma Debug (Debug_Clocks and not (Current_Limits.P2_Lower <= P2 and P2 <= Current_Limits.P2_Upper ), Debug.Put_Line ("P2 out of range.")); + pragma Debug (Debug_Clocks and not (Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper ), Debug.Put_Line ("M1 out of range.")); + pragma Debug (Debug_Clocks and not (Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper ), Debug.Put_Line ("M2 out of range.")); + pragma Debug (Debug_Clocks and not (Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper ), Debug.Put_Line ("N out of range.")); + pragma Debug (Debug_Clocks and not (Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper), Debug.Put_Line ("VCO out of range.")); + + pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Line ("Dotclock too low.")); + pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.Put_Int64 (Dotclock)); + pragma Debug (Debug_Clocks and not (Int64 (Clock_Range'First) <= Dotclock), Debug.New_Line); + + pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Line ("Dotclock too high.")); + pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.Put_Int64 (Dotclock)); + pragma Debug (Debug_Clocks and not (Dotclock <= Int64 (Clock_Range'Last)), Debug.New_Line); + + Valid := + Current_Limits.N_Lower <= N and N <= Current_Limits.N_Upper and + Current_Limits.P1_Lower <= P1 and P1 <= Current_Limits.P1_Upper and + -- Current_Limits.P2_Lower <= P2 and P2 <= Current_Limits.P2_Upper and + Current_Limits.M1_Lower <= M1 and M1 <= Current_Limits.M1_Upper and + Current_Limits.M2_Lower <= M2 and M2 <= Current_Limits.M2_Upper and + Current_Limits.VCO_Lower <= VCO and VCO <= Current_Limits.VCO_Upper and + Int64 (Clock_Range'First) <= Dotclock and + Dotclock <= Int64 (Clock_Range'Last); + + -- FIXME: intel_display.c: vlv_PLL_is_optimal() + + if Valid + then + Result := Clock_Type' + (N => N, + M1 => M1, + M2 => M2, + P1 => P1, + P2 => P2, + Reference_Clock => Reference_Clock, + VCO => VCO, + Dotclock => Clock_Range (Dotclock)); + else + Result := Invalid_Clock; + end if; + + end Verify_Parameters; + + procedure Calculate_Clock_Parameters + (Display : in Display_Type; + Target_Dotclock : in Clock_Range; + Reference_Clock : in Clock_Range; + Limits : in Limits_Type; + Best_Clock : out Clock_Type; + Valid : out Boolean) + with + Global => null, + Pre => True, + Post => True + is + Max_N : constant Int64 := Reference_Clock / 19200; + + P2_Flip_Flop : Boolean; + Best_Delta : Int64 := Int64'Last; + Current_Delta : Int64; + Current_Clock : Clock_Type; + Registers_Valid : Boolean; + begin + pragma Debug (Debug_Clocks, Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Valid := False; + Best_Clock := Invalid_Clock; + + -- Based on hardware requirement, prefer smaller n to precision + for N in N_Range range Limits.N_Lower .. Int64'Min (Limits.N_Upper, Max_N) + loop + -- Reverse loops as hardware prefers higher values + for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper + loop + P2_Flip_Flop := False; + for P2 in reverse P2_Range range Limits.P2_Lower .. Limits.P2_Upper + loop + -- Skip reserved values + P2_Flip_Flop := not P2_Flip_Flop; + if P2_Flip_Flop or else P2 <= 10 then + -- FIXME: Check if hardware prefers big or small M1, M2 values + for M1 in M1_Range range Limits.M1_Lower .. Limits.M1_Upper + loop + Verify_Parameters + (N => N, + M1 => M1, + P1 => P1, + P2 => P2, + Target_Dotclock => Target_Dotclock, + Reference_Clock => Reference_Clock, + Current_Limits => Limits, + Result => Current_Clock, + Valid => Registers_Valid); + + if Registers_Valid + then + if Current_Clock.Dotclock > Target_Dotclock + then + Current_Delta := Current_Clock.Dotclock - Target_Dotclock; + else + Current_Delta := Target_Dotclock - Current_Clock.Dotclock; + end if; + + if Current_Delta < Best_Delta + then + Best_Delta := Current_Delta; + Best_Clock := Current_Clock; + Valid := True; + end if; + + pragma Debug (Debug_Clocks, Debug.Put ("Current/Target/Best_Delta: ")); + pragma Debug (Debug_Clocks, Debug.Put_Int64 (Current_Clock.Dotclock)); + pragma Debug (Debug_Clocks, Debug.Put ("/")); + pragma Debug (Debug_Clocks, Debug.Put_Int64 (Target_Dotclock)); + pragma Debug (Debug_Clocks, Debug.Put ("/")); + pragma Debug (Debug_Clocks, Debug.Put_Int64 (Best_Delta)); + pragma Debug (Debug_Clocks, Debug.Put_Line (".")); + + end if; + end loop; + end if; + end loop; + end loop; + end loop; + + pragma Debug (Valid, Debug.Put_Line ("Valid clock found.")); + pragma Debug (Valid, Debug.Put ("Best/Target/Delta: ")); + pragma Debug (Valid, Debug.Put_Int64 (Best_Clock.Dotclock)); + pragma Debug (Valid, Debug.Put ("/")); + pragma Debug (Valid, Debug.Put_Int64 (Target_Dotclock)); + pragma Debug (Valid, Debug.Put ("/")); + pragma Debug (Valid, Debug.Put_Int64 (Best_Delta)); + pragma Debug (Valid, Debug.Put_Line (".")); + pragma Debug (not Valid, Debug.Put_Line ("No valid clock found.")); + + end Calculate_Clock_Parameters; + + type Regs is array (DPLLs) of Registers.Registers_Index; + + DPLL_CTRL : constant Regs := (Registers.GMCH_DPLL_A, Registers.GMCH_DPLL_B); + PP_CONTROL : constant Regs := + (Registers.GMCH_PP_CONTROL, + Registers.VLV_PIPE_B_PP_CONTROL); + + -- On VLV the Panel Protection also locks DPLL registers, unlock them just in case. + procedure Unlock_DPLL_Regs (PLL : in DPLLs) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Registers.Unset_And_Set_Mask + (Register => PP_CONTROL (PLL), + Mask_Unset => 16#ffff# * 2 ** 16, + Mask_Set => 16#abcd# * 2 ** 16); + end Unlock_DPLL_Regs; + + VLV_DPLL_VCO_ENABLE : constant := 1 * 2 ** 31; + VLV_DPLL_CLOCK_DRIVE_EN : constant := 1 * 2 ** 30; + VLV_DPLL_REF_CLOCK_EN : constant := 1 * 2 ** 29; + VLV_DPLL_VGA_MODE_DIS : constant := 1 * 2 ** 28; + VLV_DPLL_A_SINGLE_FREQ : constant := 1 * 2 ** 26; + VLV_DPLL_UNLOCK : constant := 0 * 2 ** 15; + VLV_DPLL_LOCK : constant := 1 * 2 ** 15; + VLV_DPLL_DISP_RATE_SW : constant := 1 * 2 ** 8; + + -- DPLL A only + VLV_DPLL_P2_10_OR_14 : constant := 0 * 2 ** 24; -- Dot clock <= 270 MHz + VLV_DPLL_P2_5_OR_7 : constant := 1 * 2 ** 24; -- Dot clock > 270 MHz + VLV_DPLL_VCC_LDO : constant := 1 * 2 ** 14; -- Note: For TNG use + VLV_REFCLK_EXT_PAD : constant := 0 * 2 ** 13; -- External refclk pad, 27 MHz + VLV_REFCLK_INT_CORE : constant := 1 * 2 ** 13; -- Integrated core refclk, default 100 MHz + + -- DPLL B only + VLV_CRICLK_EXT_PAD : constant := 0 * 2 ** 14; -- External refclk pad + VLV_CRICLK_INT_CORE : constant := 1 * 2 ** 14; -- Integrated core refclk + + -- + -- Post divider depends on pixel clock rate, DAC vs digital + -- (and LVDS, but we don't support that). + -- + -- Note: don't use the DAC post divider as it seems unstable. + -- + function Make_Mdiv (N, M1, M2, P1, P2, K, PD : in Word32) return Word32 is + ((PD * 2 ** 28) or -- Post divider + (K * 2 ** 24) or + (P1 * 2 ** 21) or + (P2 * 2 ** 16) or + (N * 2 ** 12) or + (M1 * 2 ** 8) or + (M2 and 16#ff#)) with Inline; + + PLL_To_Channel : constant array (DPLLs) of DPIO.Channel := (DPIO.DPIO_CH0, DPIO.DPIO_CH1); + + PLL_Names : constant array (DPLLs) of String (1 .. 8) := + (DPLL_A => "DPLL A ", + DPLL_B => "DPLL B "); + + -- intel_display.c: vlv_prepare_pll() + procedure Program_DPLL + (PLL : DPLLs; + Display : Display_Type; + Clk : Clock_Type) + with + Global => (In_Out => Registers.Register_State), + Pre => True, + Post => True + is + Mdiv : Word32; + begin + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug.Put_Line (": " & PLL_Names (PLL))); + + Mdiv := Make_Mdiv + (N => Word32 (Clk.N), + M1 => Word32 (Clk.M1), + M2 => Word32 (Clk.M2), + P1 => Word32 (Clk.P1), + P2 => Word32 (Clk.P2), + K => 1, + PD => 1); + + DPIO.Vlv_Pll_Prepare (PLL_To_Channel (PLL), Mdiv, Display); + + end Program_DPLL; + + function Get_Max_Clock (Limits : in Limits_Type) return Int64 is + (Limits.VCO_Upper / Limits.P1_Lower / Limits.P2_Lower / 5); + + procedure On + (PLL : in T; + Port_Cfg : in Port_Config; + Success : out Boolean) + is + Limits : constant Limits_Type := Baytrail_Limits; + Max_Clock : constant Int64 := Get_Max_Clock (Limits); + Target_Clock : constant Frequency_Type := + (if Port_Cfg.Display = DP then + DP_Symbol_Rate (Port_Cfg.DP.Bandwidth) + else + Port_Cfg.Mode.Dotclock); + Clk : Clock_Type; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Success := PLL in DPLLs; + Clk := Invalid_Clock; + + if Success then + -- Unlock DPLL regs + Unlock_DPLL_Regs (PLL); + + if Port_Cfg.Display = DP then + -- we use static values for DP + case Port_Cfg.DP.Bandwidth is + when DP_Bandwidth_1_62 => + Clk.N := 5; + Clk.M1 := 3; + Clk.M2 := 81; + Clk.P1 := 3; + Clk.P2 := 2; + when DP_Bandwidth_2_7 => + Clk.N := 1; + Clk.M1 := 2; + Clk.M2 := 27; + Clk.P1 := 2; + Clk.P2 := 2; + when others => + Success := False; + end case; + elsif Target_Clock <= Max_Clock then + Calculate_Clock_Parameters + (Display => Port_Cfg.Display, + Target_Dotclock => Target_Clock * 5, + Reference_Clock => 100_000_000, + Limits => Limits, + Best_Clock => Clk, + Valid => Success); + else + Success := False; + pragma Debug (Debug.Put ("WARNING: Targeted clock too high: ")); + pragma Debug (Debug.Put_Int64 (Target_Clock)); + pragma Debug (Debug.Put (" > ")); + pragma Debug (Debug.Put_Int64 (Max_Clock)); + pragma Debug (Debug.New_Line); + pragma Debug (Debug.New_Line); + end if; + end if; + + if Success then + Program_DPLL (PLL, Port_Cfg.Display, Clk); + + Registers.Set_Mask (DPLL_CTRL (PLL), VLV_DPLL_VCO_ENABLE or VLV_DPLL_CLOCK_DRIVE_EN); + Registers.Posting_Read (DPLL_CTRL (PLL)); + Time.U_Delay (150); + + DPIO.Vlv_Phy_Pre_Encoder_Enable (PLL_To_Channel (PLL)); + end if; + end On; + + -- intel_display.c: vlv_disable_pll() + procedure Off (PLL : T) + is + Value : Word32 := VLV_REFCLK_INT_CORE or + VLV_DPLL_REF_CLOCK_EN or + VLV_DPLL_VGA_MODE_DIS; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + if PLL in DPLLs then + if PLL /= DPLL_A then + Value := Value or VLV_CRICLK_INT_CORE; + end if; + Registers.Write (DPLL_CTRL (PLL), Value); + Registers.Posting_Read (DPLL_CTRL (PLL)); + end if; + end Off; + + ---------------------------------------------------------------------------- + + procedure Initialize + is + begin + PLLs := + (DPLLs => + (Use_Count => 0, + Used_For_DP => False, + Link_Rate => DP_Bandwidth'First, + Mode => Invalid_Mode)); + + -- Enable Refclk, this needs to be done early + Registers.Write + (Register => Registers.GMCH_DPLL_A, + Value => VLV_DPLL_VGA_MODE_DIS or + VLV_DPLL_REF_CLOCK_EN or + VLV_REFCLK_INT_CORE); + Registers.Write + (Register => Registers.GMCH_DPLL_B, + Value => VLV_DPLL_VGA_MODE_DIS or + VLV_DPLL_REF_CLOCK_EN or + VLV_CRICLK_INT_CORE or + VLV_REFCLK_INT_CORE); + end Initialize; + + procedure Alloc_Configurable + (Port_Cfg : in Port_Config; + PLL : out T; + Success : out Boolean) + with + Pre => True + is + function Config_Matches (PE : PLL_State) return Boolean + is + begin + return + PE.Used_For_DP = (Port_Cfg.Display = DP) and + ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or + (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode)); + end Config_Matches; + begin + -- try to find shareable PLL + -- FIXME: Sharing PLLs in VLV requires some special DPIO settings + for P in DPLLs loop + Success := PLLs (P).Use_Count /= 0 and + PLLs (P).Use_Count /= Count_Range'Last and + Config_Matches (PLLs (P)); + if Success then + PLL := P; + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug.Put_Line (": Will share " & PLL_Names (PLL))); + PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1; + return; + end if; + end loop; + + -- try to find free PLL + for P in DPLLs loop + if PLLs (P).Use_Count = 0 then + PLL := P; + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug.Put_Line (": Will power on " & PLL_Names (PLL))); + On (PLL, Port_Cfg, Success); + if Success then + PLLs (PLL) := + (Use_Count => 1, + Used_For_DP => Port_Cfg.Display = DP, + Link_Rate => Port_Cfg.DP.Bandwidth, + Mode => Port_Cfg.Mode); + end if; + return; + end if; + end loop; + + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug.Put_Line (": Could not allocate PLL!")); + PLL := Invalid; + end Alloc_Configurable; + + procedure Alloc + (Port_Cfg : in Port_Config; + PLL : out T; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + if Port_Cfg.Port in DIGI_B .. DIGI_D then + Alloc_Configurable (Port_Cfg, PLL, Success); + else + PLL := Invalid; + Success := False; + end if; + end Alloc; + + procedure Free (PLL : T) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + if PLL in DPLLs then + if PLLs (PLL).Use_Count /= 0 then + PLLs (PLL).Use_Count := PLLs (PLL).Use_Count - 1; + if PLLs (PLL).Use_Count = 0 then + Off (PLL); + end if; + end if; + end if; + end Free; + + procedure All_Off + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + for PLL in DPLLs loop + Off (PLL); + end loop; + end All_Off; + + function Register_Value (PLL : T) return Word32 + is + begin + return (if PLL = DPLL_B then 1 else 0); + end Register_Value; + +end HW.GFX.GMA.PLLs; diff --git a/common/valleyview/hw-gfx-gma-plls.ads b/common/valleyview/hw-gfx-gma-plls.ads new file mode 100644 index 0000000..917fa39 --- /dev/null +++ b/common/valleyview/hw-gfx-gma-plls.ads @@ -0,0 +1,43 @@ +-- +-- Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +private package HW.GFX.GMA.PLLs +with + Abstract_State => (State with Part_Of => GMA.State) +is + + -- XXX: Types should be private (but that triggers a bug in SPARK GPL 2016) + type T is (Invalid_PLL, DPLL_A, DPLL_B); + subtype DPLLs is T range DPLL_A .. DPLL_B; + Invalid : constant T := Invalid_PLL; + + -- intel_display.c: vlv_wait_port_ready() + procedure Wait_Port_Ready (Pipe : Pipe_Index); + + procedure Initialize + with + Global => (Output => State); + + procedure Alloc + (Port_Cfg : in Port_Config; + PLL : out T; + Success : out Boolean); + + procedure Free (PLL : T); + + procedure All_Off; + + function Register_Value (PLL : T) return Word32; + +end HW.GFX.GMA.PLLs; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3f59e1cd6623f6c65cd1f8e231ea1aa1ec41bd16 Gerrit-Change-Number: 44795 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: mb/system76/lemp9: enable I2C HID touchpad
by Jeremy Soller (Code Review) 06 Sep '20

06 Sep '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43623 ) Change subject: mb/system76/lemp9: enable I2C HID touchpad ...................................................................... mb/system76/lemp9: enable I2C HID touchpad Tested on lemp9, touchpad confirmed to use I2C HID Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: Ic3a90fda134b1d53f28ab687b3033ec52fee843b --- M src/mainboard/system76/lemp9/Kconfig M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/lemp9/gpio.h 3 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/43623/1 diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index dd5359e..c606d91 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID select EC_SYSTEM76_EC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 25ae62f..27f5efb 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -2,6 +2,11 @@ # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, }" # Send an extra VR mailbox command for the PS4 exit issue @@ -35,6 +40,22 @@ #register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + # SATA register "SataMode" = "Sata_AHCI" register "SataSalpSupport" = "0" @@ -194,7 +215,16 @@ device pci 14.3 on end # CNVi wifi #end device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C #0 + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index d06145d..e71197c 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -139,8 +139,8 @@ PAD_CFG_NC(GPP_B2), // CPU Misc - // GPP_B3 - _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000), + // GPP_B3 (touchpad interrupt) + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // NC PAD_CFG_NC(GPP_B4), -- To view, visit https://review.coreboot.org/c/coreboot/+/43623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a90fda134b1d53f28ab687b3033ec52fee843b Gerrit-Change-Number: 43623 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

4 38

Change in coreboot[master]: mb/system76/lemp9: move HDA options into devicetree
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45132 ) Change subject: mb/system76/lemp9: move HDA options into devicetree ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Gerrit-Change-Number: 45132 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Sep 2020 16:29:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: disable PCH DMIC, which is not wired
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45133 ) Change subject: mb/system76/lemp9: disable PCH DMIC, which is not wired ...................................................................... Patch Set 1: (1 comment) This change is ready for review. https://review.coreboot.org/c/coreboot/+/45133/1/src/mainboard/system76/lem… File src/mainboard/system76/lemp9/devicetree.cb: https://review.coreboot.org/c/coreboot/+/45133/1/src/mainboard/system76/lem… PS1, Line 204: register "PchHdaDspEnable" = "0" : register "PchHdaAudioLinkHda" = "1" : register "PchHdaAudioLinkDmic0" = "0" : register "PchHdaAudioLinkDmic1" = "0" : register "PchHdaAudioLinkSsp0" = "0" : register "PchHdaAudioLinkSsp1" = "0" : register "PchHdaAudioLinkSsp2" = "0" : register "PchHdaAudioLinkSndw1" = "0" : register "PchHdaAudioLinkSndw2" = "0" : register "PchHdaAudioLinkSndw3" = "0" : register "PchHdaAudioLinkSndw4" = "0" : I will drop disabled settings later in a global patch -- To view, visit https://review.coreboot.org/c/coreboot/+/45133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f Gerrit-Change-Number: 45133 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Sep 2020 16:28:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb: remove duplicated Make code for spd.bin generation
by 9elements QA (Code Review) 06 Sep '20

06 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44774 ) Change subject: mb: remove duplicated Make code for spd.bin generation ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17896 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17895 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/17894 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17893 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/17892 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/17899 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17898 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17897 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/44774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Gerrit-Change-Number: 44774 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Sep 2020 16:27:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2020