coreboot-gerrit September 2020

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Change in coreboot[master]: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY
by Felix Singer (Code Review) 06 Sep '20

06 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45125 ) Change subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Gerrit-Change-Number: 45125 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Sep 2020 14:33:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: enable eDP in Fsp
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45126 ) Change subject: mb/system76/lemp9: enable eDP in Fsp ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Gerrit-Change-Number: 45126 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Sep 2020 14:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45112 ) Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 50 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 615a94f..63a85c2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -262,15 +262,6 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { - params->Usb2OverCurrentPin[i] = 0; - } - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { - params->Usb3OverCurrentPin[i] = 0; - } - mainboard_silicon_init_params(params); const struct soc_power_limits_config *soc_config; @@ -379,12 +370,16 @@ /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } if (config->PchUsb2PhySusPgDisable) @@ -392,7 +387,11 @@ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 0130d2c..8e33174 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -64,13 +64,6 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) - params->Usb2OverCurrentPin[i] = 0; - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) - params->Usb3OverCurrentPin[i] = 0; - /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); @@ -135,8 +128,6 @@ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = @@ -145,11 +136,20 @@ config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 40be0d4..b787192 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -253,19 +253,25 @@ /* USB configuration */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index e96d624..a0bcac7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -139,8 +139,6 @@ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = @@ -149,11 +147,20 @@ config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1601c2c..73a620d 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -148,16 +148,24 @@ /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45125 ) Change subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/halvor/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/google/volte… PS1, Line 17: > Remove this empty line here. Done https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/prodrive/her… File src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/prodrive/her… PS1, Line 121: # unused > Drop this. Done https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… File src/mainboard/supermicro/x11-lga1151-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… PS1, Line 42: # USB : register "usb2_ports" = "{ > Drop this. Done https://review.coreboot.org/c/coreboot/+/45125/1/src/mainboard/supermicro/x… PS1, Line 59: register "usb3_ports" = "{ > Drop this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Gerrit-Change-Number: 45125 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Sep 2020 14:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Michał Żygowski, Frans Hendriks, Paul Menzel, Angel Pons, Wim Vervoorn, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45125 to look at the new patch set (#2). Change subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY ...................................................................... mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/madoo/overridetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/duffy/overridetree.cb M src/mainboard/google/hatch/variants/faffy/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/noibat/overridetree.cb M src/mainboard/google/hatch/variants/puff/overridetree.cb M src/mainboard/google/hatch/variants/stryke/overridetree.cb M src/mainboard/google/hatch/variants/wyvern/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 43 files changed, 0 insertions(+), 211 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45125/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Gerrit-Change-Number: 45125 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
by Michael Niewöhner (Code Review) 06 Sep '20

06 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Christian Walter, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45112 to look at the new patch set (#6). Change subject: soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default ...................................................................... soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 50 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45112/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Gerrit-Change-Number: 45112 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NOT FOR MERGE] mb/clevo/n130wu: Make master working
by Felix Singer (Code Review) 06 Sep '20

06 Sep '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45129 ) Change subject: [NOT FOR MERGE] mb/clevo/n130wu: Make master working ...................................................................... [NOT FOR MERGE] mb/clevo/n130wu: Make master working Change-Id: I30b4af7430c4b80d03e9601ef9d81d1624f0be87 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Makefile.inc M src/mainboard/clevo/kbl-u/dsdt.asl M src/mainboard/clevo/kbl-u/romstage.c M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 5 files changed, 20 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45129/1 diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index b0e5353..62b0bf8 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -4,20 +4,16 @@ def_bool y select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 - select USE_BLOBS - select ADD_FSP_BINARIES - select FSP_USE_REPO - select EC_ACPI +# select EC_ACPI select INTEL_GMA_HAVE_VBT select SOC_INTEL_KABYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 - select HAVE_ACPI_RESUME +# select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES # select HAVE_CMOS_DEFAULT - select HAVE_SMI_HANDLER +# select HAVE_SMI_HANDLER config MAINBOARD_DIR string diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc index 50578c2..aa8029d 100644 --- a/src/mainboard/clevo/kbl-u/Makefile.inc +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -1,3 +1 @@ -romstage-y += pei_data.c - -ramstage-y += ramstage.c pei_data.c hda_verb.c +ramstage-y += ramstage.c hda_verb.c diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl index 5eb6b04..12c8938 100644 --- a/src/mainboard/clevo/kbl-u/dsdt.asl +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -16,7 +16,7 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> +#include <acpi/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -26,23 +26,4 @@ 0x20110725 // OEM revision ) { - #include "acpi/platform.asl" - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - - } - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> } diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c index 101095c..b127a3e 100644 --- a/src/mainboard/clevo/kbl-u/romstage.c +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -24,6 +24,21 @@ #include <arch/io.h> #include "pei_data.h" +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; @@ -37,8 +52,6 @@ dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 1a552d4..feec0b8 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -29,8 +29,6 @@ # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" @@ -39,21 +37,12 @@ register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "1" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -61,15 +50,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Root port #1 x4 (TBT) register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -125,8 +105,6 @@ register "SendVrMbxCmd" = "2" - # PL2 override 44W - register "tdp_pl2_override" = "40" # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/45129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30b4af7430c4b80d03e9601ef9d81d1624f0be87 Gerrit-Change-Number: 45129 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [NOT FOR MERGE] mb/clevo/n130wu
by Felix Singer (Code Review) 06 Sep '20

06 Sep '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45128 ) Change subject: [NOT FOR MERGE] mb/clevo/n130wu ...................................................................... [NOT FOR MERGE] mb/clevo/n130wu clevo/kbl-u/n130wu: Patch set 89 Change-Id: I1be54caf3ad06038aa808f63fb350ab46b9020ca Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A Documentation/mainboard/clevo/index.md A Documentation/mainboard/clevo/n130wu/index.md A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg M Documentation/mainboard/index.md A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/kbl-u/Kconfig A src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/Makefile.inc A src/mainboard/clevo/kbl-u/acpi/ec.asl A src/mainboard/clevo/kbl-u/acpi/superio.asl A src/mainboard/clevo/kbl-u/acpi_tables.c A src/mainboard/clevo/kbl-u/board_info.txt A src/mainboard/clevo/kbl-u/dsdt.asl A src/mainboard/clevo/kbl-u/gpio.h A src/mainboard/clevo/kbl-u/hda_verb.c A src/mainboard/clevo/kbl-u/pei_data.c A src/mainboard/clevo/kbl-u/pei_data.h A src/mainboard/clevo/kbl-u/ramstage.c A src/mainboard/clevo/kbl-u/romstage.c A src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt A src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 22 files changed, 1,281 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45128/1 diff --git a/Documentation/mainboard/clevo/index.md b/Documentation/mainboard/clevo/index.md new file mode 100644 index 0000000..4b23bcc --- /dev/null +++ b/Documentation/mainboard/clevo/index.md @@ -0,0 +1,4 @@ +# Clevo mainboards + +## Kaby Lake-R +- [N130WU](n130wu/index.md) diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md new file mode 100644 index 0000000..11eca6c --- /dev/null +++ b/Documentation/mainboard/clevo/n130wu/index.md @@ -0,0 +1,52 @@ +# Clevo N130WU + +## Overview + +![][overview] + +[overview]: n130wu_overview.jpg + +### Technology +```eval_rst ++------------------+--------------------------------+ +| CPU | Intel i7-8550U | ++------------------+--------------------------------+ +| PCH | Intel Sunrise Point LP | ++------------------+--------------------------------+ +| EC / Super IO | ITE 8587 | ++------------------+--------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------+ +``` + +### Flash chip +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Model | GD25Q64B | ++---------------------+-----------------+ +| Socketed flash | no | ++---------------------+-----------------+ +| Size | 8 MiB | ++---------------------+-----------------+ +| In circuit flashing | Yes | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Write protection | No | ++---------------------+-----------------+ +| Dual BIOS feature | No | ++---------------------+-----------------+ +| Internal flashing | Yes | ++---------------------+-----------------+ +``` + +## Board status +### Working +### Not Working +### Work in progress +### Untested + +## Also known as +* TUXEDO InfinityBook Pro 13 v3 diff --git a/Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg b/Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg new file mode 100644 index 0000000..dca7bb6 --- /dev/null +++ b/Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0eefee8..d161c22 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,9 +26,9 @@ - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) -## Dell +## Clevo -- [OptiPlex 9010 SFF](dell/optiplex_9010.md) +- [Mainboards](clevo/index.md) ## Emulation diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig new file mode 100644 index 0000000..9aacf38 --- /dev/null +++ b/src/mainboard/clevo/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_CLEVO + +choice + prompt "Mainboard model" + +source "src/mainboard/clevo/*/Kconfig.name" + +endchoice + +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Clevo" + +endif diff --git a/src/mainboard/clevo/Kconfig.name b/src/mainboard/clevo/Kconfig.name new file mode 100644 index 0000000..730b6bc --- /dev/null +++ b/src/mainboard/clevo/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CLEVO + bool "Clevo" diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig new file mode 100644 index 0000000..b0e5353 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -0,0 +1,95 @@ +if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select EC_ACPI + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_KABYLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT + select HAVE_SMI_HANDLER + +config MAINBOARD_DIR + string + default clevo/kbl-u + +config VARIANT_DIR + string + default "n13xwu" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config MAINBOARD_PART_NUMBER + string + default "N130WU" if BOARD_CLEVO_N130WU + default "N131WU" if BOARD_CLEVO_N131WU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + hex + default 0x600000 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,5917.rom" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config VGA_BIOS_ID + string + default "8086,5917" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + +config PXE_ROM_ID + string + default "10ec,8168" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name new file mode 100644 index 0000000..f252f0b --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_CLEVO_N130WU + bool "N130WU" + +config BOARD_CLEVO_N131WU + bool "N131WU" diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc new file mode 100644 index 0000000..50578c2 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += pei_data.c + +ramstage-y += ramstage.c pei_data.c hda_verb.c diff --git a/src/mainboard/clevo/kbl-u/acpi/ec.asl b/src/mainboard/clevo/kbl-u/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/ec.asl diff --git a/src/mainboard/clevo/kbl-u/acpi/superio.asl b/src/mainboard/clevo/kbl-u/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/superio.asl diff --git a/src/mainboard/clevo/kbl-u/acpi_tables.c b/src/mainboard/clevo/kbl-u/acpi_tables.c new file mode 100644 index 0000000..c48f828 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/clevo/kbl-u/board_info.txt b/src/mainboard/clevo/kbl-u/board_info.txt new file mode 100644 index 0000000..579a840 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Clevo +Board name: N130WU +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl new file mode 100644 index 0000000..5eb6b04 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT Revision 2 for 64bit + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/clevo/kbl-u/gpio.h b/src/mainboard/clevo/kbl-u/gpio.h new file mode 100644 index 0000000..cc856fd --- /dev/null +++ b/src/mainboard/clevo/kbl-u/gpio.h @@ -0,0 +1,532 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + // RCIN# + _PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0), + + // LAD0 + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0), + + // LAD1 + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0), + + // LAD2 + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0), + + // LAD3 + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0), + + // LFRAME# + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + + // SERIRQ + _PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0), + + // PIRQA# + _PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0), + + // CLKRUN# + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + + // CLKOUT_LPC0 + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + + // CLKOUT_LPC1 + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + + // PME# + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + + // BM_BUSY# + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + + // SUSWARN#/SUSPWRDNACK + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + + // SUS_STAT#/ESPI_RESET# + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + + // SUS_ACK# + _PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0), + + // SD_1P8_SEL + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + + // SD_PWR_EN# + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + + // ISH_GP0 + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + + // ISH_GP1 + _PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0), + + // ISH_GP2 + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + + // ISH_GP3 + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + + // ISH_GP4 + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + + // ISH_GP5 + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + + // CORE_VID0 + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + + // CORE_VID1 + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + + // VRALERT# + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + + // CPU_GP2 + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + + // CPU_GP3 + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + + // SRCCLKREQ0# + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + + // SRCCLKREQ1# + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + + // SRCCLKREQ2# + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + + // SRCCLKREQ3# + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + + // SRCCLKREQ4# + _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + + // SRCCLKREQ5# + _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + + // EXT_PWR_GATE# + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + + // SLP_S0# + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + + // PLTRST# + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + + // SPKR + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + + // GSPI0_CS# + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + + // GSPI0_CLK + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + + // GSPI0_MISO + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + + // GSPI0_MOSI + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + + // GSPI1_CS# + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + + // GSPI1_CLK + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + + // GSPI1_MISO + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + + // GSPI1_MOSI + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + + // SML1ALERT#/PCHHOT# + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + + // SMBCLK + _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), + + // SMBDATA + _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), + + // SMBALERT# + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + + // SML0CLK + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + + // SML0DATA + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + + // SML0ALERT# + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + + // SML1CLK + _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), + + // SML1DATA + _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), + + // UART0_RXD + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + + // UART0_TXD + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + + // UART0_RTS# + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + + // UART0_CTS# + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + + // UART1_RXD + _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), + + // UART1_TXD + _PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0), + + // UART1_RTS# + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + + // UART1_CTS# + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + + // I2C0_SDA + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + + // I2C0_SCL + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + + // I2C1_SDA + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + + // I2C1_SCL + _PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0), + + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + + // UART2_RTS# + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + + // UART2_CTS# + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + + // SPI1_CS# + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + + // SPI1_CLK + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + + // SPI1_MISO + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + + // SPI1_MOSI + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + + // FLASHTRIG + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + + // ISH_I2C0_SDA + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + + // ISH_I2C0_SCL + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + + // ISH_I2C1_SDA + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + + // ISH_I2C1_SCL + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + + // ISH_UART0_RXD + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + + // ISH_UART0_TXD + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + + // ISH_UART0_RTS# + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + + // ISH_UART0_CTS# + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + + // DMIC_CLK1 + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + + // DMIC_DATA1 + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + + // DMIC_CLK0 + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + + // DMIC_DATA0 + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + + // SPI1_IO2 + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0), + + // SPI1_IO3 + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + + // I2S_MCLK + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + + // SATAXPCIE0/SATAGP0 + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + + // SATAXPCIE1/SATAGP1 + _PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0), + + // SATAXPCIE2/SATAGP2 + _PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0), + + // CPU_GP0 + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + + // DEVSLP0 + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + + // DEVSLP1 + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + + // DEVSLP2 + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + + // CPU_GP1 + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + + // SATALED# + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + + // USB2_OC0# + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + + // USB2_OC1# + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + + // USB2_OC2# + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + + // USB2_OC3# + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + + // DDPB_HPD0 + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + + // DDPC_HPD1 + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + + // DDPD_HPD2 + _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), + + // DDPE_HPD3 + _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), + + // EDP_HPD + _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + + // DDPB_CTRLCLK + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + + // DDPB_CTRLDATA + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + + // DDPC_CTRLCLK + _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), + + // DDPC_CTRLDATA + _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), + + // DDPD_CTRLCLK + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + + // DDPD_CTRLDATA + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + + // BATLOW# + _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + + // LAN_WAKE# + _PAD_CFG_STRUCT(GPD2, 0x880502, 0x0), + + // PWRBTN# + _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + + // SLP_S3# + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + + // SLP_S4# + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + + // SLP_A# + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + + // RSVD + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + + // SUSCLK + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + + // SLP_WLAN# + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + + // SLP_S5# + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + + // I2S2_SCLK + _PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0), + + // I2S2_SFRM + _PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0), + + // I2S2_TXD + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + + // I2S2_RXD + _PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0), + + // I2C2_SDA + _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + + // I2C2_SCL + _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + + // I2C3_SDA + _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), + + // I2C3_SCL + _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), + + // I2C4_SDA + _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), + + // I2C4_SCL + _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), + + // I2C5_SDA/ISH_I2C2_SDA + _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), + + // I2C5_SCL/ISH_I2C2_SCL + _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), + + // EMMC_CMD + _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + + // EMMC_DATA0 + _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + + // EMMC_DATA1 + _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + + // EMMC_DATA2 + _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + + // EMMC_DATA3 + _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + + // EMMC_DATA4 + _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + + // EMMC_DATA5 + _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + + // EMMC_DATA6 + _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + + // EMMC_DATA7 + _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + + // EMMC_RCLK + _PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0), + + // EMMC_CLK + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + + // SD_CMD + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + + // SD_DATA0 + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0), + + // SD_DATA1 + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + + // SD_DATA2 + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + + // SD_DATA3 + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + + // SD_CD# + _PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), + + // SD_CLK + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + + // SD_WP + _PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0) +}; + + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0) +}; + +#endif + +#endif diff --git a/src/mainboard/clevo/kbl-u/hda_verb.c b/src/mainboard/clevo/kbl-u/hda_verb.c new file mode 100644 index 0000000..386b6f5 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x15581314, /* Subsystem ID */ + 0x0000000b, /* Number of jacks (NID entries) */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x15581314), + + /* Pin Widget Verb Table */ + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170120), + + /* Pin Complex (NID 0x15) */ + AZALIA_PIN_CFG(0x0, 0x15, 0x02211010), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x02a11030), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1a) */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* Pin Complex (NID 0x1b) */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* Pin Complex (NID 0x1d) */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f4a205), + + /* Pin Complex (NID 0x1e) */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + + /* coreboot specific header */ + 0x8086280b, /* Codec Vendor / Device ID: Kabylake HDMI */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of jacks (NID entries) */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x2, 0x5, 0x18560010), + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x2, 0x6, 0x18560010), + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x2, 0x7, 0x18560010)}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/clevo/kbl-u/pei_data.c b/src/mainboard/clevo/kbl-u/pei_data.c new file mode 100644 index 0000000..7688e64 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/pei_data.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} + }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + {0, 1, 3, 2, 4, 5, 6, 7}, + {1, 0, 4, 5, 2, 3, 6, 7} + }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/clevo/kbl-u/pei_data.h b/src/mainboard/clevo/kbl-u/pei_data.h new file mode 100644 index 0000000..a1a5c97 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/pei_data.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c new file mode 100644 index 0000000..219fa8f --- /dev/null +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c new file mode 100644 index 0000000..101095c --- /dev/null +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <arch/io.h> +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt new file mode 100644 index 0000000..c6667ab --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb new file mode 100644 index 0000000..1a552d4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -0,0 +1,250 @@ +chip soc/intel/skylake + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_E" + register "gpe0_dw1" = "GPP_A" + register "gpe0_dw2" = "GPP_C" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Root port #1 x4 (TBT) + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + + # Root port #5 x1 (LAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port #6 x1 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + + # Root port #9 x4 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + + # PL2 override 44W + register "tdp_pl2_override" = "40" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/45128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be54caf3ad06038aa808f63fb350ab46b9020ca Gerrit-Change-Number: 45128 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

1 0

Change in libgfxinit[master]: gma baytrail: Add connectors support
by Nico Huber (Code Review) 06 Sep '20

06 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/42359 ) Change subject: gma baytrail: Add connectors support ...................................................................... Patch Set 53: (1 comment) https://review.coreboot.org/c/libgfxinit/+/42359/50/common/valleyview/hw-gf… File common/valleyview/hw-gfx-gma-connectors.adb: https://review.coreboot.org/c/libgfxinit/+/42359/50/common/valleyview/hw-gf… PS50, Line 98: end Post_On; > I'm still not sure if I should change this. For DVI and HDMI, Wait_Port_Ready works as intended. It's also what the PRM suggests. And it's definitely something to try if DP isn't working. Generally, if there is something that might work either way, it's better to do it the way that seems more likely to be the correct one. If you have to change it later because of a corner case that doesn't work, all the testing until then was for naught. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Gerrit-Change-Number: 42359 Gerrit-PatchSet: 53 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Name of user not set #1002789 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Sep 2020 11:41:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: baytrail: Add power and clocks support
by Angel Pons (Code Review) 06 Sep '20

06 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44796 ) Change subject: baytrail: Add power and clocks support ...................................................................... baytrail: Add power and clocks support Change-Id: I1e359882b78ed7436ec90f2ac8c4276f70eca1b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/valleyview/Makefile.inc A common/valleyview/hw-gfx-gma-power_and_clocks.adb A common/valleyview/hw-gfx-gma-power_and_clocks.ads 3 files changed, 189 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/96/44796/1 diff --git a/common/valleyview/Makefile.inc b/common/valleyview/Makefile.inc index 39241c2..12d31d1 100644 --- a/common/valleyview/Makefile.inc +++ b/common/valleyview/Makefile.inc @@ -9,8 +9,6 @@ gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.ads gfxinit-y += ../g45/hw-gfx-gma-port_detect.adb gfxinit-y += ../g45/hw-gfx-gma-gmch.ads -gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.ads -gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.adb gfxinit-y += hw-gfx-gma-dpio.adb gfxinit-y += hw-gfx-gma-dpio.ads @@ -18,3 +16,5 @@ gfxinit-y += hw-gfx-gma-iosf.ads gfxinit-y += hw-gfx-gma-plls.adb gfxinit-y += hw-gfx-gma-plls.ads +gfxinit-y += hw-gfx-gma-power_and_clocks.ads +gfxinit-y += hw-gfx-gma-power_and_clocks.adb diff --git a/common/valleyview/hw-gfx-gma-power_and_clocks.adb b/common/valleyview/hw-gfx-gma-power_and_clocks.adb new file mode 100644 index 0000000..f77aef1 --- /dev/null +++ b/common/valleyview/hw-gfx-gma-power_and_clocks.adb @@ -0,0 +1,144 @@ +-- +-- Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.Time; +with HW.GFX.GMA.Config; +with HW.GFX.GMA.DPIO; +with HW.GFX.GMA.IOSF; +with HW.GFX.GMA.PLLs; +with HW.GFX.GMA.Registers; + +with HW.Debug; +with GNAT.Source_Info; + +package body HW.GFX.GMA.Power_And_Clocks is + + CCK_FUSE_REG : constant := 16#0008#; + CCK_DISPLAY_CLOCK_CONTROL : constant := 16#006b#; + CCK_DISPLAY_REF_CLOCK_CONTROL : constant := 16#006c#; + + CCK_FREQUENCY_VALUES : constant := 16#001f#; + CCK_FREQUENCY_STATUS : constant := 16#1f00#; + + PUNIT_PWRGT_CONTROL : constant := 16#0060#; + PUNIT_PWRGT_STATUS : constant := 16#0061#; + + PUNIT_PWRGT_DPIO_MSK : constant := 3 * 2 ** 6; + + DPIO_CTL_CMNRST : constant := 1 * 2 ** 0; + + -- intel_display.c: vlv_get_hpll_vco() + function Vlv_Get_HPLL_Vco return Int64 + is + Vco_Freq : constant array (0 .. 3) of Int64 := (800, 1600, 2000, 2400); + Hpll_Sel : Word32; + begin + -- Obtain SKU information + IOSF.Vlv_Cck_Read (CCK_FUSE_REG, Hpll_Sel); + + return 1_000_000 * Vco_Freq (Natural (Hpll_Sel and 3)); + end Vlv_Get_HPLL_Vco; + + -- intel_display.c: vlv_get_cck_clock() + function Vlv_Get_Cck_Clock + (Register : in Word32; + Ref_Freq : in Int64) return Int64 + is + Value : Word32; + Divider : Word32; + begin + IOSF.Vlv_Cck_Read (Register, Value); + Divider := Value and CCK_FREQUENCY_VALUES; + + if Divider * 2 ** 8 /= (Value and CCK_FREQUENCY_STATUS) then + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug.Put_Line (" WARNING: Clock change in progress!")); + end if; + + return (Ref_Freq + Ref_Freq) / Int64 (Divider + 1); + end Vlv_Get_Cck_Clock; + + procedure Initialize + is + Hpll_Vco : Int64; + Value : Word32; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + -- Power Gate Status: This register indicates the status of the voltage + -- islands for the various blocks that the PUNIT controls. This register + -- is updated by the firmware after servicing a request from the driver + -- to power up/down of the various islands. The requests are done through + -- an analogous Power Gate Control register with the same bit layout. + -- + -- Each island is controlled by a 2-bit field: + -- 00 -- no clock nor power gating + -- 01 -- clock gating + -- 10 -- reset + -- 11 -- power gating + IOSF.Vlv_Punit_Read (PUNIT_PWRGT_STATUS, Value); + + -- Check if we need to ungate the Gunit + if (Value and PUNIT_PWRGT_DPIO_MSK) /= 0 then + pragma Debug (Debug.Put_Line ("Gunit is not ungated! Ungating...")); + + IOSF.Vlv_Punit_Write (PUNIT_PWRGT_CONTROL, PUNIT_PWRGT_DPIO_MSK); + Time.M_Delay (2); + IOSF.Vlv_Punit_Write (PUNIT_PWRGT_CONTROL, 0); + Time.M_Delay (2); + IOSF.Vlv_Punit_Read (PUNIT_PWRGT_STATUS, Value); + end if; + + -- De-assert DPIO common reset + Registers.Set_Mask (Registers.VLV_DPIO_CTL, DPIO_CTL_CMNRST); + + -- Before we start anything on Display pipeline, let's ask the CCU to + -- give us Spread Spectrum + Bend for the display clocks. + IOSF.Vlv_Ccu_Read (16#0114#, Value); + IOSF.Vlv_Ccu_Write (16#0114#, Value or 16#0003_0003#); + + Hpll_Vco := Vlv_Get_HPLL_Vco; + + -- intel_cdclk.c: vlv_get_cdclk() + Config.CDClk := Vlv_Get_Cck_Clock (CCK_DISPLAY_CLOCK_CONTROL, Hpll_Vco); + Config.Max_CDClk := 400_000_000; + + -- intel_cdclk.c: vlv_hrawclk() + Config.Raw_Clock := Vlv_Get_Cck_Clock (CCK_DISPLAY_REF_CLOCK_CONTROL, Hpll_Vco); + + end Initialize; + + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk * 90 / 100); + CDClk_Switch := False; + end Limit_Dotclocks; + + procedure Post_All_Off is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + -- Clear latency values to prevent flickering display without activity + Registers.Write (Registers.VLV_DDL1, 0); + Registers.Write (Registers.VLV_DDL2, 0); + + -- Assert DPIO common reset, clear SFR bypass and modesel bits + Registers.Write (Registers.VLV_DPIO_CTL, 0); + + end Post_All_Off; + +end HW.GFX.GMA.Power_And_Clocks; diff --git a/common/valleyview/hw-gfx-gma-power_and_clocks.ads b/common/valleyview/hw-gfx-gma-power_and_clocks.ads new file mode 100644 index 0000000..9997644 --- /dev/null +++ b/common/valleyview/hw-gfx-gma-power_and_clocks.ads @@ -0,0 +1,43 @@ +-- +-- Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA.Config_Helpers; + +private package HW.GFX.GMA.Power_And_Clocks is + + procedure Initialize; + + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => + not CDClk_Switch and + Config_Helpers.Stable_FB (Configs'Old, Configs); + + procedure Update_CDClk (Configs : in out Pipe_Configs) is null; + + procedure Enable_CDClk is null; + + procedure Pre_All_Off is null; + + procedure Post_All_Off; + + procedure Power_Set_To (Configs : Pipe_Configs) is null; + + procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs) is null; + + procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs) is null; + +end HW.GFX.GMA.Power_And_Clocks; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I1e359882b78ed7436ec90f2ac8c4276f70eca1b0 Gerrit-Change-Number: 44796 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020