coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/zork: Temporary init for backlight in the OS
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45854 ) Change subject: mb/google/zork: Temporary init for backlight in the OS ...................................................................... mb/google/zork: Temporary init for backlight in the OS This needs to go into ACPI, but that's taking me a while, so I figured I'd push this temporarily. Not for merge. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea --- M src/mainboard/google/zork/smihandler.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45854/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 12a3b64..6fc6f92 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -33,5 +33,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + /* Temporary fix - Needs to go into ACPI instead */ + /* Turn on the backlight when we go to ACPI mode */ + gpio_set(GPIO_85, 0); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea Gerrit-Change-Number: 45854 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Remove code that reconfigured the backlight GPIO
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45853 ) Change subject: mb/google/zork: Remove code that reconfigured the backlight GPIO ...................................................................... mb/google/zork: Remove code that reconfigured the backlight GPIO The SMU code was assuming that GPIO 85 was used for a fan, which caused interesting backlight flickering. That has now been fixed, so remove the code that reconfigured it to a GPIO on resume. BUG=b:155667589 TEST=Verify the screen does not flicker on resume from S3 BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 --- M src/mainboard/google/zork/mainboard.c 1 file changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45853/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 4206fdf..f0d9a28 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -188,25 +188,12 @@ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } -static const struct soc_amd_gpio gpio_set_bl[] = { - PAD_GPO(GPIO_85, LOW), -}; - -static void reset_backlight_gpio(void *unused) -{ - printk(BIOS_DEBUG, "Reset backlight GPIO\n"); - /* Re-Enable backlight - GPIO 85 active low */ - /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ - program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ -} - static void mainboard_final(void *chip_info) { struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); - reset_backlight_gpio(NULL); if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; @@ -231,5 +218,3 @@ *size = 0; return NULL; } - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/45853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 Gerrit-Change-Number: 45853 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack
by Jonathan Zhang (Code Review) 01 Oct '20

01 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45223 ) Change subject: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack ...................................................................... soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack Without skipping of DRHD generation for non-PCIe stack, the OS kernel detects incorrect DMRA table with following messages: [ 0.561817] Your BIOS is broken; DMAR reported at address 0! With this fix, another issue in DMAR table makes OS kernel continuously sending out following messages and OS becomes unusable: [ 123.568748] bnxt_en 0000:67:00.0 enp103s0: Resp cmpl intr err msg: 0x51 [ 123.582337] bnxt_en 0000:67:00.0 enp103s0: hwrm_ring_free type 1 failed. rc:ffffffff err:0 [ 123.600157] DMAR: DRHD: handling fault status reg 202 [ 123.610497] DMAR: [INTR-REMAP] Request device [67:00.0] fault index 2e [fault reason 34] Present field in the IRTE entry is clear It turns out the PCIe bridge device entries for PCIe ports in the DMAR table have incorrect dev/func values. Those values come from FSP IIO_UDS HOB. Hence a IPS ticket is filed, and we work around this FSP bug through hardcoding dev/func values. While at this, make some code improvements such as only find IIO_UDS HOB once while generating DMAR table. Change-Id: If31d2adf8c03bd57ef394834c03293a08dc4b21a Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 28 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45223/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..de3fcb4 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -588,17 +588,20 @@ */ static int get_stack_for_port(int p) { - if (p == 0) + if (p == PORT_0) return CSTACK; else if (p >= PORT_1A && p <= PORT_1D) return PSTACK0; else if (p >= PORT_2A && p <= PORT_2D) return PSTACK1; - else //if (p >= PORT_3A && p <= PORT_3D) + else if (p >= PORT_3A && p <= PORT_3D) return PSTACK2; + else + return -1; } -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +static unsigned long acpi_create_drhd(unsigned long current, int socket, + int stack, const IIO_UDS *hob) { int IoApicID[] = { // socket 0 @@ -612,12 +615,6 @@ uint32_t enum_id; unsigned long tmp = current; - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; uint32_t reg_base = @@ -625,6 +622,10 @@ printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", __func__, socket, stack, bus, pcie_seg, reg_base); + /* Do not generate DRHD for non-PCIe stack */ + if (reg_base == 0x0) + return current; + // Add DRHD Hardware Unit if (socket == 0 && stack == CSTACK) { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " @@ -670,13 +671,27 @@ if (socket != 0 || stack != CSTACK) { IIO_RESOURCE_INSTANCE iio_resource = hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + for (int p = 0; p < MAX_PORTS; ++p) { if (get_stack_for_port(p) != stack) continue; uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + /* TODO: remove this workaround when the IPS ticket is resolved. */ + if (p == 1 || p == 5) + dev = 0x0; + else if (p == 2 || p == 6) + dev = 0x1; + else if (p == 3 || p == 7) + dev = 0x2; + else if (p == 4 || p == 8) + dev = 0x3; + else if (p == 9) + dev = 0x0; + + func = 0x0; + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); if (id == 0xffffffff) @@ -858,11 +873,11 @@ if (socket == 0) { for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); + current = acpi_create_drhd(current, socket, stack, hob); + current = acpi_create_drhd(current, socket, CSTACK, hob); } else { for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, stack, hob); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31d2adf8c03bd57ef394834c03293a08dc4b21a Gerrit-Change-Number: 45223 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: vendorcode/google: consolidate strong mainboard_get_dram_part_num rou...
by Nick Vaccaro (Code Review) 01 Oct '20

01 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45636 ) Change subject: vendorcode/google: consolidate strong mainboard_get_dram_part_num routines ...................................................................... vendorcode/google: consolidate strong mainboard_get_dram_part_num routines Move mainboard_get_dram_part_num() into src/vendor/google/chromeos to allow mainboards to use it without having to duplicate that code. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also built coreboot for hatch, dedede, and deltaur and verified that the build succeeds without error. Change-Id: I49b7b2be7b46b5ffd6377d6caabd5e3e6c0a8d61 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/romstage.c M src/soc/intel/elkhartlake/romstage/romstage.c M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/spd_part_num_override.c 4 files changed, 25 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45636/1 diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 552648b..720ab7f 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -28,17 +28,3 @@ meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; - } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; -} diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index d68d2da..913237b 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - /* Default implementation, no need to override part number. */ - return false; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17236d..67e7b28 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -16,3 +16,5 @@ verstage-y += watchdog.c romstage-y += watchdog.c ramstage-y += watchdog.c + +romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += spd_part_num_override.c diff --git a/src/vendorcode/google/chromeos/spd_part_num_override.c b/src/vendorcode/google/chromeos/spd_part_num_override.c new file mode 100644 index 0000000..b4782ae --- /dev/null +++ b/src/vendorcode/google/chromeos/spd_part_num_override.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <spd_bin.h> +#include <string.h> + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + /* If we already have the string, return a pointer to it */ + if (!strlen(part_num_store) && + google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number" + "from CBI\n"); + return false; + } + *part_num = part_num_store; + *len = strlen(part_num_store); + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49b7b2be7b46b5ffd6377d6caabd5e3e6c0a8d61 Gerrit-Change-Number: 45636 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
by Felix Held (Code Review) 01 Oct '20

01 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42786 ) Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ...................................................................... [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 5 files changed, 192 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8c37ef5..4282c00 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,6 +8,7 @@ select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME @@ -29,6 +30,7 @@ config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP config MAINBOARD_DIR string @@ -37,10 +39,12 @@ config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME config DEVICETREE string @@ -57,6 +61,7 @@ config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs @@ -105,5 +110,6 @@ config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME -endif # BOARD_AMD_MANDOLIN +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3f..6f51233 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000..6a9b548 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 0x1000000 { + BIOS@0x0 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000..4870a27 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON" + + register "sd_emmc_config" = "SD_EMMC_DISABLE" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 on end # AHCI + device pci 0.1 off end # Ethernet + device pci 0.2 off end # Ethernet + end + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.3 on # - D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000..d38e52a --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_pcie_descriptor pollock_pcie_descriptors[] = +{ + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 1, + .end_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = +{ + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *pcie_descs = pollock_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pollock_pcie_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Gerrit-Change-Number: 42786 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

10 59

Change in coreboot[master]: 3rdparty/blobs: advance submodule pointer
by Felix Held (Code Review) 01 Oct '20

01 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45851 ) Change subject: 3rdparty/blobs: advance submodule pointer ...................................................................... 3rdparty/blobs: advance submodule pointer This pulls in the following changes: * soc/intel/baytrail/microcode.bin: Remove outdated microcode * mainboard/amd/mandolin: add Cereme APCB Only the latter one needs to land in the zork branch; it'll be used in the patch adding support for Cereme the AMD Pollock reference board. BRANCH=zork Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45851/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index bbe5d99..1aff9c3 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit bbe5d99780d2d085e92d9bae2c0f7b6787419d72 +Subproject commit 1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21 -- To view, visit https://review.coreboot.org/c/coreboot/+/45851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c Gerrit-Change-Number: 45851 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [UNTESTED] mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4
by Felix Held (Code Review) 01 Oct '20

01 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45831 ) Change subject: [UNTESTED] mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4 ...................................................................... [UNTESTED] mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4 BRANCH=zork Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45831/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 1d2fa5e..63b6306 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -110,7 +110,7 @@ config EFS_SPI_READ_MODE int default 0 if EM100 - default 5 + default 3 config EFS_SPI_SPEED int -- To view, visit https://review.coreboot.org/c/coreboot/+/45831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97 Gerrit-Change-Number: 45831 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [UNTESTED] mb/amd/mandolin: add missing SPI configuration to devicetree
by Felix Held (Code Review) 01 Oct '20

01 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45830 ) Change subject: [UNTESTED] mb/amd/mandolin: add missing SPI configuration to devicetree ...................................................................... [UNTESTED] mb/amd/mandolin: add missing SPI configuration to devicetree BUG=b:169644059 BRANCH=zork Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45830/1 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 7ccec27..3de5812 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -99,6 +99,15 @@ register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" + # eSPI Configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, -- To view, visit https://review.coreboot.org/c/coreboot/+/45830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Gerrit-Change-Number: 45830 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 01 Oct '20

01 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45747 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 14 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45747/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: payloads/external: add support for BOOTBOOT payload
by Zoltan Baldaszti (Code Review) 01 Oct '20

01 Oct '20

Zoltan Baldaszti has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45482 ) Change subject: payloads/external: add support for BOOTBOOT payload ...................................................................... payloads/external: add support for BOOTBOOT payload Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0 Signed-off-by: Zoltan Baldaszti <bztemail(a)gmail.com> --- A payloads/external/BOOTBOOT/Kconfig A payloads/external/BOOTBOOT/Kconfig.name A payloads/external/BOOTBOOT/Makefile M payloads/external/Makefile.inc 4 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45482/1 diff --git a/payloads/external/BOOTBOOT/Kconfig b/payloads/external/BOOTBOOT/Kconfig new file mode 100644 index 0000000..c9d7133 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig @@ -0,0 +1,6 @@ +if PAYLOAD_BOOTBOOT + +config PAYLOAD_FILE + default "payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf" + +endif diff --git a/payloads/external/BOOTBOOT/Kconfig.name b/payloads/external/BOOTBOOT/Kconfig.name new file mode 100644 index 0000000..082a9b1 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_BOOTBOOT + bool "BOOTBOOT" + depends on ARCH_X86 || ARCH_ARM64 + help + Select this option if you want to build a coreboot image + with a BOOTBOOT Protocol payload. + + See https://gitlab.com/bztsrc/bootboot for more information. diff --git a/payloads/external/BOOTBOOT/Makefile b/payloads/external/BOOTBOOT/Makefile new file mode 100644 index 0000000..5cd716a --- /dev/null +++ b/payloads/external/BOOTBOOT/Makefile @@ -0,0 +1,49 @@ +project_git_repo=https://gitlab.com/bztsrc/bootboot.git +project_dir=bootboot +ifeq ($(CONFIG_COREBOOT_BUILD),) +include ../../../.config +endif +ifeq ($(CONFIG_ARCH_ARM64),y) +loader_dir=$(project_dir)/aarch64-cb +else +loader_dir=$(project_dir)/x86_64-cb +endif + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: bootboot + +checkout: + echo " GIT BOOTBOOT $(loader_dir)" + @test -d ../../../../bootboot && ln -s ../../../../bootboot 2>/dev/null || true + test -L $(project_dir) || ( \ + ( test -d $(project_dir) || \ + git clone $(project_git_repo) $(project_dir) ) && \ + ( cd $(project_dir) && \ + git checkout master && \ + git remote update ) ) + +bootboot: libpayload + echo " MAKE $(loader_dir)" + $(MAKE) -C $(loader_dir) LIBCONFIG_PATH=../../../libpayload + +libpayload: checkout + cp $(loader_dir)/lib.config ../../libpayload/.config + cd ../../libpayload && $(MAKE) oldconfig && \ + $(MAKE) && $(MAKE) DESTDIR=../external/BOOTBOOT/$(loader_dir) install + +clean: + test -d $(loader_dir) && $(MAKE) -C $(loader_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: checkout bootboot libpayload clean distclean print-repo-info diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ef0990c..15d7348 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -303,3 +303,9 @@ CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ MFLAGS= MAKEFLAGS= + +# BOOTBOOT + +payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf: + $(MAKE) -C payloads/external/BOOTBOOT all + -- To view, visit https://review.coreboot.org/c/coreboot/+/45482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0 Gerrit-Change-Number: 45482 Gerrit-PatchSet: 1 Gerrit-Owner: Zoltan Baldaszti <bztemail(a)gmail.com> Gerrit-MessageType: newchange

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