coreboot-gerrit September 2020

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Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Benjamin Doron (Code Review) 01 Oct '20

01 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44995 ) Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Sep 2020 20:23:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 01 Oct '20

01 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 2: (4 comments) and I just remembered we want the TCSS xhci ports, not the PCH xhci................ that'll be more tricky, b/c that ASL code is a beast... could keep the device definition in ASL and just add https://review.coreboot.org/c/coreboot/+/45747/1/src/drivers/intel/xhci/xhc… File src/drivers/intel/xhci/xhci.c: https://review.coreboot.org/c/coreboot/+/45747/1/src/drivers/intel/xhci/xhc… PS1, Line 7: id > usb_rev ? much better https://review.coreboot.org/c/coreboot/+/45747/1/src/drivers/intel/xhci/xhc… PS1, Line 23: 9 > This buffer is too small to store the string ha yep https://review.coreboot.org/c/coreboot/+/45747/1/src/drivers/intel/xhci/xhc… PS1, Line 24: %2d > %2u Done https://review.coreboot.org/c/coreboot/+/45747/1/src/drivers/intel/xhci/xhc… PS1, Line 31: const struct drivers_intel_xhci_config *config = dev->chip_info; > nit: move this after the scope/name checks to safeguard against `dev` being null, or use `config_of( […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Sep 2020 20:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: spd: move mainboard_get_dram_part_num to src/vendor/google/chromeos
by Nick Vaccaro (Code Review) 01 Oct '20

01 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45588 ) Change subject: spd: move mainboard_get_dram_part_num to src/vendor/google/chromeos ...................................................................... spd: move mainboard_get_dram_part_num to src/vendor/google/chromeos Move mainboard_get_dram_part_num() into src/vendor/google/chromeos to allow mainboards to use it without having to duplicate that code. Add SPD_PART_NUMBER_IN_CBI Kconfig option to declare whether the SPD Module Part Number (memory part name) is stored in the CBI. Remove existing mainboard_get_dram_part_num() definitions from individual mainboards and replaced with appropriate SPD_PART_NUMBER_IN_CBI setting. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also built coreboot for hatch and dedede and verified that the build succeeds without error. Change-Id: Ie173b81b9c9a98f3744cc9da4b034d2251f5589b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/romstage.c M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/romstage_spd_cbfs.c M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/romstage.c M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/mainboard.c 8 files changed, 34 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/45588/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 79c2995..137247b 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -100,6 +100,9 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE +config SPD_PART_NUMBER_IN_CBI + def_bool y + config TPM_TIS_ACPI_INTERRUPT int default 4 # GPE0_DW0_4 (GPP_B4) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index db6f7db..02ebfac 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -21,19 +21,3 @@ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return false; - } - - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store); - return true; -} diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e4e343b..0b456b8 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -148,6 +148,10 @@ default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +config SPD_PART_NUMBER_IN_CBI + def_bool y + default n if ROMSTAGE_SPD_SMBUS + config TPM_TIS_ACPI_INTERRUPT int default 53 # GPE0_DW1_21 (GPP_C21) diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a9a65e9..0dae6cd 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -7,6 +7,7 @@ #include <memory_info.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <spd_bin.h> #include <string.h> #include <variant/gpio.h> @@ -56,29 +57,3 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } - -void mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - static enum { - PART_NUM_NOT_READ, - PART_NUM_AVAILABLE, - PART_NUM_NOT_IN_CBI, - } part_num_state = PART_NUM_NOT_READ; - - if (part_num_state == PART_NUM_NOT_READ) { - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - part_num_state = PART_NUM_NOT_IN_CBI; - } else { - part_num_state = PART_NUM_AVAILABLE; - } - } - - if (part_num_state == PART_NUM_NOT_IN_CBI) - return; - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store) + 1; -} diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index dda2f4e..040a171 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI @@ -100,6 +101,9 @@ hex default 0x1c000000 # 448 MiB +config SPD_PART_NUMBER_IN_CBI + def_bool y + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8893785..bec8f47 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -29,17 +29,3 @@ meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; - } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; -} diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17236d..04f68c4 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -16,3 +16,5 @@ verstage-y += watchdog.c romstage-y += watchdog.c ramstage-y += watchdog.c + +romstage-y += mainboard.c diff --git a/src/vendorcode/google/chromeos/mainboard.c b/src/vendorcode/google/chromeos/mainboard.c new file mode 100644 index 0000000..6cc6901 --- /dev/null +++ b/src/vendorcode/google/chromeos/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <spd_bin.h> +#include <string.h> + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + if (google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); + return false; + } + *part_num = part_num_store; + *len = strlen(part_num_store); + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie173b81b9c9a98f3744cc9da4b034d2251f5589b Gerrit-Change-Number: 45588 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add fields for the PSP to the transfer struct
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45803 ) Change subject: soc/amd/picasso: Add fields for the PSP to the transfer struct ...................................................................... soc/amd/picasso: Add fields for the PSP to the transfer struct The PSP will be adding information into these fields after verstage runs. This allows data to be passed directly to coreboot very early in the boot process. BUG=b:168895748 TEST=None Branch=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe --- M src/soc/amd/picasso/include/soc/psp_transfer.h 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45803/1 diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index 0996f64..be88ce8 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -30,7 +30,13 @@ uint32_t console_offset; uint32_t timestamp_offset; uint32_t fmap_offset; - uint32_t unused[9]; /* Pad to 64 bytes */ + + uint32_t unused1[5]; + + /* Fields reserved for the PSP */ + uint64_t timestamp; /* Offset 0x30 */ + uint32_t psp_unused; /* Offset 0x38 */ + uint32_t psp_info; /* Offset 0x3C */ }; _Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/45803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe Gerrit-Change-Number: 45803 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/stm: Fix size_t printf format error
by Eugene Myers (Code Review) 01 Oct '20

01 Oct '20

Hello Eugene Myers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45181 to review the following change. Change subject: security/intel/stm: Fix size_t printf format error ...................................................................... security/intel/stm: Fix size_t printf format error Size_t seems to have a compiler dependency. When building on the Purism librem 15v4, size_t is 'unsigned long'. In this instance, the compiler is the coreboot configured cross-compiler. In another instance, size_t is defined as 'unsigned short'. To get around the formatting conflict caused by this, The variable of type size_t was cast as 'unsigned int' in the format. Change-Id: Id51730c883d8fb9e87183121deb49f5fdda0114e Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M src/security/intel/stm/SmmStm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45181/1 diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 7256401..00490cf 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -477,7 +477,7 @@ return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08lx\n", resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int) resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; -- To view, visit https://review.coreboot.org/c/coreboot/+/45181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51730c883d8fb9e87183121deb49f5fdda0114e Gerrit-Change-Number: 45181 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by Tim Wawrzynczak (Code Review) 01 Oct '20

01 Oct '20

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44559 ) Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur This patch updates the SLP_Sx assertion widths and power cycle duration for volteer. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159108661 TEST=Verified that the power cycle duration is 1~2s with a global reset on volteer. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 43ba255..7790230 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -154,6 +154,40 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Set the minimum assertion width + # PchPmSlpS3MinAssert: + # - 1: 60us + # - 2: 1ms + # - 3: 50ms + # - 4: 2s + register "PchPmSlpS3MinAssert" = "3" # 50ms + # PchPmSlpS4MinAssert: + # - 1 = 1s + # - 2 = 2s + # - 3 = 3s + # - 4 = 4s + register "PchPmSlpS4MinAssert" = "1" # 1s + # PchPmSlpSusMinAssert: + # - 1 = 0ms + # - 2 = 500ms + # - 3 = 1s + # - 4 = 4s + register "PchPmSlpSusMinAssert" = "3" # 1s + # PchPmSlpAMinAssert + # - 1 = 0ms + # - 2 = 4s + # - 3 = 98ms + # - 4 = 2s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console: Add config EARLY_OVERRIDE_LOGLEVEL for overriding early log ...
by Johnny Lin (Code Review) 01 Oct '20

01 Oct '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45684 ) Change subject: console: Add config EARLY_OVERRIDE_LOGLEVEL for overriding early log level ...................................................................... console: Add config EARLY_OVERRIDE_LOGLEVEL for overriding early log level For early boot stages before POSTCAR it can override log level by get_option(), default set to n. Make init_log_level() set log level for all stages because get_log_level() is called by printk so avoid calling an overridden function in case it impacts performance. Tested=On OCP Delta Lake, log level can be overridden by get_option(). Change-Id: I532a88722c8e003b8e187a9714d26104c8ed8c6c Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/console/Kconfig M src/console/init.c 2 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45684/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index bad6c56..9a5d87b 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -309,6 +309,13 @@ help Send coreboot debug output to a System76 embedded controller. +config EARLY_OVERRIDE_LOGLEVEL + bool + default n + help + Set to "y" when the platform overrides the log level by get_option() + during early boot stages before POSTCAR. + config CONSOLE_OVERRIDE_LOGLEVEL bool help diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..a060683 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -12,21 +12,21 @@ #define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION static int console_inited; -static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +static int console_loglevel; static inline int get_log_level(void) { if (console_inited == 0) return -1; - if (CONSOLE_LEVEL_CONST) - return get_console_loglevel(); + if (CONSOLE_LEVEL_CONST && !CONFIG(EARLY_OVERRIDE_LOGLEVEL)) + return CONFIG_DEFAULT_CONSOLE_LOGLEVEL; return console_loglevel; } static inline void set_log_level(int new_level) { - if (CONSOLE_LEVEL_CONST) + if (CONSOLE_LEVEL_CONST && !CONFIG(EARLY_OVERRIDE_LOGLEVEL)) return; console_loglevel = new_level; @@ -34,10 +34,7 @@ static void init_log_level(void) { - int debug_level = get_console_loglevel(); - - if (CONSOLE_LEVEL_CONST) - return; + int debug_level = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; get_option(&debug_level, "debug_level"); -- To view, visit https://review.coreboot.org/c/coreboot/+/45684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I532a88722c8e003b8e187a9714d26104c8ed8c6c Gerrit-Change-Number: 45684 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by build bot (Jenkins) (Code Review) 30 Sep '20

30 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 25: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/romstage.c: https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… PS25, Line 46: __weak void variant_romstage_params(FSPM_UPD *const mupd) need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/gpio.c: https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… PS25, Line 44: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… PS25, Line 49: /* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/25/src/mainboard/siemens/chi… PS25, Line 95: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 25 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Sep 2020 11:48:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by build bot (Jenkins) (Code Review) 30 Sep '20

30 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 24: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/romstage.c: https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… PS24, Line 46: __weak void variant_romstage_params(FSPM_UPD *const mupd) need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/gpio.c: https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… PS24, Line 44: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… PS24, Line 49: /* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/24/src/mainboard/siemens/chi… PS24, Line 95: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 24 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Sep 2020 11:13:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Felix Singer (Code Review) 30 Sep '20

30 Sep '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39995 to look at the new patch set (#24). Change subject: mb/siemens/chili: Add Chili variant ...................................................................... mb/siemens/chili: Add Chili variant This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Fac… Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/chili/Kconfig.name M src/mainboard/siemens/chili/mainboard.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/chili/Makefile.inc A src/mainboard/siemens/chili/variants/chili/board_info.txt A src/mainboard/siemens/chili/variants/chili/data.vbt A src/mainboard/siemens/chili/variants/chili/devicetree.cb A src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads A src/mainboard/siemens/chili/variants/chili/gpio.c A src/mainboard/siemens/chili/variants/chili/hda_verb.c A src/mainboard/siemens/chili/variants/chili/romstage.c 13 files changed, 481 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39995/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 24 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2020