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Change in coreboot[master]: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
by Shelley Chen (Code Review) 03 Oct '20

03 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45740 ) Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ...................................................................... drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't do mmapping but still want to use the cbmem to store the mrc_cache data in order to write the mrc_cache data back at a later time. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fe0b9a7..acca7fe 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,6 +10,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..84cfbf0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..e5a119b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4..644c211 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,16 @@ Provide common implementation of the RW boot device that doesn't provide mmap() operations. +config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For x86 platforms who do not include the boot_device_rw_nommap libraries in romstage + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..00e9a3a 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config CBFS_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 29ebc6d..fe43a72 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -44,7 +44,6 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..6737c02 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,7 +41,6 @@ select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 33acf43..d35ae62 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -10,7 +10,6 @@ select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a30333b..71a17ff 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -25,7 +25,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..90b4e1d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..5c9988c 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -12,6 +12,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..c59e0ca 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 596de41..f043955 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -78,7 +78,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 91b45dc..ce2e0b4 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -13,7 +13,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..920f231 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1e66e97..6af8fd2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 15dc1b3..e851fbe 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index db0f688..1c8a7c0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -23,7 +23,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d92d496..6917ab9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..8d87628 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -29,7 +29,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/45740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Gerrit-Change-Number: 45740 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mrc_cache: Update mrc_cache data in romstage
by Shelley Chen (Code Review) 03 Oct '20

03 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44196 ) Change subject: mrc_cache: Update mrc_cache data in romstage ...................................................................... mrc_cache: Update mrc_cache data in romstage Previously, we were writing to cbmem after memory training and then writing the training data from cbmem to mrc_cache in ramstage. We were doing this because we were unable to read/write to SPI simultaneously on older SIP chips. Now that newer chips allow for simultaneously reads and writes, we can move the mrc_cache update into romstage. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen(a)google.com> Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 --- M src/drivers/elog/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/include/region_file.h M src/lib/region_file.c 4 files changed, 137 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44196/1 diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..a1c14ff 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c +romstage-$(CONFIG_ELOG) += elog.c postcar-$(CONFIG_ELOG_PRERAM) += elog.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 0e42120..2dc6ee8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -311,18 +311,26 @@ } static bool mrc_cache_needs_update(const struct region_device *rdev, - const struct cbmem_entry *to_be_updated) + struct mrc_metadata *new_md, + const void *new_data, size_t new_data_size) { - void *mapping; + void *mapping, *data_mapping; size_t size = region_device_sz(rdev); bool need_update = false; - if (cbmem_entry_size(to_be_updated) != size) + if (new_data_size != size) return true; mapping = rdev_mmap_full(rdev); + data_mapping = mapping + sizeof(struct mrc_metadata); - if (memcmp(cbmem_entry_start(to_be_updated), mapping, size)) + // we need to compare the md and the data separately + // check the mrc_metadata + if (memcmp(new_md, mapping, sizeof(struct mrc_metadata))) + need_update = true; + + // check the data + if (memcmp(new_data, data_mapping, new_data_size)) need_update = true; rdev_munmap(rdev, mapping); @@ -357,7 +365,10 @@ * read and write. The read assumes a memory-mapped boot device that can be used * to quickly locate and compare the up-to-date data. However, when an update * is required it uses the writeable region access to perform the update. */ -static void update_mrc_cache_by_type(int type) +static void update_mrc_cache_by_type(int type, + struct mrc_metadata *new_md, + const void *new_data, + size_t new_data_size) { const struct cache_region *cr; struct region region; @@ -365,7 +376,6 @@ struct region_device write_rdev; struct region_file cache_file; struct mrc_metadata md; - const struct cbmem_entry *to_be_updated; struct incoherent_rdev backing_irdev; const struct region_device *backing_rdev; struct region_device latest_rdev; @@ -376,13 +386,6 @@ if (cr == NULL) return; - to_be_updated = cbmem_entry_find(cr->cbmem_id); - if (to_be_updated == NULL) { - printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", - cr->name); - return; - } - printk(BIOS_DEBUG, "MRC: Checking cached data update for '%s'.\n", cr->name); @@ -411,8 +414,9 @@ return; - if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) { - printk(BIOS_DEBUG, "MRC: '%s' does not need update.\n", cr->name); + if (!mrc_cache_needs_update(&latest_rdev, + new_md, + new_data, new_data_size)) { log_event_cache_update(cr->elog_slot, ALREADY_UPTODATE); return; } @@ -420,9 +424,10 @@ printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) { - printk(BIOS_DEBUG, "MRC: failed to update '%s'.\n", cr->name); + new_md, + sizeof(struct mrc_metadata), + new_data, + new_data_size) < 0) { log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); @@ -544,16 +549,59 @@ /* Push an update that consists of 4 bytes that is smaller than the * MRC metadata as well as an invalid signature. */ - if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + if (region_file_update_data(&cache_file, NULL, 0, + &invalid, sizeof(invalid)) < 0) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +static void update_mrc_cache(struct mrc_metadata *md, + const void *data, + size_t size) { - update_mrc_cache_by_type(MRC_TRAINING_DATA); + update_mrc_cache_by_type(MRC_TRAINING_DATA, md, data, size); if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) - update_mrc_cache_by_type(MRC_VARIABLE_DATA); + update_mrc_cache_by_type(MRC_VARIABLE_DATA, + md, data, size); + + if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) + invalidate_normal_cache(); + + protect_mrc_region(); +} + +static void update_mrc_cache_from_cbmem(int type) +{ + const struct cache_region *cr; + struct region region; + struct mrc_metadata md; + const struct cbmem_entry *to_be_updated; + + cr = lookup_region(&region, type); + + if (cr == NULL) + return; + + to_be_updated = cbmem_entry_find(cr->cbmem_id); + + if (to_be_updated == NULL) { + printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", + cr->name); + return; + } + + update_mrc_cache(&md, + cbmem_entry_start(to_be_updated), + cbmem_entry_size(to_be_updated)); +} + +static void finalize_mrc_cache(void *unused) +{ + if (CONFIG(MRC_WRITE_NV_LATE)) + update_mrc_cache_from_cbmem(MRC_TRAINING_DATA); + + if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) + update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA); if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) invalidate_normal_cache(); @@ -562,11 +610,9 @@ } int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size) + size_t size) { const struct cache_region *cr; - size_t cbmem_size; - struct mrc_metadata *md; cr = lookup_region_type(type); if (cr == NULL) { @@ -575,24 +621,41 @@ return -1; } - cbmem_size = sizeof(*md) + size; + if (CONFIG(MRC_WRITE_NV_LATE)) { + /* Store data in cbmem for use in ramstage */ + struct mrc_metadata *md; + size_t cbmem_size; + cbmem_size = sizeof(*md) + size; - md = cbmem_add(cr->cbmem_id, cbmem_size); + md = cbmem_add(cr->cbmem_id, cbmem_size); - if (md == NULL) { - printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", - cr->name); - return -1; + if (md == NULL) { + printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", + cr->name); + return -1; + } + + memset(md, 0, sizeof(*md)); + md->signature = MRC_DATA_SIGNATURE; + md->data_size = size; + md->version = version; + md->data_checksum = compute_ip_checksum(data, size); + md->header_checksum = compute_ip_checksum(md, sizeof(*md)); + memcpy(&md[1], data, size); + } else { + /* Otherwise store to mrc_cache right away */ + struct mrc_metadata md; + + memset(&md, 0, sizeof(struct mrc_metadata)); + md.signature = MRC_DATA_SIGNATURE; + md.data_size = size; + md.version = version; + md.data_checksum = compute_ip_checksum(data, size); + md.header_checksum = + compute_ip_checksum(&md, sizeof(struct mrc_metadata)); + + update_mrc_cache(&md, data, size); } - - memset(md, 0, sizeof(*md)); - md->signature = MRC_DATA_SIGNATURE; - md->data_size = size; - md->version = version; - md->data_checksum = compute_ip_checksum(data, size); - md->header_checksum = compute_ip_checksum(md, sizeof(*md)); - memcpy(&md[1], data, size); - return 0; } @@ -602,7 +665,7 @@ */ #if CONFIG(MRC_WRITE_NV_LATE) -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL); #else -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, finalize_mrc_cache, NULL); #endif diff --git a/src/include/region_file.h b/src/include/region_file.h index 063e0e0..068e147 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -32,8 +32,11 @@ int region_file_data(const struct region_file *f, struct region_device *rdev); /* Update region file with latest data. Returns < 0 on error, 0 on success. */ -int region_file_update_data(struct region_file *f, const void *buf, - size_t size); +int region_file_update_data(struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size); /* Declared here for easy object allocation. */ struct region_file { diff --git a/src/lib/region_file.c b/src/lib/region_file.c index ce2ed30..3f47b28 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -365,11 +365,17 @@ return 0; } -static int commit_data(const struct region_file *f, const void *buf, - size_t size) +static int commit_data(const struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data_buf, + size_t data_size) { size_t offset = block_to_bytes(region_file_data_begin(f)); - if (rdev_writeat(&f->rdev, buf, offset, size) < 0) + if (rdev_writeat(&f->rdev, metadata, offset, metadata_size) < 0) + return -1; + offset += metadata_size; + if (rdev_writeat(&f->rdev, data_buf, offset, data_size) < 0) return -1; return 0; } @@ -399,8 +405,12 @@ return 0; } -static int handle_update(struct region_file *f, size_t blocks, const void *buf, - size_t size) +static int handle_update(struct region_file *f, + size_t blocks, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size) { if (!update_can_fit(f, blocks)) { printk(BIOS_INFO, "REGF update can't fit. Will empty.\n"); @@ -413,7 +423,7 @@ return -1; } - if (commit_data(f, buf, size)) { + if (commit_data(f, metadata, metadata_size, data, data_size)) { printk(BIOS_ERR, "REGF failed to commit data.\n"); return -1; } @@ -421,12 +431,18 @@ return 0; } -int region_file_update_data(struct region_file *f, const void *buf, size_t size) +int region_file_update_data(struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size) { int ret; size_t blocks; - blocks = bytes_to_block(ALIGN_UP(size, REGF_BLOCK_GRANULARITY)); + blocks = bytes_to_block(ALIGN_UP(data_size + + metadata_size, + REGF_BLOCK_GRANULARITY)); while (1) { int prev_slot = f->slot; @@ -442,7 +458,8 @@ ret = -1; break; default: - ret = handle_update(f, blocks, buf, size); + ret = handle_update(f, blocks, metadata, + metadata_size, data, data_size); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 Gerrit-Change-Number: 44196 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 43

Change in coreboot[master]: tgl/usb: disable TBT if hardware is not USB4
by Nick Vaccaro (Code Review) 03 Oct '20

03 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45832 ) Change subject: tgl/usb: disable TBT if hardware is not USB4 ...................................................................... tgl/usb: disable TBT if hardware is not USB4 TBT being enabled in FSP without USB4 hardware causes an issue powering off in depthcharge. Disable TBT for FSP if USB hardware is not USB4. BUG=b:167983038 TEST=none Change-Id: I07d5c416c79c40e9f85d721930549cf3374d327c Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/lib/fw_config.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 34 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45832/1 diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index fdfab0a..ec32059 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -127,5 +127,5 @@ } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..62316c4 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -310,10 +310,15 @@ /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) + if (is_dev_enabled(dev)) { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is enabled\n", i); params->ITbtPcieRootPortEn[i] = dev->enabled; - else + } else { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is disabled\n", i); params->ITbtPcieRootPortEn[i] = 0; + } } /* PCH FIVR settings override */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 3957299..569264c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -14,6 +14,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <fw_config.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) @@ -21,6 +22,7 @@ unsigned int i; uint32_t cpu_id, mask = 0; const struct device *dev; + bool usb4_device; /* * If IGD is enabled, set IGD stolen size to 60MB. @@ -115,19 +117,40 @@ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + usb4_device = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)); + /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - m_cfg->TcssDma0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssDma0En is enabled by fw_config\n"); + m_cfg->TcssDma0En = 1; + } else { + printk(BIOS_INFO, "TcssDma0En is disabled by fw_config\n"); + m_cfg->TcssDma0En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); m_cfg->TcssDma1En = is_dev_enabled(dev); /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie0En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie0En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TBT1); - m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie1En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie1En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TBT2); m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d5c416c79c40e9f85d721930549cf3374d327c Gerrit-Change-Number: 45832 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region
by Jonathan Zhang (Code Review) 02 Oct '20

02 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45391 ) Change subject: drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region ...................................................................... drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record Table) memory region: * Bootloader (firmware) generates UEFI CPER (Common Platform Error Record) records, and populates BERT region. In case of FSP 2.x, coreboot gets BERT region raw data from FSP (PREV_BOOT_ERROR_SRC_HOB). * OS parses ACPI BERT table, finds the BERT region address, inteprets the data and processes it accordingly. When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize, so FSP allocates memory region for it. The APEI BERT region is placed on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE. Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/drivers/intel/fsp2_0/cbmem.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45391/1 diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..f836b36 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,7 +6,10 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; + void *tolum_base; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + tolum_base = (void *)(uintptr_t)range_entry_base(&tolum); + + return tolum_base + cbmem_overhead_size(); } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e8..94fc653e 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,9 +43,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) + printk(BIOS_DEBUG, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); - die("Space between cbmem_top and BIOS TOLUM!\n"); - } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 07c4463..1ef9324 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -276,6 +276,21 @@ /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + /* + * If ACPI APEI BERT region size is defined, reserve memory for it. + * +------------------------+ range_entry_top(tolum) + * | Other reserved regions | + * | APEI BERT region | + * +------------------------+ cbmem_top() + * | CBMEM IMD ROOT | + * | CBMEM IMD SMALL | + * +------------------------+ range_entry_base(tolum), TOLUM + * | CBMEM FSP MEMORY | + * | Other CBMEM regions... | + */ + if (CONFIG(ACPI_BERT)) + arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; + /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/45391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Gerrit-Change-Number: 45391 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide
by Subrata Banik (Code Review) 02 Oct '20

02 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45808 ) Change subject: util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide ...................................................................... util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide BUG=b:153888802 TEST=Able to list correct PCH revision, SPI/eSPI frequency as per ADL SPI flash guide. Without this CL : PCH Revision: 500 series Tiger Point With this CL : PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45808/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index fab034a..220c140 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -72,7 +72,7 @@ "Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx", "100/200 series Sunrise Point", "300 series Cannon Point/ 400 series Ice Point", - "500 series Tiger Point", + "500 series Tiger Point/ 600 series Alder Point", "C620 series Lewisburg", NULL }; @@ -181,7 +181,7 @@ /* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */ if (((pchstrp_22 & 0x07) == 0x4) && ((pchstrp_22 & 0xFF0000) >> 16 == 0x58)) - return CHIPSET_500_SERIES_TIGER_POINT; + return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; return CHIPSET_PCH_UNKNOWN; } @@ -503,7 +503,7 @@ static void decode_spi_frequency(unsigned int freq) { - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) _decode_spi_frequency_500_series(freq); else _decode_spi_frequency(freq); @@ -560,7 +560,7 @@ static void decode_espi_frequency(unsigned int freq) { - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) _decode_espi_frequency_500_series(freq); else _decode_espi_frequency(freq); @@ -613,7 +613,7 @@ static int is_platform_with_100x_series_pch(void) { if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && - chipset <= CHIPSET_500_SERIES_TIGER_POINT) + chipset <= CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) return 1; return 0; @@ -638,7 +638,7 @@ if (is_platform_with_100x_series_pch() && chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { printf("\n Read eSPI/EC Bus Frequency: "); - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) freq = (fpsba->pchstrp[22] & 0x38) >> 3; else freq = (fcba->flcomp >> 17) & 7; @@ -911,7 +911,7 @@ printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); } - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) { + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) { printf("FLMAP3: 0x%08x\n", fdb->flmap3); printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index b725823..3444d9f 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -38,7 +38,9 @@ CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */ CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */ CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */ - CHIPSET_500_SERIES_TIGER_POINT, /* 11th gen Core i/o (LP) variants onwards */ + CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) + * variants onwards + */ CHIPSET_C620_SERIES_LEWISBURG, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Gerrit-Change-Number: 45808 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and...
by Jason V Le (Code Review) 02 Oct '20

02 Oct '20

Jason V Le has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45016 ) Change subject: /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for UP4 ...................................................................... /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for UP4 - Enable DDC pins for DDI-B - Enable HPD pins for DDI-1/DDI-2 - Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic Test: tested hot-plug/unplug HDMI displays with onboard micro-hdmi connector and type-C connectors to make sure the displays get detected and enabled Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45016/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 928ae36..c2c6902 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -18,13 +18,13 @@ register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 @@ -66,9 +66,16 @@ # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + register "DdiPortCHpd" = "0" + register "DdiPortCDdc" = "0" register "DdiPort1Hpd" = "1" - register "DdiPort1Ddc" = "1" + register "DdiPort1Ddc" = "0" + register "DdiPort2Hpd" = "1" + register "DdiPort2Ddc" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/45016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 Gerrit-Change-Number: 45016 Gerrit-PatchSet: 1 Gerrit-Owner: Jason V Le <jason.v.le(a)intel.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: drivers: sn65dsi86: Retry link training up to 5 times
by Julius Werner (Code Review) 02 Oct '20

02 Oct '20

Hello Douglas Anderson, Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45882 to review the following change. Change subject: drivers: sn65dsi86: Retry link training up to 5 times ...................................................................... drivers: sn65dsi86: Retry link training up to 5 times The kernel guys have found that automatic link training from this bridge can occasionally fail and needs to be retried. They think 5 retries should be enough but have added up to 10 to be sure. Let's do the same, but since things are synchronous for us and every try takes 500ms, maybe better restrict it to 5. BUG=b:169535092 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45882/1 diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index e0058c4..91e64aa 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -415,15 +415,18 @@ sn65dsi86_bridge_dpcd_request(bus, chip, DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); - /* semi auto link training mode */ - i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, 0xa); + int i; /* Kernel driver suggests to retry this a few times if it fails. */ + for (i = 0; i < 5; i++) { + i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, SEMI_AUTO_LINK_TRAINING); - if (!wait_ms(500, - !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && - (buf & NORMAL_MODE))) { - printk(BIOS_ERR, "ERROR: Link training failed"); + wait_ms(500, !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && + (buf == NORMAL_MODE || buf == MAIN_LINK_OFF)) + + if (buf == NORMAL_MODE) + return; } + printk(BIOS_ERR, "ERROR: Link training failed 5 times\n"); } static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip) -- To view, visit https://review.coreboot.org/c/coreboot/+/45882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 Gerrit-Change-Number: 45882 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: de-assert eMMC RST for Morphius
by Kevin Chiu (Code Review) 02 Oct '20

02 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45756 ) Change subject: mb/google/zork: de-assert eMMC RST for Morphius ...................................................................... mb/google/zork: de-assert eMMC RST for Morphius de-assert eMMC RST (GPIO68) to prevent eMMC abnormal. BUG=b:169211959 BRANCH=zork TEST=1. emerge-zork coreboot 2. check GPIO86 state is PU Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/gpio.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/1 diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 8da0de4..c1655fa 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -52,6 +52,8 @@ }; static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = { + /* EMMC_RESET */ + PAD_GPO(GPIO_68, HIGH), /* EN_DEV_BEEP_L */ PAD_GPO(GPIO_89, HIGH), /* TP */ @@ -60,6 +62,11 @@ PAD_GPO(GPIO_140, HIGH), }; +static const struct soc_amd_gpio morphius_gpio_set_stage_ram[] = { + /* EMMC_RESET */ + PAD_GPO(GPIO_68, HIGH), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -83,6 +90,6 @@ return morphius_bid3_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(morphius_gpio_set_stage_ram); + return morphius_gpio_set_stage_ram; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Gerrit-Change-Number: 45756 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/stm: Fix size_t printf format error
by Felix Held (Code Review) 02 Oct '20

02 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45872 ) Change subject: security/intel/stm: Fix size_t printf format error ...................................................................... security/intel/stm: Fix size_t printf format error This sort-of reverts commit 075df92298fe3bb0ef04233395effe668c4a5550 and fixes the underlying issue. The printf format string type/length specifier for a size_t type is z. Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/security/intel/stm/SmmStm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45872/1 diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 00490cf..e2fab0c 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -477,7 +477,7 @@ return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int) resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08zx\n", resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; -- To view, visit https://review.coreboot.org/c/coreboot/+/45872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Gerrit-Change-Number: 45872 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45804 ) Change subject: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block ...................................................................... vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac --- M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45804/1 diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 69ada34..684929d 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -54,6 +54,10 @@ #define SVC_SHA 0x46 #define SVC_RSAPKCS_VERIFY 0x47 +#define PSP_INFO_PRODUCTION_MODE 0x00000001UL +#define PSP_INFO_PRODUCTION_SI 0x00000002UL +#define PSP_INFO_VALID 0x80000000UL + typedef struct _RSAPSS_VERIFY_PARAMS_T { char *pHash; // Message digest to verify the RSA signature -- To view, visit https://review.coreboot.org/c/coreboot/+/45804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Gerrit-Change-Number: 45804 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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