Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 5 files changed, 192 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/1
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8c37ef5..4282c00 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
-if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,6 +8,7 @@ select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME
@@ -29,6 +30,7 @@ config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
config MAINBOARD_DIR string @@ -37,10 +39,12 @@ config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME
config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME
config DEVICETREE string @@ -57,6 +61,7 @@ config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs
@@ -105,5 +110,6 @@ config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME
-endif # BOARD_AMD_MANDOLIN +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3f..6f51233 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000..6a9b548 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 0x1000000 { + BIOS@0x0 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000..4870a27 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON" + + register "sd_emmc_config" = "SD_EMMC_DISABLE" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 on end # AHCI + device pci 0.1 off end # Ethernet + device pci 0.2 off end # Ethernet + end + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.3 on # - D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000..d38e52a --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_pcie_descriptor pollock_pcie_descriptors[] = +{ + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 1, + .end_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = +{ + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *pcie_descs = pollock_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pollock_pcie_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/1/src/mainboard/amd/mandolin/... File src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/42786/1/src/mainboard/amd/mandolin/... PS1, Line 7: { that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/42786/1/src/mainboard/amd/mandolin/... PS1, Line 63: { that open brace { should be on the previous line
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 6 files changed, 192 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/2/src/mainboard/amd/mandolin/... File src/mainboard/amd/mandolin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42786/2/src/mainboard/amd/mandolin/... PS2, Line 9: # APCB_mandolin.bin TODO: provide seperate APCB for Cereme 'seperate' may be misspelled - perhaps 'separate'?
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Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 6 files changed, 192 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG@7 PS3, Line 7: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant Are the GPIOs the same?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG@7 PS3, Line 7: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Are the GPIOs the same?
I'll still need to verify this. the code that was working at some point in time used the same GPIO configuration. shouldn't be that far off though. the patch is still WIP
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG@7 PS3, Line 7: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
I'll still need to verify this. […]
just checked and not all GPIOs the same. need to factor that out some patches earlier in the patch train
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 268 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 264 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#6).
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 263 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/6
Hello build bot (Jenkins), Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#7).
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 263 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#8).
Change subject: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Some GPIO settings are wrong and need to be fixed; the rest should be good.
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 342 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 333 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#10).
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 331 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/10
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42786/3//COMMIT_MSG@7 PS3, Line 7: [WIP] mb/amd: Add Pollock CRB Cereme as Mandolin variant
just checked and not all GPIOs the same. […]
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 10:
the patch still needs to be tested on real hardware
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#11).
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 337 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/11
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
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Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 337 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/12
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 120: default 5 we might need another setting for Cereme here, since it uses a different flash chip
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 12: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 131: Coprocesor Coproces*s*or
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 144: # - nit: alignment
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#13).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 342 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/13
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#14).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/14
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#15).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/15
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 15:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 131: Coprocesor
Coproces*s*or
Done
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 144: # -
nit: alignment
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 15: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/15/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS15: Can an overridetree be used?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/15/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS15:
Can an overridetree be used?
While this could be done, I intentionally didn't do this to make it easier to use Mandolin and Cereme as a starting point for another Picasso/Dali ("socket" FP5) or Pollock ("socket" FT5) based mainboard. FP5 and FT5 aren't interchangeable, so while certain silicon is put in both packages, it's still a different platform. There also has been an issue introduced by a devicetree override conversion on some old Thinkpad, so making this a devicetree override and then undoing that when creating a new board based on this creates additional risk of breaking things. This also mirrors what's done in mb/google/zork where we have a base devicetree for Picasso/Dali and one for Pollock; there are additional devicetree overrides for the different devices that are based on one of those two though.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/15/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS15:
While this could be done, I intentionally didn't do this to make it easier to use Mandolin and Cerem […]
Thanks. Please mention it in the commit message.
Patrick Georgi has uploaded a new patch set (#16) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
It's added as a separate board (and not a board variant) because the platforms are really different enough that later derivatives from these boards would have to untangle the variant handling, potentially leading to bugs.
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/16
Patrick Georgi has uploaded a new patch set (#17) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/17
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Martin Roth, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#18).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/18
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/15/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS15:
Thanks. Please mention it in the commit message.
done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 120: default 5
we might need another setting for Cereme here, since it uses a different flash chip
What to do about this?
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 18: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 18: Code-Review+2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 120: default 5
What to do about this?
Cereme uses the W74M12JW chip, which supports quad IO @66MHz, so I think this should be fine.
https://static6.arrow.com/aropdfconversion/4f4bceac1346022d4e8ae2d362e00a17e...
Hello build bot (Jenkins), Raul Rangel, Martin Roth, Patrick Georgi, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#19).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 346 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/19
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 120: default 5
Cereme uses the W74M12JW chip, which supports quad IO @66MHz, so I think this should be fine. […]
when Matt tested the patch maybe 2 weeks ago, it worked when EM100 was selected, but not if it wasn't even though he tested it with a flash chip and not with the EM100. not sure if this or the devicetree setting is the problem. I can only test the Mandolin + EM100 case, so that one works; don't have a Cereme or an 1.8V flasher
Matt Papageorge has uploaded a new patch set (#21) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 350 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/21
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
looks good to me, but i can't +2 this one, since i wrote part of this patch
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h I think it would be better to move this gpio.h to variants/baseboard/include/baseboard and then you can simply include <baseboard/gpio.h> rather than always having to trace the path to the file.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/42786/12/src/mainboard/amd/mandolin... PS12, Line 120: default 5
when Matt tested the patch maybe 2 weeks ago, it worked when EM100 was selected, but not if it wasn' […]
Done
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
I think it would be better to move this gpio. […]
that would result in duplicate gpio.h files though, right?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
that would result in duplicate gpio. […]
Not really. You will have one gpio.h file in variants/baseboard/include/baseboard that provides the declarations for all functions that are expected to be implemented by variants. And gpio.h files in variants/cereme/include/variant/gpio.h can simply include baseboard/gpio.h if they don't want to provide any of their own variant-specific definitions. You can check zork or volteer as examples.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 13: # TODO: provide separate APCB for Cereme I guess this would need to be handled at some point?
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
that would result in duplicate gpio. […]
IMHO, I find the baseboard subdir in `variants/` quite confusing. I think it would make more sense to have the `baseboard` concept out of `variants` for the sake of clarity.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 13: # TODO: provide separate APCB for Cereme
I guess this would need to be handled at some point?
it should be, but the APCB from mandolin also works for cereme. so while this should be done, it doesn't need to be done in order for this patch to land
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
IMHO, I find the baseboard subdir in `variants/` quite confusing. […]
in zork the baseboard thing makes much more sense than here imho, since there aren't multiple mandolin or cereme variants, but there are multiple variants of the two zork base boards
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
IMHO, I find the baseboard subdir in `variants/` quite confusing. […]
I look at the baseboard as providing: 1. Common infrastructure that is used by all variants 2. Header files that provide declarations for functions used by variants and common macro definitions used by all variants. 3. Weak function implementations which can be easily overriden by variant if required.
In my opinion, this provides a flexible way for variants to utilize common code at the reference board level while still retaining the ability to override if required and it also removes a lot of duplication that we used to do early on without baseboard/variants.
So, mainboard top level provides support for basic boot flows and callbacks from other common code e.g. SoC, library, drivers, etc. Mainboard top level code then makes a variant_* call to perform some task. Now, this variant_* can either be the default implementation provided by baseboard or something that is variant specific. So, all this implementation whether provided by baseboard/variant all lives under variants/.
But, I would be curious to understand your proposal for "baseboard out of variants".
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
in zork the baseboard thing makes much more sense than here imho, since there aren't multiple mandolin or cereme variants, but there are multiple variants of the two zork base boards
Sounds good.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
I look at the baseboard as providing:
- Common infrastructure that is used by all variants
- Header files that provide declarations for functions used by variants and common macro definitions used by all variants.
- Weak function implementations which can be easily overriden by variant if required.
In my opinion, this provides a flexible way for variants to utilize common code at the reference board level while still retaining the ability to override if required and it also removes a lot of duplication that we used to do early on without baseboard/variants.
So, mainboard top level provides support for basic boot flows and callbacks from other common code e.g. SoC, library, drivers, etc. Mainboard top level code then makes a variant_* call to perform some task. Now, this variant_* can either be the default implementation provided by baseboard or something that is variant specific. So, all this implementation whether provided by baseboard/variant all lives under variants/.
But, I would be curious to understand your proposal for "baseboard out of variants".
Oh, it's a very silly change. I agree that the baseboard concept is useful to keep things organized, but as it is currently implemented, things get really messy when there's multiple baseboards.
I'll use Zork as an example. There's two baseboards for Zork: Trembyle and Dalboz. AFAIUI, these baseboards are real boards, and also are a reference/example for ODMs that want to build their own Zork.
So, there would be a `mb/google/zork/baseboard` folder with the common baseboard files, and two `mb/google/zork/baseboard/trembyle` and `mb/google/zork/baseboard/dalboz` folders, each with the baseboard-specific devicetree and other stuff (everything with either `_trembyle` or `_dalboz` in the filename).
In addition, because Trembyle and Dalboz are real boards and thus need their own build targets, there would also be `mb/google/zork/variants/trembyle` and `mb/google/zork/variants/dalboz` folders (which already exist in the tree).
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 4: ../../gpio.h
I agree that the baseboard concept is useful to keep things organized, but as it is currently implemented, things get really messy when there's multiple baseboards.
I agree. Probably because it is the first time we have a mainboard using two different baseboards (Hatch and Puff are also in a similar boat). I agree with your point that the specific case of having two baseboards under a mainboard is not still cleanly handled and there is scope for organizing things better.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 21:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 13: # TODO: provide separate APCB for Cereme
it should be, but the APCB from mandolin also works for cereme. […]
https://review.coreboot.org/c/blobs/+/45657 will provide the correct APCB
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS21: the SPI settings are still missing; same for Mandolin. didn't run into that, since i use an EM100 for my tests
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Martin Roth, Patrick Georgi, Marshall Dawson, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#22).
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786,b:169644059 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 359 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/22
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Martin Roth, Patrick Georgi, Marshall Dawson, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#23).
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
[UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786,b:169644059 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 362 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/23
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... PS21, Line 13: # TODO: provide separate APCB for Cereme
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/21/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
PS21:
the SPI settings are still missing; same for Mandolin. […]
Done
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/23/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42786/23/src/mainboard/amd/mandolin... PS23, Line 105: .fast_speed = SPI_SPEED_66M, /* MHz */ This value should be 33M
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: [UNTESTED] mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 23: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42786/23/src/mainboard/amd/mandolin... File src/mainboard/amd/mandolin/variants/cereme/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42786/23/src/mainboard/amd/mandolin... PS23, Line 105: .fast_speed = SPI_SPEED_66M, /* MHz */
This value should be 33M
Nevermind, my blobs directory got downgraded when i rebased and that is what broke my build
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Martin Roth, Patrick Georgi, Marshall Dawson, Angel Pons, Matt Papageorge,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42786
to look at the new patch set (#24).
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786,b:169644059 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 362 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42786/24
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
Patch Set 24: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42786 )
Change subject: mb/amd: Add Pollock CRB Cereme as Mandolin variant ......................................................................
mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs.
BUG=b:159617786,b:169644059 BRANCH=zork
Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held felix-coreboot@felixheld.de Signed-off-by: Matt Papageorge matthewpapa07@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Kconfig.name M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/variants/cereme/board.fmd A src/mainboard/amd/mandolin/variants/cereme/devicetree.cb A src/mainboard/amd/mandolin/variants/cereme/early_gpio.c A src/mainboard/amd/mandolin/variants/cereme/gpio.c A src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c 8 files changed, 362 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Matt Papageorge: Looks good to me, but someone else must approve
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 63b6306..8e2bd8b 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
-if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,6 +8,7 @@ select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI @@ -31,6 +32,7 @@ config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
config MAINBOARD_DIR string @@ -39,10 +41,12 @@ config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME
config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME
config DEVICETREE string @@ -59,6 +63,7 @@ config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs
@@ -70,6 +75,7 @@ string depends on MANDOLIN_HAVE_MCHP_FW default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
if !AMD_LPC_DEBUG_CARD choice @@ -106,19 +112,22 @@ config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME
config EFS_SPI_READ_MODE int default 0 if EM100 + default 0 if BOARD_AMD_CEREME default 3
config EFS_SPI_SPEED int default 3 if EM100 + default 1 if BOARD_AMD_CEREME default 0
config EFS_SPI_MICRON_FLAG int default 0
-endif # BOARD_AMD_MANDOLIN +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3f..6f51233 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 6d7bf3a..7787018 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -10,7 +10,11 @@ ramstage-y += emmc_gpio.c endif
+ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin +else # CONFIG_BOARD_AMD_CEREME +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin +endif
PHONY+=add_mchp_fw INTERMEDIATE+=add_mchp_fw diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000..b55b8b5 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 0x20000 + RW_MRC_CACHE 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000..1553288 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec + + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port4 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port5 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping; all ports share one OC pin + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocessor + device pci 0.3 on end # USB 3.1 + device pci 0.4 off end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 off end # AHCI + device pci 0.1 off end # integrated Ethernet MAC + device pci 0.2 off end # integrated Ethernet MAC + end + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c new file mode 100644 index 0000000..b4ee5f4 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "../../gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe Reset 0 */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIe Reset 1 */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/gpio.c b/src/mainboard/amd/mandolin/variants/cereme/gpio.c new file mode 100644 index 0000000..0ba2580 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/gpio.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "../../gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* EC SCI# */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* not Blink */ + PAD_GPI(GPIO_11, PULL_UP), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* SD card detect */ + PAD_GPI(GPIO_31, PULL_UP), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* NFC wake output# */ + PAD_GPO(GPIO_89, HIGH), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000..8fc94f8 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor pollock_dxio_descriptors[] = { + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = pollock_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +}
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