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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45558 ) Change subject: mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax Change-Id: I620b9d3befd0a1a1440c6cc8908214b7b7a233bc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/superio.asl 1 file changed, 174 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45558/1 diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 705b2b9..342aae8 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -19,13 +19,13 @@ Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -55,13 +55,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -74,12 +74,12 @@ { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -104,8 +104,8 @@ IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = (_STA () & 0x02) + If (Local0 == 0) { Return(NONE) } @@ -117,15 +117,16 @@ \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) + Local0 = READ (0, 0x24, 0xfe) ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -138,29 +139,29 @@ WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -168,22 +169,23 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -200,18 +202,18 @@ { /* IRDA? */ Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -224,12 +226,12 @@ { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -254,8 +256,8 @@ IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -267,15 +269,15 @@ \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -288,55 +290,55 @@ WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -354,13 +356,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1b, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1b, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x02), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x02) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -373,12 +375,12 @@ { WRIT(0, 0x1b, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -403,8 +405,8 @@ IRQNoFlags(_IRA) { 5 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -416,15 +418,15 @@ \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1b, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0x00, 0x1b, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -437,29 +439,30 @@ WRIT(0, 0x1b, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe And(Local0, 0xfe, Local0) - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1b, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -467,22 +470,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -501,13 +504,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1c, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1c, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x04), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x04) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -520,12 +523,12 @@ { WRIT(0, 0x1c, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -550,8 +553,8 @@ IRQNoFlags(_IRA) { 11 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -563,15 +566,15 @@ \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1c, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x1c, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -584,29 +587,29 @@ WRIT(0, 0x1c, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -614,22 +617,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I620b9d3befd0a1a1440c6cc8908214b7b7a233bc Gerrit-Change-Number: 45558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45557 ) Change subject: mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax Change-Id: I41778aff742749934da1ed122f3aa13821638604 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/platform.asl 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45557/1 diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 98cecbc..3c092cf 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -9,23 +9,23 @@ TRAP(0xed) Sleep(1000) - Store(0, \_SB.ACFG) + \_SB.ACFG = 0 // Are we going to S4? - If (Lequal(Arg0, 4)) { + If (Arg0 == 4) { TRAP(0xe7) TRAP(0xea) } // Are we going to S5? - If (Lequal(Arg0, 5)) { + If (Arg0 == 5) { TRAP(0xde) } // The 2.6.12.5 ACPI engine seems to optimize the - // If(LEqual(Arg0, 5)) path away. This keeps it from doing so: + // If((Arg0 == 5) path away. This keeps it from doing so: TRAP(Arg0) - Store(Arg0, DBG0) + Arg0, DBG0 = Arg0 // End of ugly OS bug workaround } @@ -34,12 +34,12 @@ Method(_WAK,1) { // Enable GPS - Store (1, GP11) // GPSE + GP11 = 1 // GPSE // Wake from S3 or S4? - If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) { - If (And(CFGD, 0x01000000)) { - If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + If (CFGD & 0x01000000) { + If ((CFGD & 0xF0) && (OSYS == 2001)) { TRAP(0x3d) } } @@ -48,26 +48,26 @@ // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - If (LEqual(RP1D, 0)) { + If (RP1D == 0) { Notify(\_SB.PCI0.RP01, 0) } - If (LEqual(RP3D, 0)) { + If (RP3D == 0) { Notify(\_SB.PCI0.RP03, 0) } - If (LEqual(RP4D, 0)) { + If (RP4D == 0) { Notify(\_SB.PCI0.RP04, 0) } // Are we coming from S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { TRAP(0xeb) TRAP(0x46) } // Are we coming from S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { Notify(SLPB, 0x02) If (DTSE) { TRAP(0x47) @@ -75,16 +75,16 @@ } // Windows XP SP2 P-State restore - If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_SB.CP00._PPC, 0)) { - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + If ((OSYS == 2002) && (CFGD & 0x01)) { + If (\_SB.CP00._PPC > 0) { + \_SB.CP00._PPC -= 1 PNOT() - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() } Else { - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC -= 1 PNOT() } } @@ -118,7 +118,7 @@ * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 0x07D1) && MPEN) { TRAP(0x3d) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41778aff742749934da1ed122f3aa13821638604 Gerrit-Change-Number: 45557 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/google/dedede/var/madoo: Update DPTF setting
by John Su (Code Review) 14 Oct '20

14 Oct '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45784 ) Change subject: mb/google/dedede/var/madoo: Update DPTF setting ...................................................................... mb/google/dedede/var/madoo: Update DPTF setting Add tcc, critical, passive policy, and pl values from thermal team. BUG=b:169215576 TEST=build and verify by thermal tool Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a --- M src/mainboard/google/dedede/variants/madoo/overridetree.cb 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45784/1 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 039fd10..e73a728 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -53,7 +53,36 @@ }, }, }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "5" # TCC of 95C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU , 65, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "controls.power_limits.pl1" = "{ + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a Gerrit-Change-Number: 45784 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
by Brandon Breitenstein (Code Review) 14 Oct '20

14 Oct '20

Hello Divya S Sasidharan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42078 to review the following change. Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) ...................................................................... src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIS added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST= Tested boots from USB Type-C flash drive and Type-C to Type-A dongle on Volteer Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 105 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42078/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a97dfb3..22e57d2 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1374,7 +1374,7 @@ return ec_image_type; } -int google_chromeec_get_num_pd_ports(int *num_ports) +int google_chromeec_get_num_pd_ports(uint8_t *num_ports) { struct ec_response_charge_port_count resp = {}; struct chromeec_command cmd = { @@ -1435,6 +1435,91 @@ return (google_chromeec_get_current_image() == EC_IMAGE_RO); } +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +{ + struct ec_params_usb_pd_control pd_control = { + .port = port, + .role = USB_PD_CTRL_ROLE_NO_CHANGE, + .mux = USB_PD_CTRL_ROLE_NO_CHANGE, + .swap = USB_PD_CTRL_SWAP_NONE, + }; + struct ec_response_usb_pd_control_v2 resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_CONTROL, + .cmd_version = 2, + .cmd_data_in = &pd_control, + .cmd_size_in = sizeof(pd_control), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); + *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *dp_mode = resp.dp_mode; + + return 0; +} + +/** + * Return USB2 port mapping in bit 0:3 + * USB3 port mapping in bit 4:7 + */ +int google_chromeec_pd_get_port_info(int port, uint8_t *port_map) +{ + struct ec_params_locate_chip req = { + .type = EC_CHIP_TYPE_TCPC, + .index = port, + }; + struct ec_response_locate_chip resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_LOCATE_CHIP, + .cmd_version = 0, + .cmd_data_in = &req, + .cmd_size_in = sizeof(req), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *port_map = resp.reserved; + return 0; +} + +/** + * Check for the current mux state in EC + * Flags representing mux state can be + * found in ec_commands.h + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) +{ + if (port < 0) + return -1; + struct ec_params_usb_pd_mux_info req_mux = { + .port = port, + }; + struct ec_response_usb_pd_mux_info resp_mux = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_MUX_INFO, + .cmd_version = 0, + .cmd_data_in = &req_mux, + .cmd_size_in = sizeof(req_mux), + .cmd_data_out = &resp_mux, + .cmd_size_out = sizeof(resp_mux), + .cmd_dev_index = 0, + }; + if (google_chromeec_command(&cmd) < 0) + return -1; + + *flags = resp_mux.flags; + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * @@ -1443,22 +1528,16 @@ */ int google_chromeec_pd_get_amode(uint16_t svid) { - struct ec_response_usb_pd_ports resp; - struct chromeec_command cmd = { - .cmd_code = EC_CMD_USB_PD_PORTS, - .cmd_version = 0, - .cmd_data_in = NULL, - .cmd_size_in = 0, - .cmd_data_out = &resp, - .cmd_size_out = sizeof(resp), - .cmd_dev_index = 0, - }; + uint8_t num_ports; + int ret; + struct chromeec_command cmd; int i; - if (google_chromeec_command(&cmd) < 0) + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) return -1; - for (i = 0; i < resp.num_ports; i++) { + for (i = 0; i < num_ports; i++) { struct ec_params_usb_pd_get_mode_request params; struct ec_params_usb_pd_get_mode_response resp2; int svid_idx = 0; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aead5f7..3d95c16 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -27,6 +27,17 @@ enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); +/* Check for the current mux state in EC */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); +/* + * USB2 and USB3 port numbers between EC and AP + * is not one to one mapping, this function will return the + * correct mapped AP port number in port_map. + */ +int google_chromeec_pd_get_port_info(int port, uint8_t *port_map); +/* Returns data role and type of device connected */ +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, + uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ @@ -306,7 +317,7 @@ * of PD-capable USB ports according to the EC. * @return 0 on success, -1 on error */ -int google_chromeec_get_num_pd_ports(int *num_ports); +int google_chromeec_get_num_pd_ports(uint8_t *num_ports); /* Structure representing the capabilities of a USB-PD port */ struct usb_pd_port_caps { diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a2..b4a8ee1 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5331,10 +5331,6 @@ /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5641,7 +5637,7 @@ #define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { - uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ + uint8_t flags; /* USB_PD_CTRL_*-encoded USB mux state */ } __ec_align1; #define EC_CMD_PD_CHIP_INFO 0x011B -- To view, visit https://review.coreboot.org/c/coreboot/+/42078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Gerrit-Change-Number: 42078 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-MessageType: newchange

6 38

Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by Brandon Breitenstein (Code Review) 14 Oct '20

14 Oct '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42077 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... soc/intel/common/block: Enable PMC IPC driver In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a50..f7e2c13 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -9,6 +9,27 @@ /* Forward declare the power state struct here */ struct chipset_power_state; +/* pmc_ipc_buffer struct declaration to be used for IPC commands */ +struct pmc_ipc_buffer { + uint32_t buf0; + uint32_t buf1; + uint32_t buf2; + uint32_t buf3; +}; + +/* pmc_ipc_cmd union declaration to store cmd data for IPC commands */ +union pmc_ipc_cmd { + uint32_t cmd_reg; + struct { + uint32_t cmd:8; + uint32_t msi:1; + uint32_t res_1:3; + uint32_t subcmd:4; + uint32_t len:8; + uint32_t res_2:8; + }; +}; + /* * This is implemented as weak function in common pmc lib. * Clears all power management related registers as the boot @@ -220,4 +241,10 @@ */ void pmc_set_power_failure_state(bool target_on); +/* + * Send PMC IPC command + */ +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e..818a36b 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <delay.h> #include <halt.h> #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> @@ -16,6 +17,26 @@ #include <stdint.h> #include <string.h> #include <timer.h> +#include <types.h> + +/* define the offsets of all WBUFs */ +#define PMC_IPC_WBUF0 0x80 +#define PMC_IPC_WBUF1 0x84 +#define PMC_IPC_WBUF2 0x88 +#define PMC_IPC_WBUF3 0x8C + +/* define the offsets of all RBUFs */ +#define PMC_IPC_RBUF0 0x90 +#define PMC_IPC_RBUF1 0x94 +#define PMC_IPC_RBUF2 0x98 +#define PMC_IPC_RBUF3 0x9C + +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_STS_OFFSET 0x4 +#define PMC_IPC_STS_BUSY BIT(0) +#define PMC_IPC_STS_ERR BIT(1) +#define PMC_IPC_XFER_TIMEOUT_MS 1000 /* max 1s*/ static struct chipset_power_state power_state; @@ -574,3 +595,56 @@ pmc_soc_set_afterg3_en(on); } + +static enum cb_err check_ipc_sts(uintptr_t pmcbase) +{ + struct stopwatch sw; + uint32_t ipcsts; + + stopwatch_init_msecs_expire(&sw, PMC_IPC_XFER_TIMEOUT_MS); + do { + ipcsts = read32((void *)(pmcbase + PMC_IPC_STS_OFFSET)); + if (ipcsts & PMC_IPC_STS_ERR) + return CB_ERR; + + udelay(1); + + } while (!stopwatch_expired(&sw) && (ipcsts & PMC_IPC_STS_BUSY)); + + if (ipcsts & PMC_IPC_STS_BUSY) { + printk(BIOS_ERR, "IPC Timeout after %d ms\n", PMC_IPC_XFER_TIMEOUT_MS); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf) +{ + uintptr_t pmcbase; + + pmcbase = soc_read_pmc_base(); + + /* write the entire WBUF with the new PMC CMD Buffer */ + write32((void *)(pmcbase + PMC_IPC_WBUF0), wbuf->buf0); + write32((void *)(pmcbase + PMC_IPC_WBUF1), wbuf->buf1); + write32((void *)(pmcbase + PMC_IPC_WBUF2), wbuf->buf2); + write32((void *)(pmcbase + PMC_IPC_WBUF3), wbuf->buf3); + + /* Write the command register with the new command */ + write32((void *)(pmcbase + PMC_IPC_CMD_OFFSET), cmd); + + if (check_ipc_sts(pmcbase)) { + printk(BIOS_ERR, "PMC IPC command failed\n"); + return CB_ERR; + } + + /* get the response from the pmc out buffer */ + rbuf->buf0 = read32((void *)(pmcbase + PMC_IPC_RBUF0)); + rbuf->buf1 = read32((void *)(pmcbase + PMC_IPC_RBUF1)); + rbuf->buf2 = read32((void *)(pmcbase + PMC_IPC_RBUF2)); + rbuf->buf3 = read32((void *)(pmcbase + PMC_IPC_RBUF3)); + + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Gerrit-Change-Number: 42077 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

7 30

Change in coreboot[master]: mb/intel/tglrvp: Enable Pcie WWAN m.2
by Bora Guvendik (Code Review) 14 Oct '20

14 Oct '20

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45828 ) Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ...................................................................... mb/intel/tglrvp: Enable Pcie WWAN m.2 Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ad7eabe..be3ba0f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 49946c8..b63ee98 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -94,6 +94,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 3e2b342..1ba6bd6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,9 +20,9 @@ register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 91bbe93..eee3234 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -90,6 +90,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/45828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Gerrit-Change-Number: 45828 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: mb/google/zork: Enable wake on wireless lan
by Rob Barnes (Code Review) 14 Oct '20

14 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45745 ) Change subject: mb/google/zork: Enable wake on wireless lan ...................................................................... mb/google/zork: Enable wake on wireless lan Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 4 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45745/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..7e1c0ad 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -200,7 +200,13 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + register "maxsleep" = "3" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..f707465 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -200,7 +200,13 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + register "maxsleep" = "3" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index e69b47f..ab054ff 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -14,8 +14,8 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index bf25da3..a941087 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -14,8 +14,8 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Gerrit-Change-Number: 45745 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disa...
by Aamir Bohra (Code Review) 14 Oct '20

14 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34563 ) Change subject: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled ...................................................................... soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34563/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7eb413c..1058443 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -384,8 +384,12 @@ */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/34563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Gerrit-Change-Number: 34563 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Add common support for USB4/Thunderbolt
by Duncan Laurie (Code Review) 14 Oct '20

14 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44916 ) Change subject: soc/intel/common/block: Add common support for USB4/Thunderbolt ...................................................................... soc/intel/common/block: Add common support for USB4/Thunderbolt This common intel driver will add the requried ACPI _DSD entries for USB4/Thunderbolt ports that are enabled into the SSDT instead of using hardcoded values in the DSDT. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 --- A src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/usb4.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44916/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000..f588b27 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + help + Intel Processor common USB4/Thunderbolt support diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000..7dad4ba --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000..b33d774 --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + +#define INTEL_TBT_IMR_VALID_UUID "C44D002F-69F9-4E7D-A904-A7BAABDF43F7" +#define INTEL_TBT_WAKE_SUPPORTED_UUID "6C501103-C189-4296-BA72-9BF5A26EBE5D" + +static void usb4_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd, *pkg; + + if (!dev->enabled) + return; + + acpigen_write_scope(acpi_device_path(dev)); + + dsd = acpi_dp_new_table("_DSD"); + + /* Indicate that device has valid IMR. */ + pkg = acpi_dp_new_table(INTEL_TBT_IMR_VALID_UUID); + acpi_dp_add_integer(pkg, "IMR_VALID", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that device is wake capable. */ + pkg = acpi_dp_new_table(INTEL_TBT_WAKE_SUPPORTED_UUID); + acpi_dp_add_integer(pkg, "WAKE_SUPPORTED", 1); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = scan_static_bus, + .acpi_fill_ssdt = usb4_fill_ssdt, +}; + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static const struct pci_driver intel_usb4_driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Gerrit-Change-Number: 44916 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: sc7180: Enable bootblock compression
by Julius Werner (Code Review) 14 Oct '20

14 Oct '20

Hello Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45855 to review the following change. Change subject: sc7180: Enable bootblock compression ...................................................................... sc7180: Enable bootblock compression This patch enables bootblock compression on SC7180. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/decompressor.c M src/soc/qualcomm/sc7180/memlayout.ld 6 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45855/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 920ff5d..44517cb 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,6 +31,7 @@ $(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h +decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..addb49d 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a0d3bc6..7f52a9a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += timer.c + ################################################################################ bootblock-y += bootblock.c bootblock-y += mmu.c diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 7dbaeec..cfeb6f9 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -2,13 +2,11 @@ #include <bootblock_common.h> #include <soc/clock.h> -#include <soc/mmu.h> #include <soc/qspi.h> #include <soc/qupv3_config.h> void bootblock_soc_init(void) { - sc7180_mmu_init(); clock_init(); quadspi_init(37500 * KHz); qupv3_fw_init(); diff --git a/src/soc/qualcomm/sc7180/decompressor.c b/src/soc/qualcomm/sc7180/decompressor.c new file mode 100644 index 0000000..ac55150 --- /dev/null +++ b/src/soc/qualcomm/sc7180/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void decompressor_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..ea9a451 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -22,7 +22,7 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) SSRAM_END(0x146AE000) -- To view, visit https://review.coreboot.org/c/coreboot/+/45855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 Gerrit-Change-Number: 45855 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020