coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/kukui: Support SKU from camera EEPROM
by Yu-Ping Wu (Code Review) 19 Oct '20

19 Oct '20

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45811 to review the following change. Change subject: mb/google/kukui: Support SKU from camera EEPROM ...................................................................... mb/google/kukui: Support SKU from camera EEPROM To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/boardid.c 2 files changed, 102 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45811/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 532712a..7e065a3 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += sdram_params/ subdirs-y += panel_params/ -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += reset.c diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 548f36b..f8219fb 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -3,8 +3,14 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> -#include <soc/auxadc.h> +#include <delay.h> +#include <device/i2c_simple.h> #include <ec/google/chromeec/ec.h> +#include <soc/auxadc.h> +#include <soc/i2c.h> +#include <soc/pmic_wrap_common.h> +#include <string.h> +#include <vendorcode/google/chromeos/camera.h> /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 @@ -72,6 +78,97 @@ return id; } +static uint8_t eeprom_random_read(uint8_t bus, uint8_t slave, uint16_t offset, + uint8_t *data, uint16_t len) +{ + struct i2c_msg seg[2]; + uint8_t address[2]; + + address[0] = offset >> 8; + address[1] = offset & 0xff; + + seg[0].flags = 0; + seg[0].slave = slave; + seg[0].buf = address; + seg[0].len = sizeof(address); + seg[1].flags = I2C_M_RD; + seg[1].slave = slave; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + +/* Regulator for world facing camera. */ +#define PMIC_LDO_VCAMIO_CON0 0x1cb0 + +#define CROS_CAMERA_INFO_OFFSET 0x1f80 +#define MT8183_FORMAT 0x8183 +#define KODAMA_REVISION 0x00c7 + +/* Returns the ID for world facing camera. */ +static uint8_t wfc_id(void) +{ + if (!CONFIG(BOARD_GOOGLE_KODAMA)) + return 0; + + int i, ret; + uint8_t bus = 2; + uint8_t dev_addr = 0x50; /* at24c32/64 device address */ + + struct cros_camera_info data = {0}; + + const uint16_t sensor_models[] = { + [0] = 0x5965, /* OV5965 */ + [1] = 0x5035, /* GC5035 */ + }; + + mtk_i2c_bus_init(bus); + + /* Turn on camera sensor EEPROM */ + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x1); + udelay(270); + + ret = eeprom_random_read(bus, dev_addr, CROS_CAMERA_INFO_OFFSET, + (uint8_t *)&data, sizeof(data)); + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x0); + + if (ret) { + printk(BIOS_ERR, + "Failed to read from EEPROM; using default WFC id 0\n"); + return 0; + } + + if (check_cros_camera_info(&data)) { + printk(BIOS_ERR, + "Failed to check camera info; using default WFC id 0\n"); + return 0; + } + + if (data.data_format != MT8183_FORMAT) { + printk(BIOS_ERR, "Incompatible camera format: %#04x\n", + data.data_format); + return 0; + } + if (data.module_revision != KODAMA_REVISION) { + printk(BIOS_ERR, "Incompatible module revision: %#04x\n", + data.module_revision); + return 0; + } + + printk(BIOS_DEBUG, "Camera sensor model: %#04x\n", data.sensor_model); + + for (i = 0; i < ARRAY_SIZE(sensor_models); i++) { + if (data.sensor_model == sensor_models[i]) { + printk(BIOS_INFO, "Detected WFC id: %d\n", i); + return i; + } + } + + printk(BIOS_WARNING, "Unknown WFC id; using default id 0\n"); + return 0; +} + /* board_id is provided by ec/google/chromeec/ec_boardid.c */ uint32_t sku_id(void) @@ -98,11 +195,14 @@ /* * The SKU (later used for device tree matching) is combined from: + * World facing camera (WFC) ID. * ADC2[4bit/H] = straps on LCD module (type of panel). * ADC4[4bit/L] = SKU ID from board straps. */ - cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | + cached_sku_id = (wfc_id() << 8 | + get_adc_index(LCM_ID_CHANNEL) << 4 | get_adc_index(SKU_ID_CHANNEL)); + return cached_sku_id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Gerrit-Change-Number: 45811 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio: Add newline to log message about disabled mouse controller
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45805 ) Change subject: superio: Add newline to log message about disabled mouse controller ...................................................................... superio: Add newline to log message about disabled mouse controller A newline is missing at the end of the informational message. PNP: 002e.5 init nct5572d_init: Disable mouse controller.PNP: 002e.5 init finished in 0 msecs PNP: 002e.307 init Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Fixes: 6ff1078990 ("superio: Log if mouse controller is disabled") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83667hg-a/superio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45805/1 diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 351181c..c0a7118 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -36,7 +36,7 @@ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index bea2101..828fe9a 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -36,7 +36,7 @@ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); -- To view, visit https://review.coreboot.org/c/coreboot/+/45805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Gerrit-Change-Number: 45805 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]
by Angel Pons (Code Review) 17 Oct '20

17 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44880 ) Change subject: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] ...................................................................... security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] The BIOS ACM will check that enabled variable MTRRs do not cover more than the ACM's size, rounded up to 4 KiB. If that is not the case, launching the ACM will result in a lovely TXT reset. How boring. The new algorithm simply performs a reverse bit scan in a loop, and allocates one MTRR for each set bit in the rounded-up size to cache. Before allocating anything, it checks if there are enough variable MTRRs; if not, it will refuse to cache anything. This will result in another TXT reset, initiated by the processor, with error type 5: Load memory type error in Authenticated Code Execution Area. This can only happen if the ACM has different caching requirements that the current code does not know about, or something has been compromised. Therefore, causing a TXT reset should be a reasonable enough approach. Also, disable all MTRRs before clearing the variable MTRRs and only enable them again once they have been set up with the new values. Tested on Asrock B85M Pro4 with a BIOS ACM whose size is 101504 bytes. Without this patch, launching the ACM would result in a TXT reset. This no longer happens when this patch is appliedd. Change-Id: I8d411f6450928357544be20250262c2005d1e75d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 94 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/44880/1 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 3135de7..b78ab8a 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -107,10 +107,10 @@ orl $(CR0_CD | CR0_NW), %eax movl %eax, %cr0 - /* Disable fixed MTRRs */ + /* Disable all MTRRs */ movl $(MTRR_DEF_TYPE_MSR), %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_FIX_EN), %eax + xorl %eax, %eax + xorl %edx, %edx wrmsr /* @@ -164,24 +164,100 @@ * Chapter A.1.1 * Intel TXT Software Development Guide (Document: 315168-015) */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl 12(%ebp), %eax /* %eax = acmbase */ - orl $(6), %eax /* MTRR_TYPE_WB */ - movl $0, %edx - wrmsr - /* Round acmsize to next power of two. Required for MTRR programming. */ + /* + * Important note: The MTRRs must cache less than a page (4 KiB) + * of unused memory after the BIOS ACM. Failure to do so will + * result in a TXT reset with Class Code 5, Major Error Code 2. + */ + + /* Determine size of AC module */ + movl 12(%ebp), %eax /* %eax = acmbase */ movl $1, %ebx - movl 16(%ebp), %ecx /* %ebx = acmsize */ - dec %ecx - bsr %ecx, %ecx /* find MSB */ - inc %ecx - shl %cl, %ebx - movl $(MTRR_PHYS_MASK(0)), %ecx - xorl %eax, %eax - subl %ebx, %eax /* %eax = 4GIB - log2_ceil(ACM SIZE) */ - orl $((1 << 11)), %eax /* MTRR_PHYS_MASK_VALID */ + movl 16(%ebp), %ebx /* %ebx = acmsize */ + + /* Round up to page size */ + addl $(0xfff), %ebx + andl $(~0xfff), %ebx /* Aligned to a page (4 KiB) */ + + /* Use XMM to store local variables */ + movd %eax, %xmm0 /* XMM0: Base address of next MTRR */ + movd %ebx, %xmm1 /* XMM1: Remaining size to cache */ + + /* Get the number of variable MTRRs */ + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + + /* Initialize ECX */ + movl $(MTRR_PHYS_BASE(0)), %ecx + + /* Check if there are enough variable MTRRs to cache this size */ + popcnt %ebx, %edx + cmp %eax, %edx + + jbe cond_allocate_var_mtrrs + + /* + * There aren't enough MTRRs to handle this size. + * The ACM will be uncached, and will invoke TXT reset. + * + * FIXME: Do proper error handling? + */ + xorl %ebx, %ebx + movd %ebx, %xmm1 + + jmp cond_allocate_var_mtrrs + +body_allocate_var_mtrrs: + + /* Program MTRR base */ + xorl %edx, %edx + movd %xmm0, %eax + orl $(MTRR_TYPE_WRBACK), %eax + wrmsr + incl %ecx /* MTRR_PHYS_MASK */ + + /* Temporarily transfer MSR index to EDX so that CL can be used */ + movl %ecx, %edx + + /* Determine next size to cache */ + bsr %ebx, %ecx + movl $(1), %ebx + shl %cl, %ebx /* Can only use CL here */ + + /* Restore ECX */ + movl %edx, %ecx + + /* Update saved base address */ + addl %ebx, %eax + movd %eax, %xmm0 + + /* Update saved remaining size */ + movd %xmm1, %eax + subl %ebx, %eax + movd %eax, %xmm1 + + /* Program MTRR mask */ movl MTRR_HIGH_MASK, %edx + xorl %eax, %eax + subl %ebx, %eax /* %eax = 4GIB - size to cache */ + orl $((1 << 11)), %eax /* MTRR_PHYS_MASK_VALID */ + wrmsr + incl %ecx /* Next MTRR_PHYS_BASE */ + +cond_allocate_var_mtrrs: + + /* Check if we still need to cache something */ + movd %xmm1, %ebx + andl %ebx, %ebx + + jnz body_allocate_var_mtrrs + + /* Enable variable MTRRs */ + movl $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + orl $(MTRR_DEF_TYPE_EN), %eax wrmsr /* Enable cache - GPF# if not done */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d411f6450928357544be20250262c2005d1e75d Gerrit-Change-Number: 44880 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Add USB 2.0 strength for Woomax
by Kane Chen (Code Review) 16 Oct '20

16 Oct '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45641 ) Change subject: mb/google/zork: Add USB 2.0 strength for Woomax ...................................................................... mb/google/zork: Add USB 2.0 strength for Woomax Add USB 2.0 setting: 1. USB 2.0 TypeC port0 0xf1333e13. 2. USB 2.0 TypeC port3 0xf1333e13. BUG=None BRANCH=None TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550 --- M src/mainboard/google/zork/variants/woomax/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45641/1 diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index de39891..f6eb165 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -22,6 +22,30 @@ register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" # USB OC pin mapping register "usb_port_overcurrent_pin[2]" = "USB_OC_NONE" # NC -- To view, visit https://review.coreboot.org/c/coreboot/+/45641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550 Gerrit-Change-Number: 45641 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/usb4: Add driver for USB4 PCIe root port
by Duncan Laurie (Code Review) 16 Oct '20

16 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44915 ) Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ...................................................................... drivers/intel/usb4: Add driver for USB4 PCIe root port This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb --- A src/drivers/intel/usb4/Kconfig A src/drivers/intel/usb4/Makefile.inc A src/drivers/intel/usb4/pcie/Kconfig A src/drivers/intel/usb4/pcie/Makefile.inc A src/drivers/intel/usb4/pcie/chip.h A src/drivers/intel/usb4/pcie/pcie.c 6 files changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/1 diff --git a/src/drivers/intel/usb4/Kconfig b/src/drivers/intel/usb4/Kconfig new file mode 100644 index 0000000..93501aa --- /dev/null +++ b/src/drivers/intel/usb4/Kconfig @@ -0,0 +1 @@ +source "src/drivers/intel/usb4/*/Kconfig" diff --git a/src/drivers/intel/usb4/Makefile.inc b/src/drivers/intel/usb4/Makefile.inc new file mode 100644 index 0000000..4c02663 --- /dev/null +++ b/src/drivers/intel/usb4/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += ./* diff --git a/src/drivers/intel/usb4/pcie/Kconfig b/src/drivers/intel/usb4/pcie/Kconfig new file mode 100644 index 0000000..6363939 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_INTEL_USB4_PCIE + bool diff --git a/src/drivers/intel/usb4/pcie/Makefile.inc b/src/drivers/intel/usb4/pcie/Makefile.inc new file mode 100644 index 0000000..b5d3e94 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_PCIE) += pcie.c diff --git a/src/drivers/intel/usb4/pcie/chip.h b/src/drivers/intel/usb4/pcie/chip.h new file mode 100644 index 0000000..b821d47 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_PCIE_H__ +#define __DRIVERS_INTEL_USB4_PCIE_H__ + +struct drivers_intel_usb4_pcie_config { + const char *desc; + + /* USB port number */ + unsigned int port_id; + + /* Pointer to USB4 device that this PCIe root port is routed to. */ + DEVTREE_CONST struct device *usb4_port; +}; + +#endif /* __DRIVERS_INTEL_USB4_PCIE_H__ */ diff --git a/src/drivers/intel/usb4/pcie/pcie.c b/src/drivers/intel/usb4/pcie/pcie.c new file mode 100644 index 0000000..bba803f --- /dev/null +++ b/src/drivers/intel/usb4/pcie/pcie.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci_def.h> +#include <stdlib.h> +#include <string.h> +#include "chip.h" + +#define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" +#define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" + +static void usb4_pcie_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + struct acpi_dp *dsd, *pkg; + const char *usb4_path; + + if (!dev->enabled) + return; + if (!config->usb4_port) + return; + + /* Get ACPI path to USB4 device. */ + usb4_path = acpi_device_path(config->usb4_port); + if (!usb4_path) + return; + usb4_path = strdup(usb4_path); + + acpigen_write_scope(acpi_device_path(dev)); + + /* Add pointer to USB4 port controller. */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_reference(dsd, "usb4-host-interface", usb4_path); + acpi_dp_add_integer(dsd, "usb4-port-number", config->port_id); + + /* Indicate that device supports hotplug in D3. */ + pkg = acpi_dp_new_table(PCI_HOTPLUG_IN_D3_UUID); + acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that port is external. */ + pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); + acpi_dp_add_integer(pkg, "UID", config->port_id); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); +} + +static struct device_operations usb4_pcie_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_pcie_fill_ssdt, +}; + +static void usb4_pcie_enable(struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + + dev->ops = &usb4_pcie_dev_ops; + + if (config->desc) + dev->name = config->desc; + else + config->desc = dev->chip_ops->name; +} + +struct chip_operations drivers_intel_usb4_pcie_ops = { + CHIP_NAME("Intel USB4 PCIe Root Port") + .enable_dev = usb4_pcie_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Gerrit-Change-Number: 44915 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Add get_system_memory_map()
by Marc Jones (Code Review) 16 Oct '20

16 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45847 ) Change subject: soc/intel/xeon_sp: Add get_system_memory_map() ...................................................................... soc/intel/xeon_sp: Add get_system_memory_map() Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_util.c 3 files changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45847/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index c7f7383..0eac836 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -30,6 +30,7 @@ void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); +const struct SystemMemoryMapHob *get_system_memory_map(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 4296f22..c116506 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -179,13 +179,11 @@ static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) { const struct SystemMemoryMapHob *memory_map; - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; unsigned int mmap_index; - memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memory_map != NULL && hob_size != 0); - printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + memory_map = get_system_memory_map(); + assert(memory_map != NULL); + printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); mmap_index = 0; for (int e = 0; e < memory_map->numberEntries; ++e) { diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index e21edbc..179b08f 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -373,6 +373,21 @@ } #if ENV_RAMSTAGE +const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; + + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ + assert(memmap_addr != NULL && hob_size != 0); + /* assert the pointer to the hob is not NULL */ + assert(*memmap_addr != NULL); + + return *memmap_addr; +} void xeonsp_init_cpu_config(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Gerrit-Change-Number: 45847 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: Update bit field helpers to support more bit field operate
by CK HU (Code Review) 15 Oct '20

15 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44705 to review the following change. Change subject: Update bit field helpers to support more bit field operate ...................................................................... Update bit field helpers to support more bit field operate Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I8f182fff45806912da2390939a6652932501d7c5 --- M src/include/device/mmio.h 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44705/1 diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b4461e0..96bf28c 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -150,21 +150,44 @@ _BF_APPLY6(op, __VA_ARGS__)) #define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLY9(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY8(op, __VA_ARGS__)) +#define _BF_APPLY10(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY9(op, __VA_ARGS__)) +#define _BF_APPLY11(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY10(op, __VA_ARGS__)) +#define _BF_APPLY12(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY11(op, __VA_ARGS__)) +#define _BF_APPLY13(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY12(op, __VA_ARGS__)) +#define _BF_APPLY14(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY13(op, __VA_ARGS__)) +#define _BF_APPLY15(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY14(op, __VA_ARGS__)) +#define _BF_APPLY16(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY15(op, __VA_ARGS__)) #define _BF_APPLYINVALID(...) \ _Static_assert(0, "Invalid arguments for {WRITE,SET}*_BITFIELDS") #define _BF_IMPL2(op, addr, \ n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, n13, v13, n14, v14, n15, v15, n16, v16, \ NARGS, ...) \ \ op(addr, \ _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8), \ + n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16 ), \ _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8)) + n5, v5, n6, v6, n7, v7, n8, v8,\ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16)) #define _BF_IMPL(op, addr, ...) \ _BF_IMPL2(op, addr, __VA_ARGS__, \ + 16, INVALID, 15, INVALID, 14, INVALID, 13, INVALID, \ + 12, INVALID, 11, INVALID, 10, INVALID, 9, INVALID, \ 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) -- To view, visit https://review.coreboot.org/c/coreboot/+/44705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f182fff45806912da2390939a6652932501d7c5 Gerrit-Change-Number: 44705 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/tigerlake: Enable and use USB4 PCIe driver
by Duncan Laurie (Code Review) 15 Oct '20

15 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44917 ) Change subject: soc/intel/tigerlake: Enable and use USB4 PCIe driver ...................................................................... soc/intel/tigerlake: Enable and use USB4 PCIe driver This change enables the USB4/Thunderbolt common layer for Intel SOC, and enables the Intel USB4 PCIe driver. This moves the _DSD variables from the DSDT into the SSDT and allows them to be configured for each board if necessary. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/chipset.cb 8 files changed, 59 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44917/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 636d946..2717acd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -377,13 +377,17 @@ device generic 0 on end end end - device ref tbt_pcie_rp0 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/pcie + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end end - device ref tbt_pcie_rp1 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/pcie + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end end device ref tbt_dma0 on probe DB_USB USB4_GEN2 diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 2db3b96..68269b5 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -18,7 +18,9 @@ register "SaGv" = "SaGv_Disabled" device domain 0 on - device pci 07.2 on end # TBT_PCIe2 + chip drivers/intel/usb4/pcie + device pci 07.2 on end # TBT_PCIe2 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 6f14622..9d9a376 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -27,10 +27,18 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + chip drivers/intel/usb4/pcie + device pci 07.0 off end # TBT_PCIe0 0x9A23 + end + chip drivers/intel/usb4/pcie + device pci 07.1 off end # TBT_PCIe1 0x9A25 + end + chip drivers/intel/usb4/pcie + device pci 07.2 off end # TBT_PCIe2 0x9A27 + end + chip drivers/intel/usb4/pcie + device pci 07.3 off end # TBT_PCIe3 0x9A29 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index b184924..a4f3afe 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -34,10 +34,18 @@ }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + chip drivers/intel/usb4/pcie + device pci 07.0 off end # TBT_PCIe0 0x9A23 + end + chip drivers/intel/usb4/pcie + device pci 07.1 off end # TBT_PCIe1 0x9A25 + end + chip drivers/intel/usb4/pcie + device pci 07.2 off end # TBT_PCIe2 0x9A27 + end + chip drivers/intel/usb4/pcie + device pci 07.3 off end # TBT_PCIe3 0x9A29 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3b0df5d..250840f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -17,6 +17,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select DRIVERS_INTEL_USB4_PCIE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB @@ -51,6 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index da2e8fe..d00f794 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -82,30 +82,3 @@ { Return (Package() { 0x6D, 4 }) } - -Method (_DSD, 0) -{ - Return( - Package() - { - /* Thunderbolt GUID for IMR_VALID at ../drivers/acpi/property.c */ - ToUUID("C44D002F-69F9-4E7D-A904-A7BAABDF43F7"), - Package () - { - Package (2) { "IMR_VALID", 1 } - }, - - /* Thunderbolt GUID for WAKE_SUPPORTED at ../drivers/acpi/property.c */ - ToUUID("6C501103-C189-4296-BA72-9BF5A26EBE5D"), - Package () - { - Package (2) { "WAKE_SUPPORTED", 1 } - } - } - ) -} - -Method (_DSM, 4, Serialized) -{ - Return (Buffer() { 0 }) -} diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index abca5d1..3f495be 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -216,85 +216,6 @@ } } -Method (_DSD, 0) { - If ((TUID == 0) || (TUID == 1)) { - Return ( Package() { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", TUID }, - } - }) - } ElseIf (TUID == 2) { - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 0 }, - } - }) - } Else { /* TUID == 3 */ - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 1 }, - } - }) - } -} - Method (_S0W, 0x0, NotSerialized) { Return (0x4) diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 0d2b7a2..43c99a5 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -5,10 +5,26 @@ device pci 04.0 alias dptf off end device pci 05.0 alias ipu off end device pci 06.0 alias peg off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + chip drivers/intel/usb4/pcie + register "port_id" = "0" + use tbt_dma0 as usb4_port + device pci 07.0 alias tbt_pcie_rp0 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "1" + use tbt_dma0 as usb4_port + device pci 07.1 alias tbt_pcie_rp1 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "0" + use tbt_dma1 as usb4_port + device pci 07.2 alias tbt_pcie_rp2 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "1" + use tbt_dma1 as usb4_port + device pci 07.3 alias tbt_pcie_rp3 off end + end device pci 08.0 alias gna off end device pci 09.0 alias npk off end device pci 0a.0 alias crashlog off end -- To view, visit https://review.coreboot.org/c/coreboot/+/44917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd Gerrit-Change-Number: 44917 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 26

Change in coreboot[master]: mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin
by Shaunak Saha (Code Review) 15 Oct '20

15 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45643 ) Change subject: mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin ...................................................................... mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer EVT and Delbin. BUG=b:158573805 TEST=Build and boot volteer evt and confirm that FspSiliconInit time is reduced. In Volteer this saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45643/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 05c8a34..7624d40 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,8 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "HybridStorageMode" = "0" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..b6d5c8a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -5,6 +5,8 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "HybridStorageMode" = "0" + device domain 0 on device pci 05.0 on end # IPU 0x9A19 device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Gerrit-Change-Number: 45643 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

3 23

Change in coreboot[master]: soc/intel/jasperlake: Enable CAR NEM enhanced mode
by Aamir Bohra (Code Review) 14 Oct '20

14 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43705 ) Change subject: soc/intel/jasperlake: Enable CAR NEM enhanced mode ...................................................................... soc/intel/jasperlake: Enable CAR NEM enhanced mode Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7 --- M src/soc/intel/jasperlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/43705/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 89bbdd3..05543ea 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -24,7 +24,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/43705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7 Gerrit-Change-Number: 43705 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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