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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add MIPI camera support
by Chen Wisley (Code Review) 24 Oct '20

24 Oct '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44939 ) Change subject: mb/google/dedede/var/drawcia: Add MIPI camera support ...................................................................... mb/google/dedede/var/drawcia: Add MIPI camera support 1. enable IPU 2. enable VARIANT_HAS_CAMERA_ACPI 3. add VCM/NVM asl code BUG=b:163879470 TEST=follow steps on issue tracker to grap picture manually. Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 6 files changed, 455 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44939/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 40738a0..5924ac1 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -20,6 +20,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" @@ -27,6 +28,7 @@ select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_MADOO bool "-> Madoo" diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..1e9218e --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + If ((STA == Zero)) + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + /* Assert Reset */ + PON() + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA = 1 + } + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + If ((STA == One)) + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + POFF() + STA = 0 + } + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device(VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + + Name (_UID, 0x00) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM1 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } + + Device (NVM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + + Name (_UID, 0x01) /* _UID: Unique ID */ + + Name (_DDN, "AT24 EEPROM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status*/ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM1 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x05) + { + Package (0x02) + { + "size", + 0x0400 + }, + + Package (0x02) + { + "pagesize", + One + }, + + Package (0x02) + { + "read-only", + One + }, + + Package (0x02) + { + "address-width", + 0x08 + }, + + Package (0x02) + { + "compatible", + "atmel,24c08" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl new file mode 100644 index 0000000..48650c9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..7b38702 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..34c3d4b --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee95332..809ce6c 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -47,6 +47,7 @@ register "tcc_offset" = "20" # TCC of 85C device domain 0 on + device pci 05.0 on end # IPU - MIPI Camera device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/44939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Gerrit-Change-Number: 44939 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

10 48

Change in em100[master]: em100: Always install signal handler
by Stefan Reinauer (Code Review) 23 Oct '20

23 Oct '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/45538 ) Change subject: em100: Always install signal handler ...................................................................... em100: Always install signal handler Always catch SIGINT, because we don't want the tool to be interrupted half way through operations. This might leave the EM100Pro in a bad state that requires physically reconnecting the device. This renders the tool virtually unusable for lab setups. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I649dc491f68f764fdb1352599ff17b36e3d39fd8 --- M em100.c 1 file changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/38/45538/1 diff --git a/em100.c b/em100.c index 49d0d1e..580290a 100644 --- a/em100.c +++ b/em100.c @@ -840,6 +840,7 @@ unsigned long address_offset = 0; unsigned int spi_start_address = 0; const char *voltage = NULL; + struct sigaction signal_action; while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", longopts, &idx)) != -1) { @@ -936,6 +937,18 @@ if (desiredchip && !chip) return 1; + /* Set up signal handler. This is used for two reasons: + * 1) to create a way to cleanly exit trace mode. + * 2) to make sure that the em100 is not left in an improper state + * when receiving SIGINT for other reasons during operation. In + * this second case, we just ignore SIGINT until em100 naturally + * terminates or receives a second signal. This is OK because the + * utility is short-running in nature. + */ + signal_action.sa_handler = exit_handler; + signal_action.sa_flags = 0; + sigemptyset(&signal_action.sa_mask); + sigaction(SIGINT, &signal_action, NULL); if (em100.hwversion == HWVERSION_EM100PRO || em100.hwversion == HWVERSION_EM100PRO_EARLY) { printf("MCU version: %d.%02d\n", em100.mcu >> 8, em100.mcu & 0xff); @@ -1177,8 +1190,6 @@ } if (trace || terminal) { - struct sigaction signal_action; - if ((holdpin == NULL) && (!set_hold_pin_state(&em100, 3))) { printf("Error: Failed to set EM100 to input\n"); return 1; @@ -1200,10 +1211,6 @@ } printf(". Press CTL-C to exit.\n\n"); - signal_action.sa_handler = exit_handler; - signal_action.sa_flags = 0; - sigemptyset(&signal_action.sa_mask); - sigaction(SIGINT, &signal_action, NULL); while (!do_exit_flag) { if (trace) -- To view, visit https://review.coreboot.org/c/em100/+/45538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I649dc491f68f764fdb1352599ff17b36e3d39fd8 Gerrit-Change-Number: 45538 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code
by Hung-Te Lin (Code Review) 23 Oct '20

23 Oct '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41503 ) Change subject: mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code ...................................................................... mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code Kukui (eMCP, discrete) and Jacuzzi (discrete) are currently sharing same memory code table with only one ADC (12 levels) and we are running out of RAM IDs. Considering there may be lots of requests of adding new second source DRAM in future, we decided to increase the RAM code mapping table instead of doing model-specific table. Now both ADC 2 and 4 will be RAM code, and SKU straps will be moved from AP (ADC 2) to EC. All existing devices should have grounded both AP SKU and EC SKU (e.g., 0) so there should be no backward compatible issues. BUG=b:156691665 TEST=make; boots on Kukui BRANCH=kukui Change-Id: Ib4f4866aa26fd9ea797c1b74b6b59349f1898ccd Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41503/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 1b610ed..a2487b4 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -26,8 +26,8 @@ enum { LCM_ID_CHANNEL = 2, /* ID of LCD Module on schematics. */ - RAM_ID_CHANNEL = 3, - SKU_ID_CHANNEL = 4, + RAM_L_ID_CHANNEL = 3, /* Low 4 bits of RAM code */ + RAM_H_ID_CHANNEL = 4, /* High 4 bits of RAM code */ }; static const int ram_voltages[ADC_LEVELS] = { @@ -64,8 +64,8 @@ static const int *adc_voltages[] = { [LCM_ID_CHANNEL] = lcm_voltages, - [RAM_ID_CHANNEL] = ram_voltages, - [SKU_ID_CHANNEL] = ram_voltages, /* SKU ID is sharing RAM voltages. */ + [RAM_L_ID_CHANNEL] = ram_voltages, + [RAM_H_ID_CHANNEL] = ram_voltages, }; static uint32_t get_adc_index(unsigned int channel) @@ -101,7 +101,7 @@ return cached_sku_id; } - /* Quirk for Kukui: All Rev1/Sku0 had incorrectly set SKU_ID=1. */ + /* Quirk for Kukui: All Rev1/Sku0 had incorrectly set SKU ID=1. */ if (CONFIG(BOARD_GOOGLE_KUKUI)) { if (board_id() == 1) { cached_sku_id = 0; @@ -112,10 +112,10 @@ /* * The SKU (later used for device tree matching) is combined from: * ADC2[4bit/H] = straps on LCD module (type of panel). - * ADC4[4bit/L] = SKU ID from board straps. + * EC [4bit/L] = straps on EC SKU ID straps. */ cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | - get_adc_index(SKU_ID_CHANNEL)); + google_chromeec_get_sku_id()); return cached_sku_id; } @@ -124,6 +124,7 @@ static uint32_t cached_ram_code = BOARD_ID_INIT; if (cached_ram_code == BOARD_ID_INIT) - cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + cached_ram_code = (get_adc_index(RAM_H_ID_CHANNEL) << 4 | + get_adc_index(RAM_L_ID_CHANNEL)); return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4f4866aa26fd9ea797c1b74b6b59349f1898ccd Gerrit-Change-Number: 41503 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in em100[master]: Update to use upstream version 4.3.10
by Stefan Reinauer (Code Review) 23 Oct '20

23 Oct '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/45537 ) Change subject: Update to use upstream version 4.3.10 ...................................................................... Update to use upstream version 4.3.10 Upstream 4.3.10 is using a different download slot, adjusting the makechips.sh script. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I740885e4773dcbd236d1a645e03b6896bf39c0d1 --- M makechips.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/37/45537/1 diff --git a/makechips.sh b/makechips.sh index fcf0070..8a2d901 100755 --- a/makechips.sh +++ b/makechips.sh @@ -12,7 +12,7 @@ # GNU General Public License for more details. # -URL="https://www.dediprog.com/download/save/78.msi" +URL="https://www.dediprog.com/download/save/1145.msi" VURL="https://www.dediprog.com/download?productCategory=SPI+Flash+Solution&produc…" if ! which curl > /dev/null; then -- To view, visit https://review.coreboot.org/c/em100/+/45537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I740885e4773dcbd236d1a645e03b6896bf39c0d1 Gerrit-Change-Number: 45537 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: [TEST] util/abuild: Redirect output back to /dev/null
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45605 ) Change subject: [TEST] util/abuild: Redirect output back to /dev/null ...................................................................... [TEST] util/abuild: Redirect output back to /dev/null Commit 0d431ac removed the redirection. Try adding it back again. Change-Id: I872118b7dd68d5cf3bdaba0413287f41844cef3c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45605/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 7561495..538b7d3 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -821,7 +821,7 @@ printf "%s" "$configoptions" > "$TMPCFG" $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" allnoconfig printf "%s" "$configoptions" >> "$TMPCFG" - yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig + yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig > /dev/null 2>&1 BUILDPREFIX= if [ "$scanbuild" = "true" ]; then scanbuild_out=$TARGET/sharedutils-scanbuild -- To view, visit https://review.coreboot.org/c/coreboot/+/45605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872118b7dd68d5cf3bdaba0413287f41844cef3c Gerrit-Change-Number: 45605 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/lynxpoint: Use `config_of` where possible
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45714 ) Change subject: sb/intel/lynxpoint: Use `config_of` where possible ...................................................................... sb/intel/lynxpoint: Use `config_of` where possible This eliminates the need to perform null-checking. Change-Id: I88f7867d2b446a20a80417cd3758bd5406165fca Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45714/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fad83b1..dc16c37 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -174,7 +174,7 @@ u32 reg32; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -636,7 +636,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3e1f63b..4dd383b 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -145,12 +145,8 @@ rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - if (dev->chip_info != NULL) { - struct southbridge_intel_lynxpoint_config *config; - - config = dev->chip_info; - rpc.coalesce = config->pcie_port_coalesce; - } + struct southbridge_intel_lynxpoint_config *config = config_of(dev); + rpc.coalesce = config->pcie_port_coalesce; } rp = root_port_number(dev); @@ -501,7 +497,7 @@ static void pch_pcie_early(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct southbridge_intel_lynxpoint_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); int is_lp = pch_is_lp(); @@ -559,7 +555,7 @@ } /* Allow ASPM to be forced on in devicetree */ - if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) + if ((config->pcie_port_force_aspm & (1 << (rp - 1)))) do_aspm = 1; printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/45714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f7867d2b446a20a80417cd3758bd5406165fca Gerrit-Change-Number: 45714 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Align with Elkhart Lake
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45779 ) Change subject: soc/intel/jasperlake: Align with Elkhart Lake ...................................................................... soc/intel/jasperlake: Align with Elkhart Lake Change-Id: I4ac041081a0c7b97ee7069b7893bd9c1f3d340d4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/meminit.h M src/soc/intel/jasperlake/me.c M src/soc/intel/jasperlake/p2sb.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/jasperlake/reset.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/jasperlake/systemagent.c 13 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45779/1 diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8673da1..08f44b4 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -3,16 +3,16 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> -#include <device/device.h> -#include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 3a50929..382bbf7 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -2,12 +2,12 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> +#include <device/pci.h> #include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 235dc6e..c88efc8 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -2,11 +2,11 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067..ab3e42f 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <arch/ioapic.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> @@ -67,7 +67,7 @@ static void pch_enable_ioapic(const struct device *dev) { - u32 reg32; + uint32_t reg32; /* PCH-LP has 120 redirection entries */ const int redir_entries = 120; @@ -126,7 +126,7 @@ itss_irq_init(pch_interrupt_routing); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; + uint8_t int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..0916436 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> -#include <device/mmio.h> #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> +#include <device/mmio.h> #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> diff --git a/src/soc/intel/jasperlake/include/soc/meminit.h b/src/soc/intel/jasperlake/include/soc/meminit.h index 5ba3e69..f3555ac 100644 --- a/src/soc/intel/jasperlake/include/soc/meminit.h +++ b/src/soc/intel/jasperlake/include/soc/meminit.h @@ -3,8 +3,8 @@ #ifndef _SOC_JASPERLAKE_MEMINIT_H_ #define _SOC_JASPERLAKE_MEMINIT_H_ -#include <types.h> #include <fsp/soc_binding.h> +#include <types.h> /* Number of dq bits controlled per dqs */ #define DQ_BITS_PER_DQS 8 diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index b40b4dc..d00702e 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> -#include <intelblocks/cse.h> #include <console/console.h> +#include <intelblocks/cse.h> #include <soc/me.h> static void dump_me_status(void *unused) diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c index 169cde6..0ddd007 100644 --- a/src/soc/intel/jasperlake/p2sb.c +++ b/src/soc/intel/jasperlake/p2sb.c @@ -13,7 +13,7 @@ } /* Remove the host accessing right to PSF register range. - * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable sideband * access for PCI Root Bridge. */ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index ed6a31d..a3564b6 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -2,8 +2,8 @@ #include <bootstate.h> #include <console/console.h> -#include <device/mmio.h> #include <device/device.h> +#include <device/mmio.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index ebe46b1..69282ee 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -7,15 +7,16 @@ #define __SIMPLE_DEVICE__ -#include <device/mmio.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_def.h> -#include <console/console.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> +#include <security/vboot/vbnv.h> #include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -24,7 +25,6 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> -#include <security/vboot/vbnv.h> /* * SMI diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index 1f7ea3c..fe3d769 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -2,9 +2,9 @@ #include <cf9_reset.h> #include <console/console.h> +#include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> -#include <fsp/util.h> #include <soc/intel/common/reset.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index bbdcb68..11b631b 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -1,22 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> #include <smp/node.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <string.h> +#include <types.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 080446c..73f7963 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/device.h> #include <delay.h> +#include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <intelblocks/systemagent.h> #include <intelblocks/power_limit.h> +#include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ac041081a0c7b97ee7069b7893bd9c1f3d340d4 Gerrit-Change-Number: 45779 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Only hide PEG devices if ONBOARD_VGA_IS_PRIMARY
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45534 ) Change subject: nb/intel/haswell: Only hide PEG devices if ONBOARD_VGA_IS_PRIMARY ...................................................................... nb/intel/haswell: Only hide PEG devices if ONBOARD_VGA_IS_PRIMARY The MRC will perform PCI enumeration, and if it detects a VGA device in a PEG slot, it will disable the IGD and not reserve any memory for it. Since the memory map is locked by the time MRC finishes, the IGD can't be enabled afterwards. Wonderful. If we are supposed to enable the onboard VGA as primary, hide all PEG devices during MRC execution. This will trick the MRC into thinking there aren't any, and will enable the IGD. Note that PEG AFE settings will not be programmed, which may cause stability problems at higher PCIe link speeds. The most ideal way to fix this problem for good is to implement native init. Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/early_init.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45534/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..d3d511e 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -84,13 +84,24 @@ printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); /* - * Hide the PEG device while the MRC runs. This is because the MRC makes - * configurations that are not ideal if it sees a VGA device in a PEG slot, - * and it locks registers preventing changes to these configurations. + * The MRC will perform PCI enumeration, and if it detects a VGA + * device in a PEG slot, it will disable the IGD and not reserve + * any memory for it. Since the memory map is locked by the time + * MRC finishes, the IGD can't be enabled afterwards. Wonderful. + * + * If we are supposed to enable the onboard VGA as primary, hide + * all PEG devices during MRC execution. This will trick the MRC + * into thinking there aren't any, and will enable the IGD. Note + * that PEG AFE settings will not be programmed, which may cause + * stability problems at higher PCIe link speeds. The most ideal + * way to fix this problem for good is to implement native init. */ - pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); - peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; - printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); + if (CONFIG(ONBOARD_VGA_IS_PRIMARY)) { + pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); + peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; + printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", + PCI_FUNC(PCI_DEV2DEVFN(dev))); + } } void haswell_unhide_peg(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/45534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0 Gerrit-Change-Number: 45534 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] console/init: Drop get_console_loglevel() API
by Nico Huber (Code Review) 23 Oct '20

23 Oct '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45771 to review the following change. Change subject: [RFC] console/init: Drop get_console_loglevel() API ...................................................................... [RFC] console/init: Drop get_console_loglevel() API It's not used anymore. We keep the CONSOLE_OVERRIDE_LOGLEVEL Kconfig, though, as it provides some user Kconfig comfort (we can hide unneces- sary prompts). Change-Id: Id6dd54534267c5419cbe81ee4b66f7b753a6e6cf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/console/init.c M src/include/console/console.h 3 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45771/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index bad6c56..57b932d 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -312,8 +312,9 @@ config CONSOLE_OVERRIDE_LOGLEVEL bool help - Set to "y" when the platform overrides the loglevel by providing - a get_console_loglevel routine. + Set to "y" when the platform unconditionally overrides the + loglevel default. Then we don't need to present the choice + below. if !CONSOLE_OVERRIDE_LOGLEVEL diff --git a/src/console/init.c b/src/console/init.c index 9776e2a..2be2e5a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -21,7 +21,7 @@ static void init_log_level(void) { - int debug_level = get_console_loglevel(); + int debug_level = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; get_option(&debug_level, "debug_level"); diff --git a/src/include/console/console.h b/src/include/console/console.h index a96eb15..bb19cb7 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -49,18 +49,6 @@ enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; -#if CONFIG(CONSOLE_OVERRIDE_LOGLEVEL) -/* - * This function should be implemented at mainboard level. - * The returned value will _replace_ the loglevel value; - */ -int get_console_loglevel(void); -#else -static inline int get_console_loglevel(void) -{ - return CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -} -#endif #else static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6dd54534267c5419cbe81ee4b66f7b753a6e6cf Gerrit-Change-Number: 45771 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] mb/scaleway: Use mainboard_get_option() API
by Nico Huber (Code Review) 23 Oct '20

23 Oct '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45770 to review the following change. Change subject: [RFC] mb/scaleway: Use mainboard_get_option() API ...................................................................... [RFC] mb/scaleway: Use mainboard_get_option() API Change-Id: I1acb11d76fd7620001f84b2c3331820dcaab8875 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/scaleway/tagada/Kconfig M src/mainboard/scaleway/tagada/bmcinfo.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45770/1 diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index cbbb6ae..ab51b1e 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -8,6 +8,7 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select CONSOLE_OVERRIDE_LOGLEVEL + select USE_MAINBOARD_OPTIONS select UART_OVERRIDE_BAUDRATE config MAINBOARD_DIR diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 099d37e..982c09c 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> +#include <string.h> #include <console/console.h> #include <console/uart.h> +#include <option.h> #include "bmcinfo.h" @@ -172,10 +174,13 @@ return 115200; } -#if __CONSOLE_ENABLE__ /* Override default console loglevel */ -int get_console_loglevel(void) +enum cb_err mainboard_get_option(void *const dest, const char *const name) { - return bmcinfo_coreboot_verbosity_level(); + if (strcmp(name, "debug_level") == 0) { + *(char *)dest = bmcinfo_coreboot_verbosity_level(); + return CB_SUCCESS; + } + + return CB_CMOS_OPTION_NOT_FOUND; } -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1acb11d76fd7620001f84b2c3331820dcaab8875 Gerrit-Change-Number: 45770 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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