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Change in coreboot[master]: broadwell: update processor power limits configuration
by Sumeet R Pawnikar (Code Review) 25 Oct '20

25 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41234 ) Change subject: broadwell: update processor power limits configuration ...................................................................... broadwell: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Broadwell SoC based platforms. BRANCH=None BUG=None TEST=Build for broadwell based platform Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/msr.h A src/soc/intel/broadwell/include/soc/soc_chip.h M src/soc/intel/broadwell/systemagent.c 8 files changed, 33 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41234/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 20219d3..67f7563 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER @@ -34,10 +35,12 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT - select CPU_INTEL_COMMON select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 8afdba1..e44a1a1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -25,6 +25,7 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> +#include <intelblocks/cpulib.h> /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 7351d70..c8df32d 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -5,6 +5,7 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include <drivers/intel/gma/i915.h> +#include <intelblocks/cfg.h> #include <stdint.h> struct soc_intel_broadwell_config { diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 35df1b5..f5ec878 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -17,6 +17,7 @@ #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <intelblocks/cpulib.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -26,64 +27,6 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ @@ -289,90 +232,6 @@ RCBA32(PMSYNC_CONFIG2) = pmsync2; } -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on server SKU */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 93d8a01..90ea613 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -38,10 +38,6 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 7328f19..ab97b90 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -4,6 +4,8 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ +#include <intelblocks/msr.h> + #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -46,14 +48,6 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h new file mode 100644 index 0000000..ff77168 --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/soc_chip.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BROADWELL_SOC_CHIP_H_ +#define _SOC_BROADWELL_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index ac1008b..5adb731 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -405,6 +406,7 @@ static void systemagent_init(struct device *dev) { + struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -424,7 +426,8 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); } static struct device_operations systemagent_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Gerrit-Change-Number: 41234 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/broadwell: Use get_{pmbase,gpiobase}
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45717 ) Change subject: soc/intel/broadwell: Use get_{pmbase,gpiobase} ...................................................................... soc/intel/broadwell: Use get_{pmbase,gpiobase} This is to align Broadwell and Lynx Point. Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/smihandler.c 2 files changed, 47 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45717/1 diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index c96ed18..e63a981 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -19,6 +19,12 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <security/vboot/vbnv.h> +#include <stdint.h> + +static inline uint16_t get_gpiobase(void) +{ + return GPIO_BASE_ADDRESS; +} /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -59,17 +65,17 @@ /* Enable events in PM1 control register */ void enable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt |= mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* Disable events in PM1 control register */ void disable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* @@ -79,8 +85,8 @@ /* Clear and return PM1 status register */ static u16 reset_pm1_status(void) { - u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); + u16 pm1_sts = inw(get_pmbase() + PM1_STS); + outw(pm1_sts, get_pmbase() + PM1_STS); return pm1_sts; } @@ -117,7 +123,7 @@ /* Set the PM1 register to events */ void enable_pm1(u16 events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + outw(events, get_pmbase() + PM1_EN); } /* @@ -127,8 +133,8 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); + u32 smi_sts = inl(get_pmbase() + SMI_STS); + outl(smi_sts, get_pmbase() + SMI_STS); return smi_sts; } @@ -177,17 +183,17 @@ /* Enable SMI event */ void enable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* Disable SMI event */ void disable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* @@ -200,9 +206,9 @@ u32 alt_sts, alt_en; /* Low Power variant moves this to GPIO region as dword */ - alt_sts = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); /* Only report enabled events */ return alt_sts & alt_en; @@ -235,9 +241,9 @@ { u32 alt_en; - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); alt_en |= mask; - outl(alt_en, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); } /* @@ -247,9 +253,9 @@ /* Clear TCO status and return events that are enabled and active */ static u32 reset_tco_status(void) { - u32 tcobase = ACPI_BASE_ADDRESS + 0x60; + u32 tcobase = get_pmbase() + 0x60; u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(ACPI_BASE_ADDRESS + 0x68); + u32 tco_en = inl(get_pmbase() + 0x68); /* Don't clear BOOT_STS before SECOND_TO_STS */ outl(tco_sts & ~(1 << 18), tcobase + 0x04); @@ -301,7 +307,7 @@ void enable_tco_sci(void) { /* Clear pending events */ - outl(ACPI_BASE_ADDRESS + GPE0_STS(3), TCOSCI_STS); + outl(get_pmbase() + GPE0_STS(3), TCOSCI_STS); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); @@ -314,10 +320,10 @@ /* Clear a GPE0 status and return events that are enabled and active */ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { - u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); + u32 gpe0_sts = inl(get_pmbase() + sts_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg); - outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg); + outl(gpe0_sts, get_pmbase() + sts_reg); /* Only report enabled events */ return gpe0_sts & gpe0_en; @@ -376,10 +382,12 @@ /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { - outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); - outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); - outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); - outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u16 pmbase = get_pmbase(); + + outl(set1, pmbase + GPE0_EN(GPE_31_0)); + outl(set2, pmbase + GPE0_EN(GPE_63_32)); + outl(set3, pmbase + GPE0_EN(GPE_94_64)); + outl(set4, pmbase + GPE0_EN(GPE_STD)); } /* Disable all GPE */ @@ -391,17 +399,17 @@ /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } int acpi_sci_irq(void) @@ -434,10 +442,10 @@ int platform_is_resuming(void) { - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; } /* STM Support */ diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 4a12d78..fd5d452 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -133,6 +133,7 @@ u32 reg32; u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; + u16 pmbase = get_pmbase(); /* save and recover RTC port values */ u8 tmp70, tmp72; @@ -146,7 +147,7 @@ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -225,7 +226,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -393,7 +394,7 @@ static void southbridge_smi_mc(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -436,7 +437,7 @@ static void southbridge_smi_periodic(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Gerrit-Change-Number: 45717 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Clean up header handling
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45452 ) Change subject: nb/intel/gm45: Clean up header handling ...................................................................... nb/intel/gm45: Clean up header handling There's no need to have ACPI guards in `gm45.h`, since the only things the ASL files require are the base address definitions in `memmap.h`. Also, remove the southbridge include from `gm45.h` and place it only in the files that actually require something from it. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c 4 files changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45452/1 diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..e4d8d66 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../gm45.h" +#include "../memmap.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e362841..86f71d6 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -2,6 +2,7 @@ #include <stdint.h> #include <device/pci_ops.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index cad0596..7c4b22b 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include <southbridge/intel/i82801ix/i82801ix.h> - -#ifndef __ACPI__ - #include <stdint.h> typedef enum { @@ -163,8 +159,6 @@ VCO_5333 = 2, }; -#endif - /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ @@ -345,8 +339,6 @@ #include "registers/epbar.h" -#ifndef __ACPI__ - void gm45_early_init(void); void gm45_early_reset(void); @@ -396,5 +388,4 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 9d30c5b..6472a29 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Gerrit-Change-Number: 45452 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/gm45: Introduce memmap.h
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45451 ) Change subject: nb/intel/gm45: Introduce memmap.h ...................................................................... nb/intel/gm45: Introduce memmap.h Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/memmap.h 2 files changed, 17 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45451/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 061bf2d..cad0596 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -170,16 +170,7 @@ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ - -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 - - -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#include "memmap.h" /* * D0:F0 diff --git a/src/northbridge/intel/gm45/memmap.h b/src/northbridge/intel/gm45/memmap.h new file mode 100644 index 0000000..b778f2d --- /dev/null +++ b/src/northbridge/intel/gm45/memmap.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ + +#define DEFAULT_MCHBAR 0xfed14000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 + + +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 + +#endif /* __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Gerrit-Change-Number: 45451 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: nb/intel/gm45: Add more DMIBAR/EPBAR registers
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45448 ) Change subject: nb/intel/gm45: Add more DMIBAR/EPBAR registers ...................................................................... nb/intel/gm45: Add more DMIBAR/EPBAR registers Add definitions for more DMIBAR/EPBAR registers, and specify their sizes as well. Also, expand a comment as the registers' purpose is now known. On loops that poll these registers, move the semicolon to a new line. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/raminit.c 3 files changed, 78 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45448/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 91e6326..31c6984 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -361,15 +361,29 @@ #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ /* * EPBAR @@ -379,11 +393,30 @@ #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index c82e1d6..9d30c5b 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -10,34 +10,36 @@ static void init_egress(void) { /* VC0: TC0 only */ - EPBAR8(0x14) &= 1; - EPBAR8(0x4) = (EPBAR8(0x4) & ~7) | 1; + EPBAR8(EPVC0RCTL) &= 1; + EPBAR8(EPPVCCAP1) = (EPBAR8(EPPVCCAP1) & ~7) | 1; /* VC1: isoch */ - EPBAR32(0x28) = 0x0a0a0a0a; - EPBAR32(0x1c) = (EPBAR32(0x1c) & ~(127 << 16)) | (0x0a << 16); + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~(127 << 16)) | (0x0a << 16); /* VC1: ID1, TC7 */ - EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); - EPBAR8(0x20) = (EPBAR8(0x20) & 1) | (1 << 7); + EPBAR32(EPVC1RCTL) = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); + EPBAR8(EPVC1RCTL) = (EPBAR8(EPVC1RCTL) & 1) | (1 << 7); /* VC1 ARB table: setup and enable */ - EPBAR32(0x100) = 0x55555555; - EPBAR32(0x104) = 0x55555555; - EPBAR32(0x108) = 0x55555555; - EPBAR32(0x10c) = 0x55555555; - EPBAR32(0x110) = 0x55555555; - EPBAR32(0x114) = 0x55555555; - EPBAR32(0x118) = 0x55555555; - EPBAR32(0x11c) = 0x00005555; - EPBAR32(0x20) |= 1 << 16; + EPBAR32(EP_PORTARB(0)) = 0x55555555; + EPBAR32(EP_PORTARB(1)) = 0x55555555; + EPBAR32(EP_PORTARB(2)) = 0x55555555; + EPBAR32(EP_PORTARB(3)) = 0x55555555; + EPBAR32(EP_PORTARB(4)) = 0x55555555; + EPBAR32(EP_PORTARB(5)) = 0x55555555; + EPBAR32(EP_PORTARB(6)) = 0x55555555; + EPBAR32(EP_PORTARB(7)) = 0x00005555; + EPBAR32(EPVC1RCTL) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0); + while ((EPBAR8(EPVC1RSTS) & 1) != 0) + ; /* VC1: enable */ - EPBAR32(0x20) |= 1 << 31; + EPBAR32(EPVC1RCTL) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0); + while ((EPBAR8(EPVC1RSTS) & 2) != 0) + ; } /* MCH side */ @@ -46,16 +48,17 @@ { /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) &= 1; - DMIBAR8(0x4) = (DMIBAR8(0x4) & ~7) | 1; + DMIBAR8(DMIPVCCAP1) = (DMIBAR8(DMIPVCCAP1) & ~7) | 1; /* VC1: ID1, TC7 */ - DMIBAR32(0x20) = (DMIBAR32(0x20) & ~(7 << 24)) | (1 << 24); - DMIBAR8(0x20) = (DMIBAR8(0x20) & 1) | (1 << 7); + DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); + DMIBAR8(DMIVC1RCTL) = (DMIBAR8(DMIVC1RCTL) & 1) | (1 << 7); /* VC1: enable */ - DMIBAR32(0x20) |= 1 << 31; + DMIBAR32(DMIVC1RCTL) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0); + while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0) + ; /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; @@ -224,11 +227,11 @@ the endpoint (ICH), but ICH doesn't give any limits. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) - DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once) + DMIBAR8(DMILCTL) |= (3 << 0); // enable ASPM L0s, L1 (write-once) else - DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once) + DMIBAR8(DMILCTL) |= (1 << 0); // enable ASPM L0s (write-once) /* timing */ - DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15); + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~(63 << 12)) | (2 << 12) | (2 << 15); DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b95e563..5975b80 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1130,7 +1130,7 @@ } } -/* Program egress VC1 timings. */ +/* Program egress VC1 isoch timings. */ static void vc1_program_timings(const fsb_clock_t fsb) { const u32 timings_by_fsb[][2] = { @@ -1138,9 +1138,9 @@ /* FSB 800MHz */ { 0x14, 0x00f000f0 }, /* FSB 667MHz */ { 0x10, 0x00c000c0 }, }; - EPBAR8(0x2c) = timings_by_fsb[fsb][0]; - EPBAR32(0x38) = timings_by_fsb[fsb][1]; - EPBAR32(0x3c) = timings_by_fsb[fsb][1]; + EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0]; + EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1]; + EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1]; } #define DEFAULT_PCI_MMIO_SIZE 2048 -- To view, visit https://review.coreboot.org/c/coreboot/+/45448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Gerrit-Change-Number: 45448 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: nb/intel/ironlake: Add more host bridge PCI IDs
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45562 ) Change subject: nb/intel/ironlake: Add more host bridge PCI IDs ...................................................................... nb/intel/ironlake: Add more host bridge PCI IDs The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. The current coreboot code seems to be able to change the device ID of the host bridge, but it seems to be missing a warm reset so that the device ID changes. Account for the 'mysterious' device IDs in the northbridge driver, so that booting an OS has a chance to work. Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45562/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index cf014fe..e0e926e 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -202,10 +202,34 @@ .ops_pci = &pci_dev_ops_pci, }; +/* + * The host bridge PCI device ID can be changed by the firmware. There + * is no documentation about it, though. There's 'official' IDs, which + * appear in spec updates and Windows drivers, and 'mysterious' IDs, + * which Intel doesn't want OSes to know about and thus are not listed. + * + * The current coreboot code seems to be able to change the device ID + * of the host bridge, but it seems to be missing a warm reset so that + * the device ID changes. Account for the 'mysterious' device IDs in + * the northbridge driver, so that booting an OS has a chance to work. + */ +static const unsigned short pci_device_ids[] = { + /* 'Official' DIDs */ + 0x0040, /* Clarkdale */ + 0x0044, /* Arrandale */ + 0x0048, /* Unknown, but it appears in OS drivers and raminit */ + + /* Mysterious DIDs, taken from Linux' intel-agp driver */ + 0x0062, /* Clarkdale A-? */ + 0x0069, /* Clarkdale K-0 */ + 0x006a, /* Arrandale K-0 */ + 0 +}; + static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Arrandale DRAM controller */ + .device = pci_device_ids, }; static struct device_operations cpu_bus_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Gerrit-Change-Number: 45562 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: haswell: Set up Root Complex topology
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43744 ) Change subject: haswell: Set up Root Complex topology ...................................................................... haswell: Set up Root Complex topology System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it. Tested on Asrock B85M Pro4, still boots. Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index baa4f32..e6dfe3a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -91,6 +91,11 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0) +/* Device 0:1.0 PCI configuration space (PCIe Graphics Attach) */ +#define PEG_DCAP2 0xc4 /* 32bit */ +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -144,6 +149,10 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */ #define PORTARB 0x100 /* 256bit */ @@ -169,6 +178,8 @@ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define DMIESD 0x044 /* 32bit */ + #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ #define DMILE2D 0x060 /* 32bit */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4311710..25ed828 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -453,12 +453,80 @@ DMIBAR8(0xd34) = 0x44; } +static void northbridge_topology_init(void) +{ + struct device *dev; + + /* Set the CID1 EP Port Root Topology */ + EPBAR32(EPESD) = (1 << 16); + + EPBAR32(EPLE1D) = (1 << 16) | 1; + EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + dev = pcidev_on_root(1, 0); + if (dev && dev->enabled) { + + EPBAR32(EPLE2A) = 0x8000; + EPBAR32(EPLE2D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 1); + if (dev && dev->enabled) { + + EPBAR32(EPLE3A) = 0x9000; + EPBAR32(EPLE3D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 2); + if (dev && dev->enabled) { + + EPBAR32(EPLE4A) = 0xa000; + EPBAR32(EPLE4D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + DMIBAR32(DMIESD) = (1 << 16) | 1; + + DMIBAR32(DMILE1D) = (2 << 16) | 1; + DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR32(DMILE2D) = (1 << 16) | 1; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; - if (!CONFIG(INTEL_LYNXPOINT_LP)) + if (!CONFIG(INTEL_LYNXPOINT_LP)) { northbridge_dmi_init(); + northbridge_topology_init(); + } /* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b0..85fab4d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -19,6 +19,7 @@ #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> +#include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> @@ -500,6 +501,18 @@ RCBA32_OR(0x21a8, 0x3); } +static void pch_topology_init(void) +{ + /* Set component id to 2 for southbridge, northbridge has id 1 */ + RCBA32(ESD) = (2 << 16); + + /* Set target port number and target component id of the northbridge */ + RCBA32(ULD) = (1 << 24) | (1 << 16); + + /* Set target RCRB base address, i.e. DMIBAR */ + RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -546,6 +559,8 @@ pch_set_acpi_mode(); pch_fixups(dev); + + pch_topology_init(); } static void pch_lpc_add_mmio_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/43744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Gerrit-Change-Number: 43744 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 24

Change in coreboot[master]: sb/intel/lynxpoint/pcie.c: Fix subtle blunder
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45713 ) Change subject: sb/intel/lynxpoint/pcie.c: Fix subtle blunder ...................................................................... sb/intel/lynxpoint/pcie.c: Fix subtle blunder If only C had a decent type system... Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45713/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 5e69fca..3e1f63b 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -283,8 +283,7 @@ /* Update PECR1 register. */ pci_or_config8(dev, 0xe8, 1); - /* FIXME: Are we supposed to update this register with a constant boolean? */ - pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_or_config8(dev, 0x324, 1 << 5); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Gerrit-Change-Number: 45713 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: mb/google/volteer: Add settings for noise mitgation
by Shaunak Saha (Code Review) 24 Oct '20

24 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45053 ) Change subject: mb/google/volteer: Add settings for noise mitgation ...................................................................... mb/google/volteer: Add settings for noise mitgation Enable acoustic noise mitgation for volteer platform. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45053/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ffae2f0..5e33f41 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -232,6 +232,17 @@ register "tcc_offset" = "10" # TCC of 90 + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[0]" = "2" + register "SlowSlewRate[1]" = "2" + register "SlowSlewRate[2]" = "2" + register "SlowSlewRate[3]" = "2" + register "FastPkgCRampDisable[0]" = "1" + register "FastPkgCRampDisable[1]" = "1" + register "FastPkgCRampDisable[2]" = "1" + register "FastPkgCRampDisable[3]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/45053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 Gerrit-Change-Number: 45053 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/intel/tigerlake: Add Acoustic features
by Shaunak Saha (Code Review) 24 Oct '20

24 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45052 ) Change subject: soc/intel/tigerlake: Add Acoustic features ...................................................................... soc/intel/tigerlake: Add Acoustic features Expose the following FSP UPD interface into coreboot, which is the following: AcousticNoiseMitigation FastPkgCRampDisable SlowSlewRateFor AcousticNoiseMitigation is the UPD for Acoustic Noise Mitigation. FastPkgCRampDisable UPD's are to disable Fast Slew Rate for Deep Package C States for VR domains. SlowSlewRate UPD's are the Slew Rate configuration for Deep Package C States for VR domains. Slew rates are fast time divided by 2. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45052/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2da63ed..8d2483e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -145,6 +145,35 @@ /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* + * Acoustic Noise Mitigation + * 0 - Disable + * 1 - Enable noise mitigation + */ + uint8_t AcousticNoiseMitigation; + + /* + * Offset 0x054B - Disable Fast Slew Rate for Deep Package + * C States for VR domains. Disable Fast Slew Rate for Deep + * Package C States based on Acoustic Noise Mitigation feature + * enabled. + * 0 - False + * 1 - True + */ + uint8_t FastPkgCRampDisable[5]; + + /* + * Offset 0x0550 - Slew Rate configuration for Deep Package + * C States for VR domains. Slew Rate configuration for Deep + * Package C States for VR domains based on Acoustic Noise + * Mitigation feature enabled. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ + uint8_t SlowSlewRate[5]; + /* SATA related */ uint8_t SataEnable; uint8_t SataMode; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1601c2c..39baa67 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -247,6 +247,13 @@ } } + params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + for (i = 0; i < ARRAY_SIZE(config->SlowSlewRate); i++) + params->SlowSlewRate[i] = config->SlowSlewRate[i]; + + for (i = 0; i < ARRAY_SIZE(config->FastPkgCRampDisable); i++) + params->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; + /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/45052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Gerrit-Change-Number: 45052 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020