coreboot-gerrit September 2020

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Change in coreboot[master]: [RFC] Introduce mainboard_get_option()
by Nico Huber (Code Review) 23 Oct '20

23 Oct '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45769 to review the following change. Change subject: [RFC] Introduce mainboard_get_option() ...................................................................... [RFC] Introduce mainboard_get_option() Add a cmos_get_option() equivalent that queries mainboard-specific code for option values. CMOS option values take precedence over mainboard options. Change-Id: I3ff055875c50b8bf097acd58eeb001d5b91a5dcd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/Kconfig M src/include/option.h 2 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45769/1 diff --git a/src/Kconfig b/src/Kconfig index e46a6e6..40310bb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -135,6 +135,13 @@ every boot. Use this if you want the NVRAM configuration to never be modified from its default values. +config USE_MAINBOARD_OPTIONS + bool + help + Allows mainboard code to implement a mainboard_get_option() for + querying configuration values. CMOS option values take precedence + over mainboard options. + config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" depends on HAVE_RAMSTAGE diff --git a/src/include/option.h b/src/include/option.h index 6b4e6a9..86c8ff1 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -10,6 +10,8 @@ enum cb_err cmos_set_option(const char *name, void *val); enum cb_err cmos_get_option(void *dest, const char *name); +enum cb_err mainboard_get_option(void *dest, const char *name); + static inline enum cb_err set_option(const char *name, void *val) { if (CONFIG(USE_OPTION_TABLE)) @@ -20,10 +22,14 @@ static inline enum cb_err get_option(void *dest, const char *name) { - if (CONFIG(USE_OPTION_TABLE)) - return cmos_get_option(dest, name); + enum cb_err ret = CB_CMOS_OTABLE_DISABLED; - return CB_CMOS_OTABLE_DISABLED; + if (CONFIG(USE_OPTION_TABLE)) + ret = cmos_get_option(dest, name); + if (CONFIG(USE_MAINBOARD_OPTIONS) && ret != CB_SUCCESS) + ret = mainboard_get_option(dest, name); + + return ret; } #endif /* _OPTION_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff055875c50b8bf097acd58eeb001d5b91a5dcd Gerrit-Change-Number: 45769 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c
by Marc Jones (Code Review) 23 Oct '20

23 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45850 ) Change subject: soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c ...................................................................... soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c De-duplicate and prepare for common ACPI. Move common northbridge ACPI code to nb_acpi.c. There are a few differences between the skx and cpx FSP defined names that are managed with #if (CONFIG(SOC_INTEL_*_SP)). Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/soc_acpi.c A src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 4 files changed, 524 insertions(+), 935 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45850/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 3bbf6b7..8a26c14 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 63f82ae..ddc71c7d 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -255,471 +255,3 @@ return current; } - -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - unsigned int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; - - memory_map = get_system_memory_map(); - assert(memory_map != NULL); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - unsigned int nodes = xeon_sp_get_socket_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8 + nodes * nodes; - return current; -} - -/* - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACK0 stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int p) -{ - if (p == 0) - return CSTACK; - else if (p >= PORT_1A && p <= PORT_1D) - return PSTACK0; - else if (p >= PORT_2A && p <= PORT_2D) - return PSTACK1; - else //if (p >= PORT_3A && p <= PORT_3D) - return PSTACK2; -} - -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) -{ - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - - uint32_t enum_id; - unsigned long tmp = current; - - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - uint32_t reg_base = - hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); - - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - - // Add PCH IOAPIC - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - } - - // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); - - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } - - // Add PCIe Ports - if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, - bus, dev, func); - } - - // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } - } - - // Add HPET - if (socket == 0 && stack == CSTACK) { - uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count - printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", - __func__, hpet_capid, num_hpets); - //BIT 15 - if (num_hpets && (num_hpets != 0x1f) && - (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { - printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); - } - } - - acpi_dmar_drhd_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_atsr(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - unsigned long tmp = current; - bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " - "vtd_mmio_cap: 0x%llx\n", - __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); - - // ATSR is applicable only for platform supporting device IOTLBs - // through the VT-d extended capability register - assert(vtd_mmio_cap != 0xffffffffffffffff); - if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 - continue; - - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (socket == 0 && p == 0) - continue; - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - if (first) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", - 0, pcie_seg); - current += acpi_create_dmar_atsr(current, 0, pcie_seg); - first = 0; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); - } - } - if (tmp != current) - acpi_dmar_atsr_fixup(tmp, current); - } - - return current; -} - -static unsigned long acpi_create_rmrr(unsigned long current) -{ - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_rhsa(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " - "Proximity Domain: 0x%x\n", vtd_base, socket); - current += acpi_create_dmar_rhsa(current, vtd_base, socket); - } - } - - return current; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - // DRHD - for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { - int socket = iio; - if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry - socket = 0; - - if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); - } else { - for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - } - } - - // RMRR - current = acpi_create_rmrr(current); - - // ATSR - causes hang - current = acpi_create_atsr(current); - - // RHSA - current = acpi_create_rhsa(current); - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_dmar_t *dmar; - - const struct soc_intel_xeon_sp_config *const config = config_of(device); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* DMAR */ - if (config->vtd_support) { - current = ALIGN(current, 8); - dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", - (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); - acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - } - - return current; -} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c new file mode 100644 index 0000000..e54e412 --- /dev/null +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <assert.h> +#include <cbmem.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <intelblocks/acpi.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/soc_util.h> + +#include "chip.h" + +/* Northbridge(NUMA) ACPI table generation. SRAT, SLIT, etc */ + +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + unsigned int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + unsigned int mmap_index; + + memory_map = get_system_memory_map(); + assert(memory_map != NULL); + printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + unsigned int nodes = xeon_sp_get_socket_count(); +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + int nodes = get_cpu_count(); +#endif /* SOC_INTEL_SKYLAKE_SP */ + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8 + nodes * nodes; + return current; +} + +/* + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +static int get_stack_for_port(int p) +{ +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else //if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; + else if (p >= PORT_4A && p <= PORT_4D) + return PSTACK3; // MCP0 + else + return PSTACK4; // MCP1 +#endif /* SOC_INTEL_SKYLAKE_SP */ +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +#endif /* SOC_INTEL_SKYLAKE_SP */ + + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, + bus, dev, func); + } + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + uint32_t bus = iio_resource.StackRes[stack].BusBase; +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +#endif /* SOC_INTEL_SKYLAKE_SP */ + + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (socket == 0 && p == 0) + continue; + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + if (first) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", + 0, pcie_seg); + current += acpi_create_dmar_atsr(current, 0, pcie_seg); + first = 0; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, CSTACK); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // ATSR - causes hang + current = acpi_create_atsr(current); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const struct soc_intel_xeon_sp_config *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", + (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); + acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} + diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 8139dc4..1bcc708 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -153,469 +153,3 @@ return current; } - -/* Northbridge SRAT,SLIT, etc. Make a common entry point and use. */ -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; - - memory_map = get_system_memory_map(); - assert(memory_map != NULL); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - int nodes = get_cpu_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8+nodes*nodes; - return current; -} - - -static int get_stack_for_port(int p) -{ - if (p == 0) - return CSTACK; - else if (p >= PORT_1A && p <= PORT_1D) - return PSTACK0; - else if (p >= PORT_2A && p <= PORT_2D) - return PSTACK1; - else if (p >= PORT_3A && p <= PORT_3D) - return PSTACK2; - else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK3; // MCP0 - else - return PSTACK4; // MCP1 -} - -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) -{ - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - - uint32_t enum_id; - unsigned long tmp = current; - - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - uint32_t reg_base = - hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); - - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - - // Add PCH IOAPIC - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - } - - // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); - - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } - - // Add PCIe Ports - if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, - bus, dev, func); - } - - // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } - } - - // Add HPET - if (socket == 0 && stack == CSTACK) { - uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count - printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", - __func__, hpet_capid, num_hpets); - //BIT 15 - if (num_hpets && (num_hpets != 0x1f) && - (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { - printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); - } - } - - acpi_dmar_drhd_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_atsr(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - unsigned long tmp = current; - bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " - "vtd_mmio_cap: 0x%llx\n", - __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); - - // ATSR is applicable only for platform supporting device IOTLBs - // through the VT-d extended capability register - assert(vtd_mmio_cap != 0xffffffffffffffff); - if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 - continue; - - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (socket == 0 && p == 0) - continue; - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - if (first) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", - 0, pcie_seg); - current += acpi_create_dmar_atsr(current, 0, pcie_seg); - first = 0; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); - } - } - if (tmp != current) - acpi_dmar_atsr_fixup(tmp, current); - } - - return current; -} - -static unsigned long acpi_create_rmrr(unsigned long current) -{ - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_rhsa(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " - "Proximity Domain: 0x%x\n", vtd_base, socket); - current += acpi_create_dmar_rhsa(current, vtd_base, socket); - } - } - - return current; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - // DRHD - for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { - int socket = iio; - if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry - socket = 0; - - if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); - } else { - for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - } - } - - // RMRR - current = acpi_create_rmrr(current); - - // ATSR - causes hang - current = acpi_create_atsr(current); - - // RHSA - current = acpi_create_rhsa(current); - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_dmar_t *dmar; - - const struct soc_intel_xeon_sp_config *const config = config_of(device); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* DMAR */ - if (config->vtd_support) { - current = ALIGN(current, 8); - dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", - (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); - acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - } - - return current; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Gerrit-Change-Number: 45850 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()
by Marc Jones (Code Review) 23 Oct '20

23 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45845 ) Change subject: soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt() ...................................................................... soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt() Prepare for common APCI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c 2 files changed, 25 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45845/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index b9e261e..93cd8ed 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -129,13 +129,18 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; @@ -150,26 +155,29 @@ fadt->duty_offset = 1; fadt->day_alrm = 0xd; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - /* General-Purpose Event Registers */ + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 6bf38f5..1aa1192 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -52,6 +52,13 @@ return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE); +} + /* * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() * with a call from the common/function or find another way to call this at the correct place -- To view, visit https://review.coreboot.org/c/coreboot/+/45845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Gerrit-Change-Number: 45845 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/samus: Fix touchscreen wake GPIO
by Matt DeVillier (Code Review) 23 Oct '20

23 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37892 ) Change subject: mb/google/samus: Fix touchscreen wake GPIO ...................................................................... mb/google/samus: Fix touchscreen wake GPIO Wrong macro was copy/pasted at some point Change-Id: I92826cbac599c50ce7f7c5dabde066367edc3053 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37892/1 diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 40a4df0..802e827 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -201,7 +201,7 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) + Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) -- To view, visit https://review.coreboot.org/c/coreboot/+/37892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92826cbac599c50ce7f7c5dabde066367edc3053 Gerrit-Change-Number: 37892 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [RFC]drivers/smmstore: Implement SMMSTORE version 2
by Patrick Rudolph (Code Review) 22 Oct '20

22 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40520 ) Change subject: [RFC]drivers/smmstore: Implement SMMSTORE version 2 ...................................................................... [RFC]drivers/smmstore: Implement SMMSTORE version 2 Seperates the SMMSTORE into 64KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like Tianocore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/c7cbcd527af397d5d8473f3e52720ffd… Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/smmstore/smi.c M src/drivers/smmstore/store.c M src/include/smmstore.h 3 files changed, 227 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40520/1 diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index 57f79b8..501f3d3 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -60,6 +60,47 @@ break; } + case SMMSTORE_CMD_INFO: { + printk(BIOS_DEBUG, "Returning SMM store info\n"); + struct smmstore_params_info *params = param; + if (smmstore_update_info(params) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_READ: { + printk(BIOS_DEBUG, "Raw read from SMM store, param = %p\n", param); + struct smmstore_params_raw_read *params = param; + void *buf = (void *)(uintptr_t)params->buf; + + if (range_check(buf, params->bufsize) != 0) + break; + + if (smmstore_rawread_region(buf, params->bufoffset, + params->block_id, &params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_WRITE: { + printk(BIOS_DEBUG, "Raw write to SMM store, param = %p\n", param); + struct smmstore_params_raw_write *params = param; + void *buf = (void *)(uintptr_t)params->buf; + + if (range_check(buf, params->bufsize) != 0) + break; + + if (smmstore_rawwrite_region(buf, params->bufoffset, + params->block_id, &params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_CLEAR: { + printk(BIOS_DEBUG, "Raw clear SMM store, param = %p\n", param); + struct smmstore_params_raw_clear *params = param; + + if (smmstore_rawclear_region(params->block_id) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } default: printk(BIOS_DEBUG, "Unknown SMM store command: 0x%02x\n", command); diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index dbad085..e10f133 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -263,3 +263,112 @@ return 0; } + + +/* implementation of Version 2 */ + +static struct smmstore_params_info info_params; + +int smmstore_update_info(struct smmstore_params_info *out) +{ + struct region_device store; + + if (!info_params.block_size) { + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "smm store: reading region failed\n"); + return -1; + } + info_params.block_size = 64 * KiB; + info_params.num_blocks = region_device_sz(&store) / info_params.block_size; + printk(BIOS_DEBUG, "smm store: %d # blocks with size 0x%x\n", + info_params.num_blocks, info_params.block_size); + } + + out->block_size = info_params.block_size; + out->num_blocks = info_params.num_blocks; + /* FIXME: Broken EDK2 always assumes memory mapped Firmware Block Volumes */ + out->mmap_addr = (uintptr_t)rdev_mmap_full(&store); + return 0; +} + +int smmstore_rawread_region(void *buf, uint32_t offset, uint32_t block_id, uint32_t *bufsize) +{ + struct region_device store; + ssize_t ret; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return -1; + } + + if (offset >= info_params.block_size || block_id >= info_params.num_blocks) { + printk(BIOS_WARNING, "access out of region requested\n"); + return -1; + } + + ssize_t tx = MIN(*bufsize, (block_id + 1) * info_params.block_size - offset); + printk(BIOS_DEBUG, "smm store: reading %p block %d, offset=0x%x, size=%zx\n", + buf, block_id, offset, tx); + ret = rdev_readat(&store, buf, block_id * info_params.block_size + offset, tx); + if (ret < 0) + return -1; + + *bufsize = ret; + + return 0; +} + +int smmstore_rawwrite_region(void *buf, uint32_t offset, uint32_t block_id, uint32_t *bufsize) +{ + struct region_device store; + ssize_t ret; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "writing region failed\n"); + return -1; + } + printk(BIOS_DEBUG, "smm store: writing %p block %d, offset=0x%x, size=%x\n", + buf, block_id, offset, *bufsize); + + if (offset >= info_params.block_size || block_id >= info_params.num_blocks) { + printk(BIOS_WARNING, "access out of region requested\n"); + return -1; + } + + if (rdev_chain(&store, &store, block_id * info_params.block_size + offset, *bufsize)) { + printk(BIOS_WARNING, "not enough space for new data\n"); + return -1; + } + + ret = rdev_writeat(&store, buf, 0, *bufsize); + if (ret < 0) + return -1; + + *bufsize = ret; + + return 0; +} + +int smmstore_rawclear_region(uint32_t block_id) +{ + struct region_device store; + + if (block_id >= info_params.num_blocks) { + printk(BIOS_WARNING, "access out of region requested\n"); + return -1; + } + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "smm store: reading region failed\n"); + return -1; + } + + ssize_t res = rdev_eraseat(&store, block_id * info_params.block_size, + info_params.block_size); + if (res != info_params.block_size) { + printk(BIOS_WARNING, "smm store: erasing block failed\n"); + return -1; + } + + return 0; +} diff --git a/src/include/smmstore.h b/src/include/smmstore.h index af07ff0..6a32008 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -11,10 +11,18 @@ #define SMMSTORE_RET_FAILURE 1 #define SMMSTORE_RET_UNSUPPORTED 2 +/* Version 1 */ #define SMMSTORE_CMD_CLEAR 1 #define SMMSTORE_CMD_READ 2 #define SMMSTORE_CMD_APPEND 3 +/* Version 2 */ +#define SMMSTORE_CMD_INFO 4 +#define SMMSTORE_CMD_RAW_READ 5 +#define SMMSTORE_CMD_RAW_WRITE 6 +#define SMMSTORE_CMD_RAW_CLEAR 7 + +/* Version 1 */ struct smmstore_params_read { void *buf; ssize_t bufsize; @@ -27,12 +35,80 @@ size_t valsize; }; +/* Version 2 */ +/* + * Version 2 of the SMM requires as SMMSTORE of at least 256KiB of size, that + * has to be aligned to 64KiB. + * This allows the payload to store raw data in the SMMSTORE flash region. + * This can be used by a FaultTolerantWrite implementation, that uses at least + * two regions in an A/B update scheme. + * + * The Version 2 protocol seperates the SMMSTORE into 64KiB blocks, where each block + * can be read/written/cleared in an independent manner. + * FIXME: The data format isn't specified. + * + */ +/* + * Returns the number of blocks the SMMSTORE supports and their size. + * For EDK2 this should be at least two blocks with 64KiB each. + */ +struct smmstore_params_info { + uint32_t num_blocks; + uint32_t block_size; + uint32_t mmap_addr; +} __packed; + +/* + * Reads a chunk of raw data with size @bufsize from the block specified by + * @block_id starting at @bufoffset. + * The read data is placed in memory pointed to by @buf. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_write { + uint32_t buf; + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Writes a chunk of raw data with size @bufsize to the block specified by + * @block_id starting at @bufoffset. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_read { + uint32_t buf; + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Erases the specified block. + * + * @block_id must be less than num_blocks + */ +struct smmstore_params_raw_clear { + uint32_t block_id; +} __packed; + + /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); -/* implementation */ +/* implementation of Version 1 */ int smmstore_read_region(void *buf, ssize_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); +/* implementation of Version 2 */ +int smmstore_update_info(struct smmstore_params_info *info); +int smmstore_rawread_region(void *buf, uint32_t offset, uint32_t block_id, uint32_t *bufsize); +int smmstore_rawwrite_region(void *buf, uint32_t offset, uint32_t block_id, uint32_t *bufsize); +int smmstore_rawclear_region(uint32_t block_id); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Gerrit-Change-Number: 40520 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

12 81

Change in coreboot[master]: console: Make DEFAULT_CONSOLE_LOGLEVEL available for CONSOLE_OVERRIDE...
by Johnny Lin (Code Review) 22 Oct '20

22 Oct '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45866 ) Change subject: console: Make DEFAULT_CONSOLE_LOGLEVEL available for CONSOLE_OVERRIDE_LOGLEVEL ...................................................................... console: Make DEFAULT_CONSOLE_LOGLEVEL available for CONSOLE_OVERRIDE_LOGLEVEL It's more flexible to be able to keep using DEFAULT_CONSOLE_LOGLEVEL when CONSOLE_OVERRIDE_LOGLEVEL is selected. Change-Id: Ib3ca8482459584e039a0e8881d79358948696ac2 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/console/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45866/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index bad6c56..28138b3 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -315,8 +315,6 @@ Set to "y" when the platform overrides the loglevel by providing a get_console_loglevel routine. -if !CONSOLE_OVERRIDE_LOGLEVEL - choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 if CHROMEOS @@ -375,8 +373,6 @@ help Map the log level config names to an integer. -endif - config NO_POST bool "Don't show any POST codes" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/45866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ca8482459584e039a0e8881d79358948696ac2 Gerrit-Change-Number: 45866 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware
by Paul Menzel (Code Review) 22 Oct '20

22 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39371 ) Change subject: mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware ...................................................................... mb/asus/f2a85-m: Copy Super I/O CR values from vendor firmware Here is the relevant output of `superiotool` for the global control registers: Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM The serial console still does not work. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/bootblock.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39371/1 diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index 3d980a6..cbd6e3a 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -15,6 +15,7 @@ */ #include <bootblock_common.h> +#include <device/pnp_ops.h> #include <device/pnp_type.h> #include <amdblocks/acpimmio.h> #include <stdint.h> @@ -47,8 +48,21 @@ static void superio_init_m_pro(void) { + pnp_devfn_t global_dev = PNP_DEV(0x2e, 0); pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); + pnp_write_config(global_dev, 0x13, 0xff); + pnp_write_config(global_dev, 0x14, 0xff); + pnp_write_config(global_dev, 0x1a, 0x0a); + pnp_write_config(global_dev, 0x1b, 0x28); + pnp_write_config(global_dev, 0x1c, 0x00); + pnp_write_config(global_dev, 0x1d, 0x10); + pnp_write_config(global_dev, 0x22, 0xdf); + pnp_write_config(global_dev, 0x2a, 0x48); + pnp_write_config(global_dev, 0x2b, 0x20); + pnp_write_config(global_dev, 0x2c, 0x00); + pnp_write_config(global_dev, 0x2f, 0x01); + nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/39371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Gerrit-Change-Number: 39371 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor
by Paul Menzel (Code Review) 21 Oct '20

21 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42201 ) Change subject: soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor ...................................................................... soc/intel/skylake: Check Kconfig symbols in C instead of preprocessor This unifies the file with `src/soc/intel/cannonlake/acpi.c`. Change-Id: Ia6601bfd6e7a11eca6bbc32f6757c165ba5a4cff Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42201/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index bdfacd3..5d48184 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,3 +1,4 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> @@ -170,15 +171,20 @@ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG(CHROMEOS) - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif + /* Update the mem console pointer. */ + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/42201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6601bfd6e7a11eca6bbc32f6757c165ba5a4cff Gerrit-Change-Number: 42201 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Skip writing references for disabled devices in Type-C config
by Tim Wawrzynczak (Code Review) 21 Oct '20

21 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45877 ) Change subject: acpi: Skip writing references for disabled devices in Type-C config ...................................................................... acpi: Skip writing references for disabled devices in Type-C config When emitting ACPI tables for the Type-C connector class, skip writing out a device reference if it is to a disabled device. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf --- M src/acpi/acpigen_usb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45877/1 diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 90a9b77..7448b3b 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -71,7 +71,7 @@ const char *path; char *fresh; - if (!dev) + if (!dev || !dev->enabled) return; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/45877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf Gerrit-Change-Number: 45877 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: add PEN for Boten
by Alec Wang (Code Review) 20 Oct '20

20 Oct '20

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45807 ) Change subject: mb/google/dedede: add PEN for Boten ...................................................................... mb/google/dedede: add PEN for Boten Add PEN to devicetree for boten BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb 3 files changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/45807/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index bd7d36e..fbc669f 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -2,6 +2,7 @@ def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DPTF_USE_EISA_HID + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 05a567f..f889c7f 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), /* C19 : AP_I2C_EMR_SCL */ diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 61dff93..b1fcbe6 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -9,9 +9,8 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | Stylus | #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -28,14 +27,35 @@ .i2c[2] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device pci 15.1 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wake_gpe" = "GPE0_DW2_12" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Gerrit-Change-Number: 45807 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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