coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/denverton_ns: Select CPU_INTEL_COMMON
by Angel Pons (Code Review) 28 Oct '20

28 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45040 ) Change subject: soc/intel/denverton_ns: Select CPU_INTEL_COMMON ...................................................................... soc/intel/denverton_ns: Select CPU_INTEL_COMMON This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1, Scaleway Tagada does not change. Change-Id: I70765dcc7cace1e367311824b81d3a6b21dba24c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45040/1 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3fce223..e6d3237 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -16,6 +16,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO + select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/45040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70765dcc7cace1e367311824b81d3a6b21dba24c Gerrit-Change-Number: 45040 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/amd/picasso/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 27 Oct '20

27 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45701 ) Change subject: soc/amd/picasso/acpi: Convert to ASL 2.0 syntax ...................................................................... soc/amd/picasso/acpi: Convert to ASL 2.0 syntax Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/pci_int.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/sleepstates.asl 4 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45701/1 diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index eb646de..e1b7498 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -48,7 +48,7 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 8)) { + If (\PCNT >= 8) { Return (Package () { \_SB.C000, @@ -60,7 +60,7 @@ \_SB.C006, \_SB.C007 }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { + } ElseIf (\PCNT >= 4) { Return (Package () { \_SB.C000, @@ -68,7 +68,7 @@ \_SB.C002, \_SB.C003 }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { + } ElseIf (\PCNT >= 2) { Return (Package () { \_SB.C000, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 2a2a561..8114c52 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -3,7 +3,7 @@ Method(\_PIC, 0x01, NotSerialized) { printf("PIC MODE: %o", Arg0) - Store(Arg0, PMOD) + PMOD = Arg0 } /* PIC Possible Resource Values */ diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 9208e13..f627a28 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -9,14 +9,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -78,15 +78,15 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) - Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) + BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index 88c6efc..03d28bb 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -3,25 +3,25 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) If (CONFIG(HAVE_ACPI_RESUME)) { - Store(0x0D, SSFG) + SSFG = 0x0D } If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSFG & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/45701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Gerrit-Change-Number: 45701 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/asurada: Init dram in romstage
by CK HU (Code Review) 27 Oct '20

27 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44568 to review the following change. Change subject: mb/google/asurada: Init dram in romstage ...................................................................... mb/google/asurada: Init dram in romstage Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/romstage.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44568/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 8395e4a..c742539 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -8,6 +8,7 @@ romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += memlayout.ld diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c new file mode 100644 index 0000000..8fa2f38 --- /dev/null +++ b/src/mainboard/google/asurada/romstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/dramc_param.h> +#include <soc/emi.h> +#include <soc/mmu_operations.h> + +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "read data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "write data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter = {0x0}; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + +void platform_romstage_main(void) +{ + mt_mem_init(&dparam_ops); + mtk_mmu_after_dram(); + printk(BIOS_WARNING, "after mt_mem_init\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Gerrit-Change-Number: 44568 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: mb/google/volteer/variants/eldrid: disable Fan Performance Control an...
by Nick Chen (Code Review) 27 Oct '20

27 Oct '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45860 ) Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ...................................................................... mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy add dptf option and disable fan relate control from overridetree.cb BUG=b:167931578 Signed-off-by: nick_xr_chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 6e9d743..1aef702 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -58,7 +58,75 @@ }" device domain 0 on - device pci 04.0 off end + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Gerrit-Change-Number: 45860 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

6 53

Change in coreboot[master]: sconfig: Move exported device names to separate output file
by Tim Wawrzynczak (Code Review) 26 Oct '20

26 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45667 ) Change subject: sconfig: Move exported device names to separate output file ...................................................................... sconfig: Move exported device names to separate output file Both the FW_CONFIG_FIELD_* macros and exported devicetree device names were placed in static.h. Some payloads may decide they would like to consume FW_CONFIG as well, however the current status of static.h makes this impossible. To alleviate this, the exported device names are moved to a separate output file named static_devices.h. This leaves static.h with only the FW_CONFIG_FIELD* macros, making it easily consumable by payloads. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Makefile.inc M util/sconfig/main.c 2 files changed, 30 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45667/1 diff --git a/Makefile.inc b/Makefile.inc index ccc614c..b9758f0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,6 +619,9 @@ mkdir -p $(dir $(DEVICETREE_STATIC_C)) $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) +DEVICETREE_DEVICENAMES_H := $(obj)/static_devices.h +SCONFIG_OPTIONS += --output_d=$(DEVICETREE_DEVICENAMES_H) + ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) verstage-y+=$(DEVICETREE_STATIC_C) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 842c8af..a35013c 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -528,9 +528,6 @@ if (!field) return; - fprintf(fil, "\n/* firmware configuration */\n"); - fprintf(fil, "#include <fw_config.h>\n"); - while (field) { struct fw_config_option *option = field->options; uint32_t mask; @@ -1719,6 +1716,7 @@ { "chipset_devtree", 1, NULL, 'p' }, { "output_c", 1, NULL, 'c' }, { "output_h", 1, NULL, 'r' }, + { "output_d", 1, NULL, 'd' }, { "help", 1, NULL, 'h' }, { } }; @@ -1727,9 +1725,10 @@ const char *chipset_devtree = NULL; const char *outputc = NULL; const char *outputh = NULL; + const char *outputd = NULL; int opt, option_index; - while ((opt = getopt_long(argc, argv, "m:o:p:c:r:h", long_options, + while ((opt = getopt_long(argc, argv, "m:o:p:c:r:d:h", long_options, &option_index)) != EOF) { switch (opt) { case 'm': @@ -1747,13 +1746,16 @@ case 'r': outputh = strdup(optarg); break; + case 'd': + outputd = strdup(optarg); + break; case 'h': default: usage(); } } - if (!base_devtree || !outputc || !outputh) + if (!base_devtree || !outputc || !outputh || !outputd) usage(); if (chipset_devtree) { @@ -1783,14 +1785,25 @@ fclose(autogen); exit(1); } + + FILE *autodev = fopen(outputd, "w"); + if (!autodev) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputd); + perror(NULL); + fclose(autogen); + fclose(autohead); + exit(1); + } + fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); - fprintf(autohead, "#include <device/device.h>\n\n"); emit_fw_config(autohead); fprintf(autogen, "#include <device/device.h>\n"); - fprintf(autogen, "#include <device/pci.h>\n\n"); + fprintf(autogen, "#include <device/pci.h>\n"); + fprintf(autogen, "#include <fw_config.h>\n"); fprintf(autogen, "#include <static.h>\n"); + fprintf(autogen, "#include <static_devices.h>\n\n"); emit_chip_headers(autogen, chip_header.next); fprintf(autogen, "\n#define STORAGE static __unused DEVTREE_CONST\n\n"); @@ -1804,12 +1817,17 @@ walk_device_tree(autogen, autohead, &base_root_dev, pass1); /* Expose static devicenames to global namespace. */ - fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + fprintf(autodev, "#ifndef __STATIC_DEVICES_H\n"); + fprintf(autodev, "#define __STATIC_DEVICES_H\n\n"); + fprintf(autodev, "#include <device/device.h>\n\n"); + fprintf(autodev, "/* expose_device_names */\n"); + walk_device_tree(autogen, autodev, &base_root_dev, expose_device_names); fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); + fprintf(autodev, "\n#endif /* __STATIC_DEVICE_NAMES_H */\n"); fclose(autohead); fclose(autogen); + fclose(autodev); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Gerrit-Change-Number: 45667 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

7 15

Change in coreboot[master]: mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL
by Johnny Lin (Code Review) 26 Oct '20

26 Oct '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45326 ) Change subject: mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL ...................................................................... mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL And set CONSOLE_VPD_DEFAULT_LOGLEVEL to 4 if the VPD variable is not found. Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45326/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b229c94..9fab7de 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CONSOLE_VPD_OVERRIDE_LOGLEVEL select FSP_CAR select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 @@ -51,4 +52,8 @@ bool default y +config CONSOLE_VPD_DEFAULT_LOGLEVEL + int + default 4 + endif # BOARD_OCP_DELTALAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/45326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Gerrit-Change-Number: 45326 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: console/init: Drop CONSOLE_LEVEL_CONST
by Nico Huber (Code Review) 26 Oct '20

26 Oct '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45765 to review the following change. Change subject: console/init: Drop CONSOLE_LEVEL_CONST ...................................................................... console/init: Drop CONSOLE_LEVEL_CONST We limited the configurability of the debug level to stages that have a `.data` section. This is not really a requirement, because a `.bss` section should suffice and we always have that now. Making the debug level always configurable, adds an early call to get_option(). But that shouldn't hurt: The value is cached locally. Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/init.c 1 file changed, 2 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45765/1 diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..9776e2a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -8,40 +8,24 @@ #include <option.h> #include <version.h> -/* Mutable console log level only allowed when RAM comes online. */ -#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION - static int console_inited; -static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +static int console_loglevel; static inline int get_log_level(void) { if (console_inited == 0) return -1; - if (CONSOLE_LEVEL_CONST) - return get_console_loglevel(); return console_loglevel; } -static inline void set_log_level(int new_level) -{ - if (CONSOLE_LEVEL_CONST) - return; - - console_loglevel = new_level; -} - static void init_log_level(void) { int debug_level = get_console_loglevel(); - if (CONSOLE_LEVEL_CONST) - return; - get_option(&debug_level, "debug_level"); - set_log_level(debug_level); + console_loglevel = debug_level; } int console_log_level(int msg_level) -- To view, visit https://review.coreboot.org/c/coreboot/+/45765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Gerrit-Change-Number: 45765 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

8 20

Change in coreboot[master]: mb/google/zork/vilboz: Enable P sensor
by Frank Wu (Code Review) 26 Oct '20

26 Oct '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45565 ) Change subject: mb/google/zork/vilboz: Enable P sensor ...................................................................... mb/google/zork/vilboz: Enable P sensor BUG=b:161759253 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 --- M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45565/1 diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 12b303a..d4bcfa5 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -10,6 +10,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { /* TP */ PAD_NC(GPIO_32), + /* P sensor INT */ + PAD_GPI(GPIO_40, PULL_NONE), /* EN_DEV_BEEP_L */ PAD_GPO(GPIO_89, HIGH), /* USI_RESET */ diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index d415de5..932805f 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -136,5 +136,12 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + device i2c 28 on end + end end end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/45565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 Gerrit-Change-Number: 45565 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: src: Remove unused <arch/io.h>
by HAOUAS Elyes (Code Review) 26 Oct '20

26 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45404 ) Change subject: src: Remove unused <arch/io.h> ...................................................................... src: Remove unused <arch/io.h> Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ipmi_kcs_ops_premem.c M src/include/device/pnp_ops.h M src/mainboard/51nb/x210/romstage.c M src/mainboard/asus/a88xm-e/romstage.c M src/mainboard/asus/am1i-a/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c M src/mainboard/facebook/fbg1701/ramstage.c M src/mainboard/lenovo/t440p/smihandler.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/mainboard.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/lynxpoint/early_pch.c 35 files changed, 8 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45404/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3..dd8f34c 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -8,6 +8,7 @@ * end */ +#include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pnp.h> diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c index d799be1..e1ae0dc 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops_premem.c +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <console/console.h> #include <device/pnp.h> #include <delay.h> diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 15acf36..8a6face 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -4,7 +4,6 @@ #define __DEVICE_PNP_OPS_H__ #include <stdint.h> -#include <arch/io.h> #include <device/pnp.h> #if ENV_PNP_SIMPLE_DEVICE diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 2112e25..38652b5 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -3,7 +3,6 @@ #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> -#include <arch/io.h> #include <string.h> static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c index c9ba041..1187de2 100644 --- a/src/mainboard/asus/a88xm-e/romstage.c +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> -#include <arch/io.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/smbus.h> diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index 4cfa5b1..6e71962 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <arch/io.h> #include <bootblock_common.h> #include <device/pnp_ops.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..6f23a34 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> -#include <arch/io.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 2719460..5a58f90 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -3,7 +3,6 @@ #include <cbfs.h> #include <cf9_reset.h> #include <option.h> -#include <arch/io.h> #include <cpu/x86/msr.h> #include <console/console.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 59832a47..be99573 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <console/console.h> #include <soc/ramstage.h> #include <soc/smbus.h> diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index 8cc5135..de48240 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 05a4cf2..d8e82fc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/io.h> #include <ec/acpi/ec.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index ce8d504..0ba7342 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <arch/io.h> #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f594..dea4f9b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index e5ecafe..6b9f3d0 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <stdint.h> #include <console/console.h> #include <cf9_reset.h> diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 89e7014..cccc4ca 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -7,7 +7,6 @@ #include <amdblocks/spi.h> #include <arch/exception.h> #include <arch/hlt.h> -#include <arch/io.h> #include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 46f12e7..fa8283c 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/io.h> #include <device/pci_ops.h> #include <soc/iosf.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 252a82a..3d1ea28 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <bootblock_common.h> #include <build.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 87ace88..e4b6295 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b3f4fe5..6e1a66f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -7,7 +7,6 @@ #include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 562db4e..1418d30 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a..0e31524 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e3..5bfad71 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 228e0f6..e40d248 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 6412144..8755825 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index e9b3f21..1fa3714 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cba..00850ac 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..707ae20 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 98f12a5..7ac7f5b 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <bootstate.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de..52d3e2f 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -6,7 +6,6 @@ * Chapter number: 4, 29 */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 17f801b..fb0d05c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -14,7 +14,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index bce7738..ce5e305 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,7 +26,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 59d4297..975d839 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <console/console.h> #include <device/pci_ops.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 06d7c74..a9402c7 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> -#include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac009..ace09e2 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 956d1d2..8cffe57 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Gerrit-Change-Number: 45404 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/acpi: Add pch.asl
by Marc Jones (Code Review) 26 Oct '20

26 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45836 ) Change subject: soc/intel/xeon_sp/acpi: Add pch.asl ...................................................................... soc/intel/xeon_sp/acpi: Add pch.asl Add ASL for the PCH. Initially, this only contains soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL may be added in the future. Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- A src/soc/intel/xeon_sp/acpi/pch.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45836/1 diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/pch.asl new file mode 100644 index 0000000..98a5fdd --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pch.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file should be included in the proper platform ACPI \_SB PCI scope */ + +/* LPC 0:1f.0 */ +#include <soc/intel/common/block/acpi/acpi/lpc.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Gerrit-Change-Number: 45836 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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