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Change in coreboot[master]: soc/intel/broadwell: Relocate southbridge .c files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41929 ) Change subject: soc/intel/broadwell: Relocate southbridge .c files ...................................................................... soc/intel/broadwell: Relocate southbridge .c files Move Broadwell southbridge source code files under the southbridge scope. The PCH that Broadwell is paired with is called Wildcat Point. Note that headers and Kconfig still reside inside the soc namespace. This is temporary and will be accounted for in subsequent commits. Change-Id: Ia2831c24314f685fc1f7f4993efa23e9bb025f24 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/romstage/Makefile.inc A src/southbridge/intel/wildcatpoint/Makefile.inc R src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/early_pch.c R src/southbridge/intel/wildcatpoint/early_smbus.c R src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/elog.c R src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/hda.c R src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me_status.c R src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pmutil.c R src/southbridge/intel/wildcatpoint/power_state.c R src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smi.c R src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/uart.c R src/southbridge/intel/wildcatpoint/usb_debug.c R src/southbridge/intel/wildcatpoint/xhci.c 28 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41929/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 46ea705..dada3d1 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,43 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += romstage - -bootblock-y += bootblock/pch.c - -ramstage-y += adsp.c -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += gpio.c -romstage-y += gpio.c -smm-y += gpio.c -ramstage-y += hda.c -ramstage-y += iobp.c -romstage-y += iobp.c -ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c -ramstage-y += pch.c -romstage-y += pch.c -ramstage-y += pcie.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c -ramstage-y += ramstage.c -ramstage-y += sata.c -ramstage-y += serialio.c -ramstage-y += smbus.c -ramstage-y += smi.c -smm-y += smihandler.c -bootblock-y += usb_debug.c -romstage-y += usb_debug.c -ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c - -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - CPPFLAGS_common += -Isrc/soc/intel/broadwell/include endif diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc deleted file mode 100644 index 511295d..0000000 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -romstage-y += pch.c -romstage-y += power_state.c -romstage-y += smbus.c -romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc new file mode 100644 index 0000000..f1761f2 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/Makefile.inc @@ -0,0 +1,42 @@ +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) + +romstage-y += early_pch.c +romstage-y += early_smbus.c +romstage-y += power_state.c +romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c + +ramstage-y += adsp.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += gpio.c +romstage-y += gpio.c +smm-y += gpio.c +ramstage-y += hda.c +ramstage-y += iobp.c +romstage-y += iobp.c +ramstage-y += lpc.c +ramstage-y += me.c +ramstage-y += me_status.c +romstage-y += me_status.c +ramstage-y += pch.c +romstage-y += pch.c +ramstage-y += pcie.c +ramstage-y += pmutil.c +romstage-y += pmutil.c +smm-y += pmutil.c +verstage-y += pmutil.c +ramstage-y += ramstage.c +ramstage-y += sata.c +ramstage-y += serialio.c +ramstage-y += smbus.c +ramstage-y += smi.c +smm-y += smihandler.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c +ramstage-y += ehci.c +ramstage-y += xhci.c +smm-y += xhci.c + +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c + +endif diff --git a/src/soc/intel/broadwell/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c similarity index 100% rename from src/soc/intel/broadwell/adsp.c rename to src/southbridge/intel/wildcatpoint/adsp.c diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/southbridge/intel/wildcatpoint/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/pch.c rename to src/southbridge/intel/wildcatpoint/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c similarity index 100% rename from src/soc/intel/broadwell/romstage/pch.c rename to src/southbridge/intel/wildcatpoint/early_pch.c diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c similarity index 100% rename from src/soc/intel/broadwell/romstage/smbus.c rename to src/southbridge/intel/wildcatpoint/early_smbus.c diff --git a/src/soc/intel/broadwell/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c similarity index 100% rename from src/soc/intel/broadwell/ehci.c rename to src/southbridge/intel/wildcatpoint/ehci.c diff --git a/src/soc/intel/broadwell/elog.c b/src/southbridge/intel/wildcatpoint/elog.c similarity index 100% rename from src/soc/intel/broadwell/elog.c rename to src/southbridge/intel/wildcatpoint/elog.c diff --git a/src/soc/intel/broadwell/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c similarity index 100% rename from src/soc/intel/broadwell/gpio.c rename to src/southbridge/intel/wildcatpoint/gpio.c diff --git a/src/soc/intel/broadwell/hda.c b/src/southbridge/intel/wildcatpoint/hda.c similarity index 100% rename from src/soc/intel/broadwell/hda.c rename to src/southbridge/intel/wildcatpoint/hda.c diff --git a/src/soc/intel/broadwell/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c similarity index 100% rename from src/soc/intel/broadwell/iobp.c rename to src/southbridge/intel/wildcatpoint/iobp.c diff --git a/src/soc/intel/broadwell/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c similarity index 100% rename from src/soc/intel/broadwell/lpc.c rename to src/southbridge/intel/wildcatpoint/lpc.c diff --git a/src/soc/intel/broadwell/me.c b/src/southbridge/intel/wildcatpoint/me.c similarity index 100% rename from src/soc/intel/broadwell/me.c rename to src/southbridge/intel/wildcatpoint/me.c diff --git a/src/soc/intel/broadwell/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c similarity index 100% rename from src/soc/intel/broadwell/me_status.c rename to src/southbridge/intel/wildcatpoint/me_status.c diff --git a/src/soc/intel/broadwell/pch.c b/src/southbridge/intel/wildcatpoint/pch.c similarity index 100% rename from src/soc/intel/broadwell/pch.c rename to src/southbridge/intel/wildcatpoint/pch.c diff --git a/src/soc/intel/broadwell/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c similarity index 100% rename from src/soc/intel/broadwell/pcie.c rename to src/southbridge/intel/wildcatpoint/pcie.c diff --git a/src/soc/intel/broadwell/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c similarity index 100% rename from src/soc/intel/broadwell/pmutil.c rename to src/southbridge/intel/wildcatpoint/pmutil.c diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c similarity index 100% rename from src/soc/intel/broadwell/romstage/power_state.c rename to src/southbridge/intel/wildcatpoint/power_state.c diff --git a/src/soc/intel/broadwell/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c similarity index 100% rename from src/soc/intel/broadwell/ramstage.c rename to src/southbridge/intel/wildcatpoint/ramstage.c diff --git a/src/soc/intel/broadwell/sata.c b/src/southbridge/intel/wildcatpoint/sata.c similarity index 100% rename from src/soc/intel/broadwell/sata.c rename to src/southbridge/intel/wildcatpoint/sata.c diff --git a/src/soc/intel/broadwell/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c similarity index 100% rename from src/soc/intel/broadwell/serialio.c rename to src/southbridge/intel/wildcatpoint/serialio.c diff --git a/src/soc/intel/broadwell/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c similarity index 100% rename from src/soc/intel/broadwell/smbus.c rename to src/southbridge/intel/wildcatpoint/smbus.c diff --git a/src/soc/intel/broadwell/smi.c b/src/southbridge/intel/wildcatpoint/smi.c similarity index 100% rename from src/soc/intel/broadwell/smi.c rename to src/southbridge/intel/wildcatpoint/smi.c diff --git a/src/soc/intel/broadwell/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/smihandler.c rename to src/southbridge/intel/wildcatpoint/smihandler.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/southbridge/intel/wildcatpoint/uart.c similarity index 100% rename from src/soc/intel/broadwell/romstage/uart.c rename to src/southbridge/intel/wildcatpoint/uart.c diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/southbridge/intel/wildcatpoint/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/usb_debug.c rename to src/southbridge/intel/wildcatpoint/usb_debug.c diff --git a/src/soc/intel/broadwell/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c similarity index 100% rename from src/soc/intel/broadwell/xhci.c rename to src/southbridge/intel/wildcatpoint/xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2831c24314f685fc1f7f4993efa23e9bb025f24 Gerrit-Change-Number: 41929 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/broadwell: Relocate northbridge .c files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41928 ) Change subject: soc/intel/broadwell: Relocate northbridge .c files ...................................................................... soc/intel/broadwell: Relocate northbridge .c files Move Broadwell northbridge source code files under the northbridge scope. Assume that both MRC and the refcode are northbridge things. Note that headers and Kconfig still reside inside the soc namespace. This is temporary and will be accounted for in subsequent commits. Change-Id: I645881f9691cfb78bc8b03902e1cc74e37490276 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/broadwell/Makefile.inc R src/northbridge/intel/broadwell/bootblock.c R src/northbridge/intel/broadwell/finalize.c R src/northbridge/intel/broadwell/igd.c R src/northbridge/intel/broadwell/memmap.c R src/northbridge/intel/broadwell/minihd.c R src/northbridge/intel/broadwell/pei_data.c R src/northbridge/intel/broadwell/raminit.c R src/northbridge/intel/broadwell/refcode.c R src/northbridge/intel/broadwell/report_platform.c R src/northbridge/intel/broadwell/romstage.c R src/northbridge/intel/broadwell/systemagent.c M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/romstage/Makefile.inc 15 files changed, 37 insertions(+), 654 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41928/1 diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc new file mode 100644 index 0000000..77e96ce --- /dev/null +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -0,0 +1,37 @@ +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) + +bootblock-y += bootblock.c + +ramstage-y += finalize.c + +ramstage-y += igd.c + +ramstage-y += memmap.c +romstage-y += memmap.c +postcar-y += memmap.c +ramstage-y += minihd.c + +ramstage-y += pei_data.c +romstage-y += pei_data.c + +romstage-y += raminit.c +romstage-y += report_platform.c +romstage-y += romstage.c + +ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c + +ramstage-y += systemagent.c + +# If an MRC file is an ELF file determine the entry address and first loadable +# section offset in the file. Subtract the offset from the entry address to +# determine the final location. +mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) +mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') + +# Add memory reference code blob. +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin +mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) +mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) +mrc.bin-type := mrc + +endif diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/northbridge/intel/broadwell/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/systemagent.c rename to src/northbridge/intel/broadwell/bootblock.c diff --git a/src/soc/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c similarity index 100% rename from src/soc/intel/broadwell/finalize.c rename to src/northbridge/intel/broadwell/finalize.c diff --git a/src/soc/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c similarity index 100% rename from src/soc/intel/broadwell/igd.c rename to src/northbridge/intel/broadwell/igd.c diff --git a/src/soc/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c similarity index 100% rename from src/soc/intel/broadwell/memmap.c rename to src/northbridge/intel/broadwell/memmap.c diff --git a/src/soc/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c similarity index 100% rename from src/soc/intel/broadwell/minihd.c rename to src/northbridge/intel/broadwell/minihd.c diff --git a/src/soc/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c similarity index 100% rename from src/soc/intel/broadwell/pei_data.c rename to src/northbridge/intel/broadwell/pei_data.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/northbridge/intel/broadwell/raminit.c similarity index 100% rename from src/soc/intel/broadwell/romstage/raminit.c rename to src/northbridge/intel/broadwell/raminit.c diff --git a/src/soc/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c similarity index 100% rename from src/soc/intel/broadwell/refcode.c rename to src/northbridge/intel/broadwell/refcode.c diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c similarity index 100% rename from src/soc/intel/broadwell/romstage/report_platform.c rename to src/northbridge/intel/broadwell/report_platform.c diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/northbridge/intel/broadwell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/systemagent.c rename to src/northbridge/intel/broadwell/romstage.c diff --git a/src/soc/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c similarity index 100% rename from src/soc/intel/broadwell/systemagent.c rename to src/northbridge/intel/broadwell/systemagent.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7e502ec..46ea705 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -3,43 +3,32 @@ subdirs-y += romstage bootblock-y += bootblock/pch.c -bootblock-y += bootblock/systemagent.c ramstage-y += adsp.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += finalize.c ramstage-y += gpio.c romstage-y += gpio.c smm-y += gpio.c ramstage-y += hda.c -ramstage-y += igd.c ramstage-y += iobp.c romstage-y += iobp.c ramstage-y += lpc.c ramstage-y += me.c ramstage-y += me_status.c romstage-y += me_status.c -ramstage-y += memmap.c -romstage-y += memmap.c -postcar-y += memmap.c -ramstage-y += minihd.c ramstage-y += pch.c romstage-y += pch.c ramstage-y += pcie.c -ramstage-y += pei_data.c -romstage-y += pei_data.c ramstage-y += pmutil.c romstage-y += pmutil.c smm-y += pmutil.c verstage-y += pmutil.c ramstage-y += ramstage.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += smbus.c ramstage-y += smi.c smm-y += smihandler.c -ramstage-y += systemagent.c bootblock-y += usb_debug.c romstage-y += usb_debug.c ramstage-y += usb_debug.c @@ -51,16 +40,4 @@ CPPFLAGS_common += -Isrc/soc/intel/broadwell/include -# If an MRC file is an ELF file determine the entry address and first loadable -# section offset in the file. Subtract the offset from the entry address to -# determine the final location. -mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) -mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') - -# Add memory reference code blob. -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) -mrc.bin-type := mrc - endif diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c deleted file mode 100644 index 316b85a..0000000 --- a/src/soc/intel/broadwell/acpi.c +++ /dev/null @@ -1,628 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpigen.h> -#include <arch/smp/mpspec.h> -#include <cbmem.h> -#include <device/pci_ops.h> -#include <cpu/x86/smm.h> -#include <console/console.h> -#include <types.h> -#include <string.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <soc/acpi.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/systemagent.h> -#include <soc/intel/broadwell/chip.h> -#include <intelblocks/cpulib.h> - -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_s0ix[3] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -static int cstate_set_non_s0ix[3] = { - C_STATE_C1E, - C_STATE_C3, - C_STATE_C7S_LONG_LAT -}; - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -void acpi_init_gnvs(global_nvs_t *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - -#if CONFIG(CHROMEOS) - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -void acpi_fill_in_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; -} - -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; - const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; - const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; - const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; - - /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - - acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); - } - - /* VTVC0BAR has to be set, enabled, and in 32-bit space */ - if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { - const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); - acpi_dmar_drhd_fixup(tmp, current); - } - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - /* Create DMAR table only if we have VT-d capability. */ - const u32 capid0_a = pci_read_config32(dev, CAPID0_A); - if (capid0_a & VTD_DISABLE) - return current; - - acpi_dmar_t *const dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - - return current; -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci >= 20) - flags |= MP_IRQ_POLARITY_LOW; - else - flags |= MP_IRQ_POLARITY_HIGH; - - /* SCI */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); - - return current; -} diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index fb6c56a..511295d 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,7 +1,4 @@ romstage-y += pch.c romstage-y += power_state.c -romstage-y += raminit.c -romstage-y += report_platform.c romstage-y += smbus.c -romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I645881f9691cfb78bc8b03902e1cc74e37490276 Gerrit-Change-Number: 41928 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: soc/intel/broadwell/Kconfig: Tidy up selected symbols
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41930 ) Change subject: soc/intel/broadwell/Kconfig: Tidy up selected symbols ...................................................................... soc/intel/broadwell/Kconfig: Tidy up selected symbols Order the `select` entries alphabetically except for the stage architecture entries. Also, rename the dummy symbol where these are selected from `CPU_SPECIFIC_OPTIONS` to `SOC_SPECIFIC_OPTIONS`, because the original symbol would result in name clashes in future commits. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I042189c271bf918bf7d988ecdc062ffeccfd881a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/41930/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 67f7563..bdbdda4 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,7 +5,7 @@ if SOC_INTEL_BROADWELL -config CPU_SPECIFIC_OPTIONS +config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_BOOTBLOCK_X86_32 @@ -14,37 +14,37 @@ select ARCH_RAMSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select MRC_SETTINGS_PROTECT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select HAVE_SPI_CONSOLE_SUPPORT select HAVE_USBDEBUG select IOAPIC - select REG_SCRIPT + select INTEL_DESCRIPTOR_MODE_CAPABLE + select INTEL_GMA_ACPI + select MRC_SETTINGS_PROTECT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP + select REG_SCRIPT select RTC select SMP - select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select HAVE_SPI_CONSOLE_SUPPORT - select INTEL_GMA_ACPI - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select NO_FIXED_XIP_ROM_SIZE + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SPI_FLASH + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select TSC_SYNC_MFENCE + select UDELAY_TSC config PCIEXP_ASPM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/41930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I042189c271bf918bf7d988ecdc062ffeccfd881a Gerrit-Change-Number: 41930 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: Drop SOC_INTEL_BROADWELL from Kconfig
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41940 ) Change subject: Drop SOC_INTEL_BROADWELL from Kconfig ...................................................................... Drop SOC_INTEL_BROADWELL from Kconfig With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I966f767c904e64d290a6d59b77bb7470c77f7f17 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile.inc M src/drivers/intel/gma/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/purism/librem_bdw/Kconfig D src/soc/intel/broadwell/Kconfig M src/southbridge/intel/common/firmware/Kconfig 8 files changed, 14 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/41940/1 diff --git a/Makefile.inc b/Makefile.inc index 86467a6..4f2eeef 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -253,7 +253,7 @@ # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y) IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 635de1c..01a580f 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -72,8 +72,8 @@ def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ - || NORTHBRIDGE_INTEL_HASWELL \ - || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ + || NORTHBRIDGE_INTEL_HASWELL || NORTHBRIDGE_INTEL_BROADWELL \ + || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ || SOC_INTEL_WHISKEYLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID @@ -103,7 +103,7 @@ default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || NORTHBRIDGE_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 20d2e44..2319598 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,7 +1,8 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n - select SOC_INTEL_BROADWELL + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 71143c9..a13d290 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n - select SOC_INTEL_BROADWELL + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 2f6b21e..9f7a20c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,7 +2,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_INTEL_BROADWELL + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index dcfe78e..7deefa8 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -9,7 +9,8 @@ select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM1 - select SOC_INTEL_BROADWELL + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT if BOARD_PURISM_BASEBOARD_LIBREM_BDW diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig deleted file mode 100644 index 2556ee2..0000000 --- a/src/soc/intel/broadwell/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -config SOC_INTEL_BROADWELL - bool - select NORTHBRIDGE_INTEL_BROADWELL - select SOUTHBRIDGE_INTEL_WILDCATPOINT - help - Intel Broadwell and Haswell ULT support. diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index d827b1a..4b6967e 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -48,7 +48,7 @@ depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ - SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ + SOUTHBRIDGE_INTEL_WILDCATPOINT || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help Verify the integrity of the supplied Intel ME/TXE firmware before @@ -60,7 +60,7 @@ depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ - SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ + SOUTHBRIDGE_INTEL_WILDCATPOINT || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help Use me_cleaner to remove all the non-fundamental code from the Intel -- To view, visit https://review.coreboot.org/c/coreboot/+/41940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I966f767c904e64d290a6d59b77bb7470c77f7f17 Gerrit-Change-Number: 41940 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: [DO NOT MERGE] LPT/WPT: WIP unification
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42520 ) Change subject: [DO NOT MERGE] LPT/WPT: WIP unification ...................................................................... [DO NOT MERGE] LPT/WPT: WIP unification Change-Id: I62e80c009f8360b1d780db84eeddc6dc1799ee98 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/southbridge/intel/lynxpoint/lpt_nvs.h A src/southbridge/intel/lynxpoint/nvs.c M src/southbridge/intel/lynxpoint/nvs.h M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/wildcatpoint/nvs.h 5 files changed, 125 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42520/1 diff --git a/src/southbridge/intel/lynxpoint/lpt_nvs.h b/src/southbridge/intel/lynxpoint/lpt_nvs.h new file mode 100644 index 0000000..08d8043 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/lpt_nvs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/helpers.h> +#include <stdint.h> +#include "vendorcode/google/chromeos/gnvs.h" + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + /* Thermal policy */ + u8 tlvl; /* 0x11 - Throttle Level Limit */ + u8 flvl; /* 0x12 - Current FAN Level */ + u8 tcrt; /* 0x13 - Critical Threshold */ + u8 tpsv; /* 0x14 - Passive Threshold */ + u8 tmax; /* 0x15 - CPU Tj_max */ + u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ + u8 f0on; /* 0x17 - FAN 0 ON Threshold */ + u8 f0pw; /* 0x18 - FAN 0 PWM value */ + u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ + u8 f1on; /* 0x1a - FAN 1 ON Threshold */ + u8 f1pw; /* 0x1b - FAN 1 PWM value */ + u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ + u8 f2on; /* 0x1d - FAN 2 ON Threshold */ + u8 f2pw; /* 0x1e - FAN 2 PWM value */ + u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ + u8 f3on; /* 0x20 - FAN 3 ON Threshold */ + u8 f3pw; /* 0x21 - FAN 3 PWM value */ + u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ + u8 f4on; /* 0x23 - FAN 4 ON Threshold */ + u8 f4pw; /* 0x24 - FAN 4 PWM value */ + u8 tmps; /* 0x25 - Temperature Sensor ID */ + u8 rsvd3[2]; + /* Processor Identification */ + u8 apic; /* 0x28 - APIC enabled */ + u8 mpen; /* 0x29 - MP capable/enabled */ + u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ + u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ + u8 ppcm; /* 0x2c - Max. PPC state */ + u8 pcnt; /* 0x2d - Processor Count */ + u8 rsvd4[4]; + /* Super I/O & CMOS config */ + u8 natp; /* 0x32 - SIO type */ + u8 s5u0; /* 0x33 - Enable USB0 in S5 */ + u8 s5u1; /* 0x34 - Enable USB1 in S5 */ + u8 s3u0; /* 0x35 - Enable USB0 in S3 */ + u8 s3u1; /* 0x36 - Enable USB1 in S3 */ + u8 s33g; /* 0x37 - Enable S3 in 3G */ + u32 obsolete_cmem; /* 0x38 - CBMEM TOC */ + /* Integrated Graphics Device */ + u8 igds; /* 0x3c - IGD state */ + u8 tlst; /* 0x3d - Display Toggle List Pointer */ + u8 cadl; /* 0x3e - currently attached devices */ + u8 padl; /* 0x3f - previously attached devices */ + u8 rsvd14[27]; + /* TPM support */ + u8 tpmp; /* 0x5b - TPM Present */ + u8 tpme; /* 0x5c - TPM Enable */ + u8 rsvd5[3]; + /* LynxPoint Serial IO device BARs */ + u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ + u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ + u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + u8 rsvd6[92]; + + /* ChromeOS specific (starts at 0x100)*/ + chromeos_acpi_t chromeos; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); + +void acpi_create_gnvs(global_nvs_t *gnvs); + +static inline void gnvs_set_sio_bar0(global_nvs_t *gnvs, int sio_index, u32 bar0_base) +{ + gnvs->s0b[sio_index] = bar0_base; +} + +static inline void gnvs_set_sio_bar1(global_nvs_t *gnvs, int sio_index, u32 bar1_base) +{ + gnvs->s1b[sio_index] = bar1_base; +} diff --git a/src/southbridge/intel/lynxpoint/nvs.c b/src/southbridge/intel/lynxpoint/nvs.c new file mode 100644 index 0000000..03fc48e --- /dev/null +++ b/src/southbridge/intel/lynxpoint/nvs.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" +#include "iobp.h" +#include "pch.h" +#include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b5b6e9f..48af38f 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -1,85 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <commonlib/helpers.h> -#include <stdint.h> -#include "vendorcode/google/chromeos/gnvs.h" - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - /* Thermal policy */ - u8 tlvl; /* 0x11 - Throttle Level Limit */ - u8 flvl; /* 0x12 - Current FAN Level */ - u8 tcrt; /* 0x13 - Critical Threshold */ - u8 tpsv; /* 0x14 - Passive Threshold */ - u8 tmax; /* 0x15 - CPU Tj_max */ - u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ - u8 f0on; /* 0x17 - FAN 0 ON Threshold */ - u8 f0pw; /* 0x18 - FAN 0 PWM value */ - u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ - u8 f1on; /* 0x1a - FAN 1 ON Threshold */ - u8 f1pw; /* 0x1b - FAN 1 PWM value */ - u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ - u8 f2on; /* 0x1d - FAN 2 ON Threshold */ - u8 f2pw; /* 0x1e - FAN 2 PWM value */ - u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ - u8 f3on; /* 0x20 - FAN 3 ON Threshold */ - u8 f3pw; /* 0x21 - FAN 3 PWM value */ - u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ - u8 f4on; /* 0x23 - FAN 4 ON Threshold */ - u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 tmps; /* 0x25 - Temperature Sensor ID */ - u8 rsvd3[2]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ - u8 rsvd4[4]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 s5u0; /* 0x33 - Enable USB0 in S5 */ - u8 s5u1; /* 0x34 - Enable USB1 in S5 */ - u8 s3u0; /* 0x35 - Enable USB0 in S3 */ - u8 s3u1; /* 0x36 - Enable USB1 in S3 */ - u8 s33g; /* 0x37 - Enable S3 in 3G */ - u32 obsolete_cmem; /* 0x38 - CBMEM TOC */ - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u8 rsvd14[27]; - /* TPM support */ - u8 tpmp; /* 0x5b - TPM Present */ - u8 tpme; /* 0x5c - TPM Enable */ - u8 rsvd5[3]; - /* LynxPoint Serial IO device BARs */ - u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ - u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ - u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ - u8 rsvd6[92]; - - /* ChromeOS specific (starts at 0x100)*/ - chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -void acpi_create_gnvs(global_nvs_t * gnvs); +#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) +#include <southbridge/intel/lynxpoint/lpt_nvs.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT) +#include <southbridge/intel/wildcatpoint/nvs.h> +#endif diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 8c2d940..cfa9f21 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -209,8 +209,8 @@ } /* Save BAR0 and BAR1 to ACPI NVS */ - gnvs->s0b[sio_index] = (u32)bar0->base; - gnvs->s1b[sio_index] = (u32)bar1->base; + gnvs_set_sio_bar0(gnvs, sio_index, (u32)bar0->base); + gnvs_set_sio_bar1(gnvs, sio_index, (u32)bar1->base); } } diff --git a/src/southbridge/intel/wildcatpoint/nvs.h b/src/southbridge/intel/wildcatpoint/nvs.h index b5fca62..712649d 100644 --- a/src/southbridge/intel/wildcatpoint/nvs.h +++ b/src/southbridge/intel/wildcatpoint/nvs.h @@ -53,4 +53,14 @@ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); +static inline void gnvs_set_sio_bar0(global_nvs_t *gnvs, int sio_index, u32 bar0_base) +{ + gnvs->dev.bar0[sio_index] = bar0_base; +} + +static inline void gnvs_set_sio_bar1(global_nvs_t *gnvs, int sio_index, u32 bar1_base) +{ + gnvs->dev.bar1[sio_index] = bar1_base; +} + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62e80c009f8360b1d780db84eeddc6dc1799ee98 Gerrit-Change-Number: 42520 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: cpu/intel/broadwell: Add Kconfig
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41931 ) Change subject: cpu/intel/broadwell: Add Kconfig ...................................................................... cpu/intel/broadwell: Add Kconfig Move the CPU-related Kconfig settings from soc to the cpu scope. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 43 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..b609422 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -14,6 +14,7 @@ source "src/cpu/intel/model_f3x/Kconfig" source "src/cpu/intel/model_f4x/Kconfig" source "src/cpu/intel/haswell/Kconfig" +source "src/cpu/intel/broadwell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" source "src/cpu/intel/socket_BGA956/Kconfig" diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 21dc291..95e4b11 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,7 +13,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell +subdirs-$(CONFIG_CPU_INTEL_BROADWELL) += broadwell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/broadwell/Kconfig b/src/cpu/intel/broadwell/Kconfig new file mode 100644 index 0000000..5889646 --- /dev/null +++ b/src/cpu/intel/broadwell/Kconfig @@ -0,0 +1,40 @@ +config CPU_INTEL_BROADWELL + bool + help + Intel Broadwell and Haswell ULT CPU support. + +if CPU_INTEL_BROADWELL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select NO_FIXED_XIP_ROM_SIZE + select PARALLEL_MP + select SMP + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select TSC_SYNC_MFENCE + select UDELAY_TSC + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config IED_REGION_SIZE + hex + default 0x400000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +endif diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bdbdda4..2048d97 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,14 +8,9 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -25,14 +20,10 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE - select PARALLEL_MP select REG_SCRIPT select RTC - select SMP select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -40,11 +31,6 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE - select UDELAY_TSC config PCIEXP_ASPM bool @@ -90,18 +76,6 @@ hex default 0xf0000000 -config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406" -- To view, visit https://review.coreboot.org/c/coreboot/+/41931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Gerrit-Change-Number: 41931 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/broadwell: Add Kconfig
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41932 ) Change subject: northbridge/intel/broadwell: Add Kconfig ...................................................................... northbridge/intel/broadwell: Add Kconfig Move the northbridge Kconfig settings to the corresponding scope. Also, correct `initialse` to `initialize`, as fixed on Haswell. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/broadwell/Kconfig M src/northbridge/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/Kconfig 3 files changed, 121 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41932/1 diff --git a/src/northbridge/intel/broadwell/Kconfig b/src/northbridge/intel/broadwell/Kconfig new file mode 100644 index 0000000..3207a04 --- /dev/null +++ b/src/northbridge/intel/broadwell/Kconfig @@ -0,0 +1,119 @@ +config NORTHBRIDGE_INTEL_BROADWELL + def_bool n + select CACHE_MRC_SETTINGS + select CPU_INTEL_BROADWELL + select INTEL_GMA_ACPI + select MRC_SETTINGS_PROTECT + +if NORTHBRIDGE_INTEL_BROADWELL + +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialize memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DCACHE_RAM_BASE + hex + default 0xff7c0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x30000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config HAVE_MRC + bool "Add a Memory Reference Code binary" + help + Select this option to add a Memory Reference Code binary to + the resulting coreboot image. + + Note: Without this binary coreboot will not work + +if HAVE_MRC + +config MRC_FILE + string "Intel Memory Reference Code path and filename" + depends on HAVE_MRC + default "mrc.bin" + help + The filename of the file to use as Memory Reference Code binary. + +config MRC_BIN_ADDRESS + hex + default 0xfffa0000 + +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + +endif # HAVE_MRC + +config PRE_GRAPHICS_DELAY + int "Graphics initialization delay in ms" + default 0 + help + On some systems, coreboot boots so fast that connected monitors + (mostly TVs) won't be able to wake up fast enough to talk to the + VBIOS. On those systems we need to wait for a bit before executing + the VBIOS. + +config HAVE_REFCODE_BLOB + depends on ARCH_X86 + bool "An external reference code blob should be put into cbfs." + default n + help + The reference code blob will be placed into cbfs. + +if HAVE_REFCODE_BLOB + +config REFCODE_BLOB_FILE + string "Path and filename to reference code blob." + default "refcode.elf" + help + The path and filename to the file to be added to cbfs. + +endif # HAVE_REFCODE_BLOB + +endif diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 77e96ce..cbcc631 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_BROADWELL),y) bootblock-y += bootblock.c diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2048d97..e61bee8 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -9,8 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES - select CACHE_MRC_SETTINGS - select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -18,8 +16,7 @@ select HAVE_USBDEBUG select IOAPIC select INTEL_DESCRIPTOR_MODE_CAPABLE - select INTEL_GMA_ACPI - select MRC_SETTINGS_PROTECT + select NORTHBRIDGE_INTEL_BROADWELL select REG_SCRIPT select RTC select SOC_INTEL_COMMON @@ -52,98 +49,6 @@ bool default y -config BROADWELL_VBOOT_IN_BOOTBLOCK - depends on VBOOT - bool "Start verstage in bootblock" - default y - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - help - Broadwell can either start verstage in a separate stage - right after the bootblock has run or it can start it - after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which - needs to be located at a fixed offset. Therefore even with - a separate verstage starting after the bootblock that same - binary is used meaning a jump is made from RW to the RO region - and back to the RW region after the binary is done. - -config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config VGA_BIOS_ID - string - default "8086,0406" - -config DCACHE_RAM_BASE - hex - default 0xff7c0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE - must add up to a power of 2. - -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x30000 - help - The amount of cache-as-ram region required by the reference code. - -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - -config HAVE_MRC - bool "Add a Memory Reference Code binary" - help - Select this option to add a Memory Reference Code binary to - the resulting coreboot image. - - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel Memory Reference Code path and filename" - depends on HAVE_MRC - default "mrc.bin" - help - The filename of the file to use as Memory Reference Code binary. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -# The UEFI System Agent binary needs to be at a fixed offset in the flash -# and can therefore only reside in the COREBOOT fmap region -config RO_REGION_ONLY - string - depends on VBOOT - default "mrc.bin" - -endif # HAVE_MRC - -config PRE_GRAPHICS_DELAY - int "Graphics initialization delay in ms" - default 0 - help - On some systems, coreboot boots so fast that connected monitors - (mostly TVs) won't be able to wake up fast enough to talk to the - VBIOS. On those systems we need to wait for a bit before executing - the VBIOS. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n @@ -170,21 +75,4 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Gerrit-Change-Number: 41932 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/intel/wildcatpoint: Add Kconfig
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41933 ) Change subject: southbridge/intel/wildcatpoint: Add Kconfig ...................................................................... southbridge/intel/wildcatpoint: Add Kconfig Move the southbridge Kconfig settings to the corresponding scope. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I96424fa6b2521487a29fd624a394a21bc6e663b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig A src/southbridge/intel/wildcatpoint/Kconfig M src/southbridge/intel/wildcatpoint/Makefile.inc 3 files changed, 80 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41933/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index e61bee8..2556ee2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -1,78 +1,6 @@ config SOC_INTEL_BROADWELL bool + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT help Intel Broadwell and Haswell ULT support. - -if SOC_INTEL_BROADWELL - -config SOC_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select BOOT_DEVICE_SUPPORTS_WRITES - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select HAVE_SMI_HANDLER - select HAVE_SPI_CONSOLE_SUPPORT - select HAVE_USBDEBUG - select IOAPIC - select INTEL_DESCRIPTOR_MODE_CAPABLE - select NORTHBRIDGE_INTEL_BROADWELL - select REG_SCRIPT - select RTC - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SPI_FLASH - -config PCIEXP_ASPM - bool - default y - -config PCIEXP_AER - bool - default y - -config PCIEXP_COMMON_CLOCK - bool - default y - -config PCIEXP_CLK_PM - bool - default y - -config PCIEXP_L1_SUB_STATE - bool - default y - -config INTEL_PCH_UART_CONSOLE - bool "Use Serial IO UART for console" - default n - select DRIVERS_UART_8250MEM - -config INTEL_PCH_UART_CONSOLE_NUMBER - hex "Serial IO UART number to use for console" - default 0x0 - depends on INTEL_PCH_UART_CONSOLE - -config TTYS0_BASE - hex - default 0xd6000000 - depends on INTEL_PCH_UART_CONSOLE - -config EHCI_BAR - hex - default 0xd8000000 - -config SERIRQ_CONTINUOUS_MODE - bool - default y - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -endif diff --git a/src/southbridge/intel/wildcatpoint/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig new file mode 100644 index 0000000..6f8c29a --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/Kconfig @@ -0,0 +1,77 @@ +config SOUTHBRIDGE_INTEL_WILDCATPOINT + bool + help + Intel Wildcat Point and Lynx Point ULT PCH support. + +if SOUTHBRIDGE_INTEL_WILDCATPOINT + +config SOUTH_BRIDGE_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select BOOT_DEVICE_SUPPORTS_WRITES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_USBDEBUG + select IOAPIC + select INTEL_DESCRIPTOR_MODE_CAPABLE + select REG_SCRIPT + select RTC + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SPI_FLASH + +config PCIEXP_ASPM + bool + default y + +config PCIEXP_AER + bool + default y + +config PCIEXP_COMMON_CLOCK + bool + default y + +config PCIEXP_CLK_PM + bool + default y + +config PCIEXP_L1_SUB_STATE + bool + default y + +config INTEL_PCH_UART_CONSOLE + bool "Use Serial IO UART for console" + default n + select DRIVERS_UART_8250MEM + +config INTEL_PCH_UART_CONSOLE_NUMBER + hex "Serial IO UART number to use for console" + default 0x0 + depends on INTEL_PCH_UART_CONSOLE + +config TTYS0_BASE + hex + default 0xd6000000 + depends on INTEL_PCH_UART_CONSOLE + +config EHCI_BAR + hex + default 0xd8000000 + +config SERIRQ_CONTINUOUS_MODE + bool + default y + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +endif diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc index f1761f2..49a2094 100644 --- a/src/southbridge/intel/wildcatpoint/Makefile.inc +++ b/src/southbridge/intel/wildcatpoint/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y) romstage-y += early_pch.c romstage-y += early_smbus.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96424fa6b2521487a29fd624a394a21bc6e663b0 Gerrit-Change-Number: 41933 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/broadwell: Add ACPI
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41934 ) Change subject: northbridge/intel/broadwell: Add ACPI ...................................................................... northbridge/intel/broadwell: Add ACPI Move ACPI ASL files from the soc namespace to the northbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I8f6d8036dc2e875312c8f9b3604548e54ce66239 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/northbridge/intel/broadwell/acpi/broadwell.asl R src/northbridge/intel/broadwell/acpi/ctdp.asl R src/northbridge/intel/broadwell/acpi/pci_irqs.asl 7 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41934/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index c0f4d9f..0fa2d17 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 7770198..ad5ca61 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -25,7 +25,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index f9d4fe8..6453d7a 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -25,7 +25,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 5053a7d..68e97c3 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -21,7 +21,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <northbridge/intel/broadwell/acpi/broadwell.asl> #include <soc/intel/broadwell/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/systemagent.asl rename to src/northbridge/intel/broadwell/acpi/broadwell.asl diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/northbridge/intel/broadwell/acpi/ctdp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ctdp.asl rename to src/northbridge/intel/broadwell/acpi/ctdp.asl diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/northbridge/intel/broadwell/acpi/pci_irqs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pci_irqs.asl rename to src/northbridge/intel/broadwell/acpi/pci_irqs.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/41934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f6d8036dc2e875312c8f9b3604548e54ce66239 Gerrit-Change-Number: 41934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/intel/wildcatpoint: Add ACPI
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41935 ) Change subject: southbridge/intel/wildcatpoint: Add ACPI ...................................................................... southbridge/intel/wildcatpoint: Add ACPI Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 0fa2d17..315b558 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -10,13 +10,13 @@ 0x20110725 // OEM revision ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl> // Thermal handler #include "acpi/thermal.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -25,7 +25,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index ad5ca61..396f105 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ #include <variant/acpi/thermal.asl> // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 6453d7a..119ab89 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 68e97c3..e0a07a9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -10,10 +10,10 @@ 0x20160115 /* OEM revision */ ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl> /* Global NVS and variables */ - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -22,7 +22,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/southbridge/intel/wildcatpoint/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/southbridge/intel/wildcatpoint/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/southbridge/intel/wildcatpoint/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/southbridge/intel/wildcatpoint/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/southbridge/intel/wildcatpoint/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/southbridge/intel/wildcatpoint/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/southbridge/intel/wildcatpoint/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/southbridge/intel/wildcatpoint/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/southbridge/intel/wildcatpoint/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/southbridge/intel/wildcatpoint/acpi/platform.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/platform.asl rename to src/southbridge/intel/wildcatpoint/acpi/platform.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/southbridge/intel/wildcatpoint/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/southbridge/intel/wildcatpoint/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/southbridge/intel/wildcatpoint/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/southbridge/intel/wildcatpoint/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/southbridge/intel/wildcatpoint/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/southbridge/intel/wildcatpoint/acpi/xhci.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/41935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Gerrit-Change-Number: 41935 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020