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Change in coreboot[master]: coreinfo: Add support for link time optimization
by Jacob Garber (Code Review) 03 Nov '20

03 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38293 ) Change subject: coreinfo: Add support for link time optimization ...................................................................... coreinfo: Add support for link time optimization This introduces a Kconfig option for compiling coreinfo with LTO. This option can be used independently of LTO in libpayload, though will benefit most if that is enabled as well. If both are enabled, the final size of coreinfo.elf is reduced from 125K to 122K. Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/coreinfo/Kconfig M payloads/coreinfo/Makefile 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38293/1 diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index fd4c1b4..5fb17bb 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -56,6 +56,13 @@ help The version number of this payload. +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 34c45d9..6452c00 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -90,9 +90,13 @@ include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Gerrit-Change-Number: 38293 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

8 18

Change in coreboot[master]: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 03 Nov '20

03 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45418 ) Change subject: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Signed-off-by: Manideep Kurumella <mkurumel(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/soc.c 3 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45418/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bb..b369d55 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,6 +9,7 @@ DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..80df6c8 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -52,6 +52,7 @@ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem, 0x86000000, 0x8C00000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..30ad967 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -15,6 +15,8 @@ REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + reserved_ram_resource(dev, 3, (uintptr_t)_dram_modem / KiB, + REGION_SIZE(dram_modem) / KiB); } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Gerrit-Change-Number: 45418 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block
by Subrata Banik (Code Review) 02 Nov '20

02 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45337 ) Change subject: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block ...................................................................... soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block This patch removes all redundant reset code block and make use of common pch/reset code block. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f --- M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/reset.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/elkhartlake/Makefile.inc D src/soc/intel/elkhartlake/reset.c M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/reset.c M src/soc/intel/jasperlake/Makefile.inc D src/soc/intel/jasperlake/reset.c M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/reset.c M src/soc/intel/tigerlake/Makefile.inc D src/soc/intel/tigerlake/reset.c 13 files changed, 2 insertions(+), 228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45337/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..7d829e9 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += i2c.c romstage-y += lpc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -45,7 +44,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/cannonlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..a2f38cc 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOC_INTEL_COMMON_PCH_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..f642598 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c deleted file mode 100644 index 107db5a..0000000 --- a/src/soc/intel/elkhartlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 05f4846..58944a1 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -25,7 +25,6 @@ romstage-y += espi.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -38,7 +37,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/icelake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..dd5b249 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c + ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +39,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/jasperlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index de516c1..e52ef85 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -56,7 +55,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c deleted file mode 100644 index 1076ad2..0000000 --- a/src/soc/intel/skylake/reset.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/me.h> -#include <soc/pm.h> - -static void do_force_global_reset(void) -{ - /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] - */ - pmc_global_reset_enable(true); - - /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ - do_full_reset(); -} - -void do_global_reset(void) -{ - if (!send_global_reset()) { - /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ - do_force_global_reset(); - } -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..28e09ad 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/tigerlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Gerrit-Change-Number: 45337 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

11 77

Change in coreboot[master]: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
by Patrick Rudolph (Code Review) 02 Nov '20

02 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44673 ) Change subject: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode ...................................................................... cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode * Use heap for linker script calculated constant to fix relocation symbols in mixed assembly code. * Work around a strange bug that causes the CPU to halt when accessing MMX registers in long mode Tested on HPZ220: * Still boots in x86_32. Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 40 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44673/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b24f101..481cbee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -9,6 +9,27 @@ .global bootblock_pre_c_entry +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#ifdef __x86_64__ +rom_mtrr_mask: +.quad _rom_mtrr_mask + +rom_mtrr_base: +.quad _rom_mtrr_base + +car_mtrr_mask: +.quad _car_mtrr_mask +#else +rom_mtrr_mask: +.long _rom_mtrr_mask + +rom_mtrr_base: +.long _rom_mtrr_base + +car_mtrr_mask: +.long _car_mtrr_mask +#endif + .code32 _cache_as_ram_setup: @@ -83,7 +104,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -96,20 +116,20 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -208,17 +228,24 @@ the pushes below. */ andl $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ +#ifdef __x86_64__ + /* + * BUG: On some x86 platforms acessing MMX register in long mode + * causes a crash. Retrieve them here and then switch to long mode. + */ + movd %mm2, %eax + push %eax + movd %mm1, %eax /* tsc */ + push %eax + movd %mm0, %eax + push %eax + xorl %eax, %eax + push %eax /* BIST */ + #include <cpu/x86/64bit/entry64.inc> -#ifdef __x86_64__ - - movd %mm2, %rdi - shld %rdi, 32 - movd %mm1, %rsi - or %rsi, %rdi /* tsc */ - - movd %mm0, %rsi /* BIST */ + pop %rsi /* BIST */ + pop %rdi /* tsc */ #else subl $4, %esp /* push TSC and BIST to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Gerrit-Change-Number: 44673 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: cpu/x86/smm: Pass smm.ld trought src-to-obj
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44321 ) Change subject: cpu/x86/smm: Pass smm.ld trought src-to-obj ...................................................................... cpu/x86/smm: Pass smm.ld trought src-to-obj This allows for ccopts symbols and preprocessor to be used inside the smm.ld linker script. Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44321/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a..bbd96c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -16,7 +16,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $^) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,8 +72,10 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Gerrit-Change-Number: 44321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel/fsp-car: Use the coreboot defined stack
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37278 ) Change subject: soc/intel/fsp-car: Use the coreboot defined stack ...................................................................... soc/intel/fsp-car: Use the coreboot defined stack The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37278/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index ec43311..d7ef834 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,7 +87,7 @@ jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl _ecar_stack, %esp /* coreboot assumes CAR region will be zero */ cld -- To view, visit https://review.coreboot.org/c/coreboot/+/37278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Gerrit-Change-Number: 37278 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: ec/hp/kbc1126: Support using a different GPE
by Iru Cai (vimacs) (Code Review) 02 Nov '20

02 Nov '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45576 to review the following change. Change subject: ec/hp/kbc1126: Support using a different GPE ...................................................................... ec/hp/kbc1126: Support using a different GPE HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but with a different GPE, so add a Kconfig option to support using a different GPE. Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/acpi/ec.asl 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45576/1 diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index fa2414a..957fdd5 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -10,6 +10,11 @@ depends on EC_HP_KBC1126 default y +config EC_HP_KBC1126_GPE + hex + depends on EC_HP_KBC1126 + default 0x16 + if EC_HP_KBC1126_ECFW_IN_CBFS comment "Please select the following otherwise your laptop cannot be powered on." diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index e5752a8..81bdff9 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -4,7 +4,7 @@ { Name (_HID, EISAID("PNP0C09")) Name (_UID, 0) - Name (_GPE, 0x16) + Name (_GPE, CONFIG_EC_HP_KBC1126_GPE) Name (_CRS, ResourceTemplate () { -- To view, visit https://review.coreboot.org/c/coreboot/+/45576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b Gerrit-Change-Number: 45576 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: x86: Add a fake SoC along with a board for build testing
by Nico Huber (Code Review) 31 Oct '20

31 Oct '20

Hello Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45710 to review the following change. Change subject: x86: Add a fake SoC along with a board for build testing ...................................................................... x86: Add a fake SoC along with a board for build testing This fake SoC code should serve as a minimal example how a buildable code base can look like. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the fake code itself is build-tested, it should advance with coreboot and can't rot like documentation might. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A src/mainboard/fake/Kconfig A src/mainboard/fake/Kconfig.name A src/mainboard/fake/x86/Kconfig A src/mainboard/fake/x86/Kconfig.name A src/mainboard/fake/x86/board_info.txt A src/mainboard/fake/x86/devicetree.cb A src/soc/fake/Kconfig A src/soc/fake/x86/Kconfig A src/soc/fake/x86/Makefile.inc A src/soc/fake/x86/cache_as_ram.S A src/soc/fake/x86/chip.c A src/soc/fake/x86/exit_car.S A src/soc/fake/x86/romstage.c A src/soc/fake/x86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45710/1 diff --git a/src/mainboard/fake/Kconfig b/src/mainboard/fake/Kconfig new file mode 100644 index 0000000..2c0431a --- /dev/null +++ b/src/mainboard/fake/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_FAKE + +choice + prompt "Mainboard model" + +source "src/mainboard/fake/*/Kconfig.name" + +endchoice + +source "src/mainboard/fake/*/Kconfig" + +config MAINBOARD_VENDOR + default "Fake" + +endif # VENDOR_FAKE diff --git a/src/mainboard/fake/Kconfig.name b/src/mainboard/fake/Kconfig.name new file mode 100644 index 0000000..3beb2c0a --- /dev/null +++ b/src/mainboard/fake/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FAKE + bool "Fake boards for build testing only" diff --git a/src/mainboard/fake/x86/Kconfig b/src/mainboard/fake/x86/Kconfig new file mode 100644 index 0000000..db0746b --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig @@ -0,0 +1,15 @@ +if MAINBOARD_FAKE_X86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_FAKE_X86 + select MISSING_BOARD_RESET + select BOARD_ROMSIZE_KB_256 # MTRR code minimum + +config MAINBOARD_DIR + default "fake/x86" + +config MAINBOARD_PART_NUMBER + default "Fake86" + +endif diff --git a/src/mainboard/fake/x86/Kconfig.name b/src/mainboard/fake/x86/Kconfig.name new file mode 100644 index 0000000..a579d03 --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig.name @@ -0,0 +1,9 @@ +config MAINBOARD_FAKE_X86 + bool "x86 fake board" + help + This fake mainboard along with the fake/x86 SoC should serve + as a minimal example how a buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. diff --git a/src/mainboard/fake/x86/board_info.txt b/src/mainboard/fake/x86/board_info.txt new file mode 100644 index 0000000..c778859 --- /dev/null +++ b/src/mainboard/fake/x86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/fake/x86/devicetree.cb b/src/mainboard/fake/x86/devicetree.cb new file mode 100644 index 0000000..38e82bd --- /dev/null +++ b/src/mainboard/fake/x86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/fake/x86 + + device domain 0 on + end + +end diff --git a/src/soc/fake/Kconfig b/src/soc/fake/Kconfig new file mode 100644 index 0000000..b498e7c --- /dev/null +++ b/src/soc/fake/Kconfig @@ -0,0 +1 @@ +source "src/soc/fake/*/Kconfig" diff --git a/src/soc/fake/x86/Kconfig b/src/soc/fake/x86/Kconfig new file mode 100644 index 0000000..686a8d5 --- /dev/null +++ b/src/soc/fake/x86/Kconfig @@ -0,0 +1,26 @@ +config SOC_FAKE_X86 + bool + help + This fake SoC code should serve as a minimal example how a + buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. + +if SOC_FAKE_X86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/fake/x86/Makefile.inc b/src/soc/fake/x86/Makefile.inc new file mode 100644 index 0000000..0780607 --- /dev/null +++ b/src/soc/fake/x86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_FAKE_X86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/fake/x86/cache_as_ram.S b/src/soc/fake/x86/cache_as_ram.S new file mode 100644 index 0000000..a350143 --- /dev/null +++ b/src/soc/fake/x86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/fake/x86/chip.c b/src/soc/fake/x86/chip.c new file mode 100644 index 0000000..a5ec309 --- /dev/null +++ b/src/soc/fake/x86/chip.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations soc_fake_x86_ops = { NULL }; diff --git a/src/soc/fake/x86/exit_car.S b/src/soc/fake/x86/exit_car.S new file mode 100644 index 0000000..0f1b227 --- /dev/null +++ b/src/soc/fake/x86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/fake/x86/romstage.c b/src/soc/fake/x86/romstage.c new file mode 100644 index 0000000..91074b2 --- /dev/null +++ b/src/soc/fake/x86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/fake/x86/timer.c b/src/soc/fake/x86/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/fake/x86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Gerrit-Change-Number: 45710 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: [Do not merge] Separate power resource for VCM
by Daniel Kang (Code Review) 31 Oct '20

31 Oct '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45159 ) Change subject: [Do not merge] Separate power resource for VCM ...................................................................... [Do not merge] Separate power resource for VCM WIP patch for discussion. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45159/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index dad762a..ad0b782 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -334,6 +334,54 @@ }) } + PowerResource (VCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* VCPR_ON_: VCM Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull PWREN high */ + STXS(GPP_H20) + Sleep(2) /* reset pulse width */ + + /* Pull RST high */ + STXS(GPP_F15) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* VCPR_OFF: VCM Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull PWREN low */ + CTXS(GPP_H20) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (VCM0) { Name (_HID, "PRP0001") /* _HID: Hardware ID */ @@ -356,11 +404,11 @@ }) Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { - RCPR + VCPR }) Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { - RCPR + VCPR }) Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { -- To view, visit https://review.coreboot.org/c/coreboot/+/45159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 Gerrit-Change-Number: 45159 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

6 37

Change in coreboot[master]: soc/intel/broadwell: Relocate CPU .c files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41927 ) Change subject: soc/intel/broadwell: Relocate CPU .c files ...................................................................... soc/intel/broadwell: Relocate CPU .c files Haswell and Broadwell are rather similar, and could share some code. However, Haswell is split into cpu/northbridge/southbridge folders, whereas all of Broadwell is crammed into the soc namespace. We will split Broadwell and then fuse it with Haswell in multiple commits. To begin with, move Broadwell source code files into a folder under the corresponding cpu scope, without changing any of their contents. Note that headers and Kconfig still reside inside the soc namespace. This is temporary and will be accounted for in subsequent commits. Change-Id: Ic2f719ea7585ec724c52950e76e5f52bdc1d6c43 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Makefile.inc A src/cpu/intel/broadwell/acpi.c R src/cpu/intel/broadwell/bootblock.c R src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/chip.c R src/cpu/intel/broadwell/cpu.c R src/cpu/intel/broadwell/cpu_info.c R src/cpu/intel/broadwell/romstage.c R src/cpu/intel/broadwell/smmrelocate.c R src/cpu/intel/broadwell/tsc_freq.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/Makefile.inc 13 files changed, 667 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41927/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19..21dc291 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc new file mode 100644 index 0000000..453b879 --- /dev/null +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -0,0 +1,38 @@ +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/intel/common + +bootblock-y += bootblock.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S + +romstage-y += ../../../cpu/intel/car/romstage.c +romstage-y += broadwell_early_init.c + +ramstage-y += acpi.c + +ramstage-y += chip.c + +ramstage-y += cpu.c +ramstage-y += cpu_info.c +smm-y += cpu_info.c + +romstage-y += romstage.c + +ramstage-y += smmrelocate.c + +bootblock-y += tsc_freq.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-y += tsc_freq.c +postcar-y += tsc_freq.c +verstage-y += tsc_freq.c + +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S + +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c new file mode 100644 index 0000000..316b85a --- /dev/null +++ b/src/cpu/intel/broadwell/acpi.c @@ -0,0 +1,628 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <device/pci_ops.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cpu/intel/turbo.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/systemagent.h> +#include <soc/intel/broadwell/chip.h> +#include <intelblocks/cpulib.h> + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +static int cstate_set_non_s0ix[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT +}; + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG(CHROMEOS) + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); +#if CONFIG(EC_GOOGLE_CHROMEEC) + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static void generate_C_state_entries(void) +{ + acpi_cstate_t map[3]; + int *set; + int i; + + config_t *config = config_of_soc(); + + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix; + + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CPU_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; + + /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar + && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* VTVC0BAR has to be set, enabled, and in 32-bit space */ + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci >= 20) + flags |= MP_IRQ_POLARITY_LOW; + else + flags |= MP_IRQ_POLARITY_HIGH; + + /* SCI */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); + + return current; +} diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/cpu/intel/broadwell/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/cpu.c rename to src/cpu/intel/broadwell/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/cpu/intel/broadwell/broadwell_early_init.c similarity index 100% rename from src/soc/intel/broadwell/romstage/cpu.c rename to src/cpu/intel/broadwell/broadwell_early_init.c diff --git a/src/soc/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c similarity index 100% rename from src/soc/intel/broadwell/chip.c rename to src/cpu/intel/broadwell/chip.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c similarity index 100% rename from src/soc/intel/broadwell/cpu.c rename to src/cpu/intel/broadwell/cpu.c diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c similarity index 100% rename from src/soc/intel/broadwell/cpu_info.c rename to src/cpu/intel/broadwell/cpu_info.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/cpu/intel/broadwell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/romstage.c rename to src/cpu/intel/broadwell/romstage.c diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c similarity index 100% rename from src/soc/intel/broadwell/smmrelocate.c rename to src/cpu/intel/broadwell/smmrelocate.c diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/cpu/intel/broadwell/tsc_freq.c similarity index 100% rename from src/soc/intel/broadwell/tsc_freq.c rename to src/cpu/intel/broadwell/tsc_freq.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index be854b2..7e502ec 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,27 +1,11 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/intel/common -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c -bootblock-y += ../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../cpu/x86/early_reset.S -ramstage-y += acpi.c ramstage-y += adsp.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += cpu_info.c -smm-y += cpu_info.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c ramstage-y += gpio.c @@ -55,14 +39,7 @@ ramstage-y += smbus.c ramstage-y += smi.c smm-y += smihandler.c -ramstage-y += smmrelocate.c ramstage-y += systemagent.c -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c bootblock-y += usb_debug.c romstage-y += usb_debug.c ramstage-y += usb_debug.c @@ -70,12 +47,8 @@ ramstage-y += xhci.c smm-y += xhci.c -postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S - ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin - CPPFLAGS_common += -Isrc/soc/intel/broadwell/include # If an MRC file is an ELF file determine the entry address and first loadable diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index a53cd95..fb6c56a 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,10 +1,7 @@ -romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c -romstage-y += romstage.c romstage-y += smbus.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f719ea7585ec724c52950e76e5f52bdc1d6c43 Gerrit-Change-Number: 41927 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020