coreboot-gerrit September 2020

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Change in coreboot[master]: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45813 ) Change subject: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration ...................................................................... soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration This prototype will be used outside of soc/amd. Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/smi_util.c M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smi_util.c 5 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45813/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 1073d03..6cf6f82 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -197,5 +197,8 @@ /* Return the SMM save state revision. The revision can be fetched from the smm savestate which is always at the same offset downward from the top of the save state. */ uint32_t smm_revision(void); +/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2). + On AMD systems it is sometimes configurable. */ +uint16_t pm_acpi_smi_cmd_port(void); #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5..ee47676 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -213,7 +213,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index f7cacea..15bba0f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -211,7 +211,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Gerrit-Change-Number: 45813 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP] SMM save states
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44323 ) Change subject: [WIP] SMM save states ...................................................................... [WIP] SMM save states Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smm.ld A src/include/cpu/x86/save_state.h M src/lib/program.ld M src/southbridge/intel/i82801ix/smihandler.c 8 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44323/1 diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index a49b796..df73ae7 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +smm-y += em64t101_save_state.c diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c new file mode 100644 index 0000000..404906b --- /dev/null +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/intel/em64t101_save_state.h> + +static void *em64t101_get_reg_base(const enum cpu_reg reg, const int node) +{ + const em64t101_smm_state_save_area_t *save_state = (const em64t101_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int em64t101_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = em64t101_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int em64t101_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return em64t101_get_set(GET, reg, node, out, length); +} + +static int em64t101_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return em64t101_get_set(SET, reg, node, in, length); +} + +static int em64t101_apmc_node(u8 cmd) +{ + em64t101_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030101, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops __smm_save_state_ops = { + .revision_table = revisions, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, + .apmc_node = em64t101_apmc_node, +}; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index bbd96c6..2b3e073 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -28,6 +28,8 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c new file mode 100644 index 0000000..7c757e3 --- /dev/null +++ b/src/cpu/x86/smm/save_state.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> + +static struct smm_save_state_ops *save_state; + +/* Returns -1 on failure, 0 on success */ +static int init_save_state(void) +{ + const uint32_t revision = smm_revision(); + struct smm_save_state_ops *ops; + static bool initialized = false; + + if (initialized) + return 0; + + for (ops = _smm_save_state_ops; ops < _esmm_save_state_ops; ops++) { + const uint32_t *rev; + for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++) + if (*rev == revision) { + save_state = ops; + initialized = true; + return 0; + } + } + + return -1; +} + +int get_apmc_node(u8 cmd) +{ + if (init_save_state()) + return -1; + + return save_state->apmc_node(cmd); +} + +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + if (init_save_state()) + return -1; + + return save_state->get_reg(reg, node, out, length); +} diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 2f46975..39afee4 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -25,6 +25,11 @@ /* C read-only data of the SMM handler */ . = ALIGN(16); + + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; + *(.rodata) *(.rodata.*) diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h new file mode 100644 index 0000000..b97890b --- /dev/null +++ b/src/include/cpu/x86/save_state.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_X86_SAVE_STATE_H__ +#define __CPU_X86_SAVE_STATE_H__ + +#include <stdint.h> + +#if ENV_SMM +#define __smm_save_state_ops __attribute__((used, __section__(".rodata.smm_ops"))) +#else +#define __smm_save_state_ops __attribute__((unused)) +#endif + +enum cpu_reg { + RAX, + RBX, + RCX, + RDX +}; + +#define SMM_REV_INVALID 0xffffffff + +struct smm_save_state_ops { + const uint32_t *revision_table; + /* Accessors for CPU registers in the SMM save state + Returns -1 on failure, 0 on success */ + int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + int(*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + /* Returns -1 on failure, the node on which the 'cmd' was send on success */ + int(*apmc_node)(u8 cmd); +}; + +/** start of compile time generated pci driver array */ +extern struct smm_save_state_ops _smm_save_state_ops[]; +/** end of compile time generated pci driver array */ +extern struct smm_save_state_ops _esmm_save_state_ops[]; + +int get_apmc_node(u8 cmd); +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + +#endif /* __CPU_X86_SAVE_STATE_H__ */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 88a3126..1894ae0 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -44,6 +44,13 @@ _ecpu_drivers = .; #endif +#if ENV_SMM || ENV_RMODULE + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; +#endif + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); *(.rodata); *(.rodata.*); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f..9b37f05 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,6 +3,7 @@ #include <types.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> #include "i82801ix.h" @@ -31,6 +32,8 @@ return 1; /* IO trap handled */ } + get_apmc_node(5); + /* Not handled */ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Gerrit-Change-Number: 44323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44322 ) Change subject: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 ...................................................................... cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 The SMM_ASEG code only supports up to 4 CPUs, so assert this at buildtime. Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm.ld 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44322/1 diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index af5968d..2f46975 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -2,6 +2,9 @@ /* Maximum number of CPUs/cores */ CPUS = 4; + +_ = ASSERT(CPUS > CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); + ENTRY(smm_handler_start); SECTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/44322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Gerrit-Change-Number: 44322 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/smm/smihandler.c: Simplify smm revision handling
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45471 ) Change subject: cpu/x86/smm/smihandler.c: Simplify smm revision handling ...................................................................... cpu/x86/smm/smihandler.c: Simplify smm revision handling The ASEG smihandler bails out if an unsupported SMM save state revision is detected. Now we have code to find the SMM save state depending on the SMM save state revision so reuse this to do the same. This also increases the loglevel when bailing out of SMM due to unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING, given that the system likely still boots but won't have a functioning smihandler. Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c 1 file changed, 3 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45471/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 077fa8d..dea4cf3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -14,23 +14,6 @@ #include <spi-generic.h> #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -162,9 +145,6 @@ void smi_handler(void) { unsigned int node; - const uint32_t smm_rev = smm_revision(); - smm_state_save_area_t state_save; - u32 smm_base = SMM_BASE; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -190,36 +170,9 @@ printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_rev) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + if (smm_get_save_state(node) == NULL) { + printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); + printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Gerrit-Change-Number: 45471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: drivers/uart: Override uart base address
by Bryant Ou (Code Review) 09 Nov '20

09 Nov '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45405 ) Change subject: drivers/uart: Override uart base address ...................................................................... drivers/uart: Override uart base address Add CONFIG_UART_OVERRIDE_BASE_ADDR to select the function, platform overrides the base address by providing a uart_platform_base routine. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a --- M src/drivers/uart/Kconfig M src/drivers/uart/uart8250io.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45405/1 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 41b870f..9cbb359 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -33,6 +33,13 @@ Set to "y" when the platform overrides the uart_platform_refclk routine. +config UART_OVERRIDE_BASE_ADDR + bool + default n + help + Set to "y" when the platform overrides the base address by providing + a uart_platform_base routine. + config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index d0841de..c5317af 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -75,6 +75,7 @@ ENABLE_TRACE; } +#if !CONFIG(UART_OVERRIDE_BASE_ADDR) static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; uintptr_t uart_platform_base(unsigned int idx) @@ -83,6 +84,7 @@ return bases[idx]; return 0; } +#endif void uart_init(unsigned int idx) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a Gerrit-Change-Number: 45405 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

9 24

Change in coreboot[master]: mb/ocp/deltalake: Insert IO port in linux command line
by Bryant Ou (Code Review) 06 Nov '20

06 Nov '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45410 ) Change subject: mb/ocp/deltalake: Insert IO port in linux command line ...................................................................... mb/ocp/deltalake: Insert IO port in linux command line Search "uart8250,io," string in CONFIG_LINUX_COMMAND_LINE, then insert uart base address which defined in VPD. Tested=On OCP Delta Lake, payload use correct uart base address to output messages via VPD variable. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I8747a23c7246aabe8c01ad5be668e1672b586f2c --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/ramstage.c 2 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45410/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 5671664..0ab8bbb 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -54,4 +54,10 @@ bool default y +config LINUX_COMMAND_LINE_OVERRIDE + bool + default y + help + Override linux command line by using VPD. + endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..115f7d3 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -10,6 +10,7 @@ #include <soc/ramstage.h> #include <soc/soc_util.h> #include <stdio.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <device/pci_def.h> @@ -18,10 +19,13 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <cpxsp_dl_gpio.h> - +#include <program_loading.h> +#include <drivers/vpd/vpd.h> +#include "vpd.h" #include "ipmi.h" #define SLOT_ID_LEN 2 +#define COMMAND_LINE_LOC 0x91000 extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; @@ -285,3 +289,68 @@ } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); + +#if (CONFIG(LINUX_COMMAND_LINE_OVERRIDE)) +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + char *port; + char *dupstr = strdup((char*)start); + const char s[] = {"uart8250,io,"}; + char *new = NULL; + char *p; + char *slice[10]; + char *found; + char *pre; + char *t1; + char *t2; + int count = 0; + int i; + int c; + int len; + int pos; + + /* Add IO port into linux command line */ + if (start == COMMAND_LINE_LOC) { + port = malloc(VPD_LEN); + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) { + port = strconcat(port, ","); + } else { + printk(BIOS_ERR, "UART_IOPORT is not found in VPD\n"); + port = strconcat(UART_IOPORT_DEFAULT, ","); + } + strcpy(new, ""); + for (p = strtok(dupstr, " "); p; p = strtok(NULL, " ")) { + slice[count] = p; + count++; + } + for (i = 0; i < count; i++) { + len = strlen(slice[i]); + found = strstr(slice[i], s); + if (found != NULL) { + pos = found - slice[i] + strlen(s); + t1 = malloc(pos); + for (c = 0; c < pos; c++) { + *(t1 + c) = *(slice[i] + c); + } + *(t1 + c) = '\0'; + pre = strconcat(t1, port); + free(t1); + t2 = malloc(len - pos + 2); + for (c = 0; c < (len - pos + 1); c++) { + *(t2 + c) = *((slice[i] + pos) + c); + } + *(t2 + c) = '\0'; + pre = strconcat(pre, t2); + free(t2); + slice[i] = strdup(pre); + } + new = strconcat(new, slice[i]); + if (i < count - 1) + new = strconcat(new, " "); + } + free(port); + memset((uint8_t*)start, 0, size); + memcpy((uint8_t*)start, new, strlen(new)); + } +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8747a23c7246aabe8c01ad5be668e1672b586f2c Gerrit-Change-Number: 45410 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/msi/ms7707/Kconfig: Drop invalid defaults
by Angel Pons (Code Review) 06 Nov '20

06 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45672 ) Change subject: mb/msi/ms7707/Kconfig: Drop invalid defaults ...................................................................... mb/msi/ms7707/Kconfig: Drop invalid defaults The PCI ID corresponds to the iGPU, which is disabled in the devicetree. Also, the VBIOS file does not exist at the specified location. Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/msi/ms7707/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45672/1 diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index e6095ba..93a43f9 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -33,12 +33,4 @@ hex default 0x200000 -config VGA_BIOS_FILE - string - default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vgabios.bin" - -config VGA_BIOS_ID - string - default "8086,0102" - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Gerrit-Change-Number: 45672 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/rockchip: port make_idb.py to python3
by Stefan Reinauer (Code Review) 05 Nov '20

05 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42319 ) Change subject: util/rockchip: port make_idb.py to python3 ...................................................................... util/rockchip: port make_idb.py to python3 converted with 2to3 and manually changed shebang to reflect python3. Tested by calling the script on the command line. Change-Id: I0e399c491ab07cd3e7fda24231cf3f7611b341e3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/rockchip/make_idb.py 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42319/1 diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12cd130..4f04676 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: BSD-2-Clause import struct @@ -7,10 +7,10 @@ class IDBTool: def __init__(self): - print "Initialize IDBTool" + print("Initialize IDBTool") def p_rc4(self, buf, length): - key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) + key = (124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17) K = key * 16 S = [i for i in range(256)] @@ -79,7 +79,7 @@ fout.write(''.join(idblock)) fout.write(''.join(blank)) - for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + for s in range(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) fout.write(''.join(blank)) else: @@ -90,11 +90,11 @@ sys.exit("Failed to write data to : " + to_file) finally: fout.close() - print "DONE" + print("DONE") def usage(): - print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" - print " --chip: default is RK32" + print("Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in") + print(" --chip: default is RK32") if __name__ == '__main__': rc4_flag = align_flag = False -- To view, visit https://review.coreboot.org/c/coreboot/+/42319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e399c491ab07cd3e7fda24231cf3f7611b341e3 Gerrit-Change-Number: 42319 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/exynos: Port *_cksum.py to python3
by Stefan Reinauer (Code Review) 05 Nov '20

05 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42321 ) Change subject: util/exynos: Port *_cksum.py to python3 ...................................................................... util/exynos: Port *_cksum.py to python3 Manually changed shebang to reflect python3, no further porting needed. Tested by calling the scripts on the command line. Change-Id: I116696576081460a7d503ee4a032c5430a430888 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/exynos/fixed_cksum.py M util/exynos/variable_cksum.py 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42321/1 diff --git a/util/exynos/fixed_cksum.py b/util/exynos/fixed_cksum.py index c6a9ddae..25537de 100755 --- a/util/exynos/fixed_cksum.py +++ b/util/exynos/fixed_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py index 62a76cc..f908049 100755 --- a/util/exynos/variable_cksum.py +++ b/util/exynos/variable_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause -- To view, visit https://review.coreboot.org/c/coreboot/+/42321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I116696576081460a7d503ee4a032c5430a430888 Gerrit-Change-Number: 42321 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Fix `PcieClkSrcUsage` setting
by Felix Singer (Code Review) 04 Nov '20

04 Nov '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39795 to review the following change. Change subject: soc/intel/cnl: Fix `PcieClkSrcUsage` setting ...................................................................... soc/intel/cnl: Fix `PcieClkSrcUsage` setting Remove unnecessary for-loop because the setting gets overwritten with memcpy afterwards. Change-Id: Idb2192e68e29ae53fcdd0775ac7fd6cea2930a0e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39795/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4634806..bbacfc1 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -320,10 +320,6 @@ params->PchCnviMode = 0; #endif /* PCI Express */ - for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { - if (config->PcieClkSrcUsage[i] == 0) - config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; - } memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, -- To view, visit https://review.coreboot.org/c/coreboot/+/39795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb2192e68e29ae53fcdd0775ac7fd6cea2930a0e Gerrit-Change-Number: 39795 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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