coreboot-gerrit September 2020

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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45555 ) Change subject: mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'ec.asl' to ASL 2.0 syntax Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/ec.asl 1 file changed, 89 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45555/1 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae644..ac637d7 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -87,16 +87,16 @@ Method (_Q01, 0) { Notify (\_SB.CP00, 0x80) - If(ADP) { - Store(1, \_SB.AC.ACST) - TRAP(0xe3) - Store(1, PWRS) - TRAP(0x2b) + If (ADP) { + \_SB.AC.ACST = 1 + TRAP (0xe3) + PWRS = 1 + TRAP (0x2b) } Else { - Store(0, \_SB.AC.ACST) - Notify(\_SB.AC, 0x80) - Notify(\_SB.BAT0, 0x80) - Store(0, PWRS) + \_SB.AC.ACST = 0 + Notify (\_SB.AC, 0x80) + Notify (\_SB.BAT0, 0x80) + PWRS = 0 TRAP(0x2b) } @@ -107,7 +107,7 @@ Method (_Q02, 0) { - If(BAT) { + If (BAT) { Notify(\_SB.BAT0, 0x00) Notify(\_SB.AC, 0x80) } Else { @@ -132,7 +132,7 @@ { TRAP(0xe0) - If (LEqual(RTCF, 0x00)) { + If (RTCF == 0x00) { Notify(LID0, 0x80) } else { TRAP(0xc1) @@ -172,25 +172,25 @@ Method (_Q24, 0) { - Store(0x3f, HOTK) - If(IGDS) { + HOTK = 0x3f + If (IGDS) { Notify (\_SB.PCI0.GFX0, 0x82) } Else { - TRAP(0xE1) + TRAP (0xE1) } Notify (\_SB.ECO, 0x85) } Method (_Q25, 0) { - Store(0x40, HOTK) + HOTK = 0x40 TRAP(0xe1) Notify(\_SB.ECO, 0x86) } Method (_Q26, 0) { - Store(0x41, HOTK) + HOTK = 0x41 TRAP(0xe1) Notify(\_SB.ECO, 0x87) } @@ -212,7 +212,7 @@ Method (_Q2A, 0) { - Store(0x57, HOTK) + HOTK = 0x57 TRAP(0xe1) Notify(\_SB.ECO, 0x8b) } @@ -225,7 +225,7 @@ Method (_Q2C, 0) { - Store(0x59, HOTK) + HOTK = 0x59 TRAP(0xe1) } @@ -241,25 +241,25 @@ Method (_Q3A, 0) { - Store(1, BRTL) + BRTL = 1 Notify(\_SB.ECO, 0x93) } Method (_Q3B, 0) { - Store(0, BRTL) + BRTL = 0 Notify(\_SB.ECO, 0x93) } Method (_Q3C, 0) { - Store(1, SUN) + SUN = 1 Notify(\_SB.ECO, 0x92) } Method (_Q3D, 0) { - Store(0, SUN) + SUN = 0 Notify(\_SB.ECO, 0x92) } @@ -302,14 +302,14 @@ Method (_Q48, 0) { TRAP(0xd2) // Check AC Status - Store (1, ODDS) + ODDS = 1 Notify(\_SB.ECO, 0x90) } Method (_Q49, 0) { TRAP(0xd2) // Check AC Status - Store (0, ODDS) + ODDS = 0 Notify(\_SB.ECO, 0x90) } @@ -337,7 +337,7 @@ Method (_Q5C, 0) { - // Store(2, IGPS) + // IGPS = 2 Notify(\_SB.ECO, 0x94) } @@ -364,26 +364,26 @@ Method (GDPD, 0, Serialized) { // Set flag byte to zero - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x01)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x01) { + Local0 |= 0x01 } - If (And(BRTL, 0x02)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x02) { + Local0 |= 0x04 } - If (And(BRTL, 0x04)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x04) { + Local0 |= 0x02 } - If (And(BRTL, 0x30)) { - Or(Local0, 0x10, Local0) + If (BRTL & 0x30) { + Local0 |= 0x10 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x40, Local0) + If (BRTL & 0x40) { + Local0 |= 0x40 } Return (Local0) @@ -391,18 +391,18 @@ Method (GDPC, 0, Serialized) { - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x10)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x10) { + Local0 |= 0x0 } - If (And( BRTL, 0x20)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x20) { + Local0 |= 0x01 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x40) { + Local0 |= 0x02 } Return (Local0) @@ -411,7 +411,7 @@ /* Set Brightness Level */ Method(SBLL, 1, Serialized) { - Store (Arg0, BRTL) + BRTL = Arg0 TRAP(0xd5) // See mainboard's smihandler.c Return (0) } @@ -426,7 +426,7 @@ /* Get Brightness Level Medium? */ Method(GBLM, 0, Serialized) { - Store(0x3f, BRTL) + BRTL = 0x3f // XXX don't we have to set the brightness? Return(BRTL) } @@ -434,7 +434,7 @@ /* ??? */ Method(SUTE, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf5) } Else { TRAP(0xf6) @@ -462,33 +462,30 @@ /* Let coreboot update the flags */ TRAP(0xe5) - Store (0, Local0) - If(And(RFDV, 0x01)) { - Or(Local0, 0x01, Local0) + Local0 = 0 + If (RFDV & 0x01) { + Local0 |= 0x01 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x02) { + Local0 |= 0x02 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x04) { + Local0 |= 0x04 } - If(And(RFDV, 0x04)) { - Or(Local0, 0x04, Local0) + If (RFDV & 0x08) { + Local0 |= 0x08 } - If(And(RFDV, 0x08)) { - Or(Local0, 0x08, Local0) + If (GP15 & 0x01) { // GDIS + Local0 |= 0x10 } - If(And(GP15, 0x01)) { // GDIS - Or(Local0, 0x10, Local0) + If (GP12 & 0x01) { // WIFI Led (WLED) + Local0 |= 0x20 } - If(And(GP12, 0x01)) { // WIFI Led (WLED) - Or(Local0, 0x20, Local0) + If (BTEN & 0x01) { // BlueTooth Enable + Local0 |= 0x40 } - If(And(BTEN, 0x01)) { // BlueTooth Enable - Or(Local0, 0x40, Local0) - } - If(And(GP10, 0x01)) { // GPS Enable - Or(Local0, 0x80, Local0) + If (GP10 & 0x01) { // GPS Enable + Local0 |= 0x80 } Return (Local0) @@ -497,30 +494,30 @@ /* Set RFD */ Method(SRFD, 1, Serialized) { - If (And(Arg0, 0x01)) { - Store (1, GP14) // GLED - Store (1, GP15) // GDIS + If (Arg0 & 0x01) { + GP14 = 1 // GLED + GP15 = 1 // GDIS } Else { - Store (0, GP14) - Store (0, GP15) + GP14 = 0 + GP15 = 0 } /* WIFI */ - If (And(Arg0, 0x02)) { - Store (1, GP12) // WLED - Store (1, GP25) // WLAN + If (Arg0 & 0x02) { + GP12 = 1 // WLED + GP25 = 1 // WLAN } Else { - Store (0, GP12) - Store (0, GP25) + GP12 = 0 + GP25 = 0 } /* Bluetooth */ - If (And(Arg0, 0x04)) { - Store (1, GP13) // BLED - Store (1, BTEN) + If (Arg0 & 0x04) { + GP13 = 1 // BLED + BTEN = 1 } Else { - Store (0, GP13) // BLED - Store (0, BTEN) + GP13 = 0 // BLED + BTEN = 0 } Return (0) } @@ -542,7 +539,7 @@ /* Set IGD (Graphics) */ Method(SIGD, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf7) } Else { TRAP(0xf8) @@ -553,7 +550,7 @@ /* SMI-C? Set Mic? */ Method (SMIC, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xeb) } Else { TRAP(0xec) @@ -570,7 +567,7 @@ /* Not even decent function names anymore? */ Method(S024, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf1) } Else { TRAP(0xf2) @@ -588,13 +585,13 @@ /* ??? Something with PATA */ Method(S025, 1, Serialized) { - If(And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xfc) - Store (1, GP33) // CREN + GP33 = 1 // CREN Sleep(1500) - Store (1, GP34) // CRRS + GP34 = 1 // CRRS Sleep(500) Notify(^^PCI0.PATA, 0) @@ -602,7 +599,7 @@ } Else { TRAP(0xfb) Sleep(1500) - Store(0, GP33) // CREN + GP33 = 0 // CREN Sleep(1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID, 0) @@ -616,16 +613,16 @@ Method(G021, 0, Serialized) { TRAP(0xfe) - If (LEqual(ACIN, 0)) { + If (ACIN == 0) { TRAP(0xfa) TRAP(0xfd) - If (LEqual(ODDS, 1)) { + If (ODDS == 1) { TRAP(0xfb) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) Notify(^^PCI0.PATA.PRID.DSK0, 1) Sleep (1500) - Store (0, GP33) // CREN + GP33 = 0 // CREN Sleep (1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) @@ -648,7 +645,7 @@ /* ??? */ Method(S00B, 1, Serialized) { - If (And(Arg0, 1)) { + If (Arg0 & 1) { TRAP(0xdc) } Else { TRAP(0xdd) -- To view, visit https://review.coreboot.org/c/coreboot/+/45555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Gerrit-Change-Number: 45555 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/getac/p470/acpi/ec.asl: Remove duplicated code
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45865 ) Change subject: mb/getac/p470/acpi/ec.asl: Remove duplicated code ...................................................................... mb/getac/p470/acpi/ec.asl: Remove duplicated code "If(And(RFDV, 0x02)) {Or(Local0, 0x02, Local0)}" is duplicated. Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/ec.asl 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45865/1 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae644..5c0f4d8 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -469,9 +469,6 @@ If(And(RFDV, 0x02)) { Or(Local0, 0x02, Local0) } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) - } If(And(RFDV, 0x04)) { Or(Local0, 0x04, Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Gerrit-Change-Number: 45865 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: include/list.h: Add support for GCC9+
by Patrick Rudolph (Code Review) 03 Nov '20

03 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44573 ) Change subject: include/list.h: Add support for GCC9+ ...................................................................... include/list.h: Add support for GCC9+ When getting the address of a structure's member that is not on offset 0, GCC9+ assumes that the address never can be NULL. However the code relied on the fact that it can be NULL by letting the pointer intentionally overflow. Manually calculate the address using uintptr_t. This allows to gracefully terminate the list_for_each MACRO instead of crashing at the end of the list. Tested on qemu-system-arm: coreboot no longer crashed in the devicetree parser and is able to boot Linux 5.5. Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/include/list.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44573/1 diff --git a/src/include/list.h b/src/include/list.h index 3944878..6f0b54d 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -16,10 +16,10 @@ // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); -#define list_for_each(ptr, head, member) \ - for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ - &((ptr)->member); \ - (ptr) = container_of((ptr)->member.next, \ +#define list_for_each(ptr, head, member) \ + for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ + (uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \ + (ptr) = container_of((ptr)->member.next, \ typeof(*(ptr)), member)) #endif /* __LIST_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7 Gerrit-Change-Number: 44573 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 12

Change in coreboot[master]: util/cbfstool: Add Alignment for CBnT
by Christian Walter (Code Review) 03 Nov '20

03 Nov '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45652 ) Change subject: util/cbfstool: Add Alignment for CBnT ...................................................................... util/cbfstool: Add Alignment for CBnT Change-Id: Ibd94539a6025e7c3912730a6d90454379d85fb59 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M util/cbfstool/cbfstool.c M util/cbfstool/fit.c 2 files changed, 27 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45652/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d2df1cc..ce72835 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -70,6 +70,7 @@ bool machine_parseable; bool unprocessed; bool ibb; + bool cbnt; enum comp_algo compression; int precompression; enum vb2_hash_algorithm hash; @@ -551,6 +552,18 @@ len_align = 16; } + if (param.cbnt) { + ERROR("MARKING ENTRY AS CBNT\n"); + /* Mark as Initial Boot Block */ + struct cbfs_file_attribute *attrs = cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_IBB, + sizeof(struct cbfs_file_attribute)); + if (attrs == NULL) + return -1; + /* For Intel CBNT minimum align is 64 */ + len_align = 64; + } + if (param.padding) { const uint32_t hs = sizeof(struct cbfs_file_attribute); uint32_t size = MAX(hs, param.padding); @@ -1290,6 +1303,7 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_CBNT = 257, LONGOPT_END, }; @@ -1333,6 +1347,7 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"cbnt", no_argument, 0, LONGOPT_CBNT }, {NULL, 0, 0, 0 } }; @@ -1406,7 +1421,7 @@ " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) [--ibb] " + " [-j topswap-size] (Intel CPUs only) [--ibb] [--cbnt] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1417,7 +1432,7 @@ " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" " [-a alignment] [-P page-size] [-Q|--pow2page] \\\n" - " [-y|--xip] [--ibb] " + " [-y|--xip] [--ibb] [--cbnt] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1750,6 +1765,9 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_CBNT: + param.cbnt = true; + break; case 'h': case '?': usage(argv[0]); diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index e7aa8d7..b04cf90 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -463,9 +463,10 @@ uint32_t boot_policy_size) { entry->address = boot_policy_addr; - /* Boot Policy Manifest size is not multiple of 16 bytes */ - fit_entry_update_size(entry, boot_policy_size << 4); entry->type_checksum_valid = FIT_TYPE_BOOT_POLICY; + /* Boot Policy Manifest size is not multiple of 16 bytes */ + fit_entry_update_size(entry, boot_policy_size); + entry->size_reserved = boot_policy_size; entry->version = FIT_TXT_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); @@ -482,9 +483,11 @@ uint32_t key_manifest_size) { entry->address = key_manifest_addr; - /* Key Manifest size is not multiple of 16 bytes */ - fit_entry_update_size(entry, key_manifest_size << 4); + entry->type_checksum_valid = FIT_TYPE_KEY_MANIFEST; + /* Key Manifest size is not multiple of 16 bytes */ + fit_entry_update_size(entry, key_manifest_size); + entry->size_reserved = key_manifest_size; entry->version = FIT_TXT_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd94539a6025e7c3912730a6d90454379d85fb59 Gerrit-Change-Number: 45652 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [TESTONLY] smm loader v2 fixups for B85M Pro4
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44174 ) Change subject: [TESTONLY] smm loader v2 fixups for B85M Pro4 ...................................................................... [TESTONLY] smm loader v2 fixups for B85M Pro4 Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h M src/mainboard/asrock/b85m_pro4/Kconfig 4 files changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44174/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..375c94e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -726,8 +726,18 @@ * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ - perm_smbase = mp_state.perm_smbase; - perm_smbase -= cpu * runtime->save_state_size; + if (CONFIG(X86_SMM_LOADER_VERSION2)) { + perm_smbase = smm_get_cpu_smbase(cpu); + mp_state.perm_smbase = perm_smbase; + + if (!perm_smbase) { + printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); + return; + } + } else { + perm_smbase = mp_state.perm_smbase; + perm_smbase -= cpu * runtime->save_state_size; + } printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index c084f74..e6ccfdf 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -173,7 +173,7 @@ * input: cpu_num - cpu number which is used as an index into the * map to return the smbase */ -int smm_get_cpu_smbase(unsigned int cpu_num) +u32 smm_get_cpu_smbase(unsigned int cpu_num) { if (cpu_num < CONFIG_MAX_CPUS) { if (cpus[cpu_num].active) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7838223..084d150 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -149,21 +149,19 @@ struct smm_runtime *runtime; /* The following are only used by X86_SMM_LOADER_VERSION2 */ - #if CONFIG(X86_SMM_LOADER_VERSION2) +#if CONFIG(X86_SMM_LOADER_VERSION2) unsigned int smm_entry; unsigned int smm_main_entry_offset; unsigned int smram_start; unsigned int smram_end; - #endif +#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); -#if CONFIG(X86_SMM_LOADER_VERSION2) -int smm_get_cpu_smbase(unsigned int cpu_num); -#endif +u32 smm_get_cpu_smbase(unsigned int cpu_num); /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc65120..2afc334 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -17,6 +17,7 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 + select X86_SMM_LOADER_VERSION2 config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/44174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Gerrit-Change-Number: 44174 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45275 ) Change subject: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax ...................................................................... sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/usb.asl 2 files changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45275/1 diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 16db175..7c4ef34 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -40,7 +40,6 @@ } } - // USB Controller 0:1d.1 Device (USB2) @@ -60,9 +59,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -80,7 +79,6 @@ } - // USB Controller 0:1d.2 Device (USB3) @@ -100,9 +98,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -120,7 +118,6 @@ } - // USB Controller 0:1d.3 Device (USB4) @@ -140,9 +137,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U4WE) + U4WE = 3 } Else { - Store (0, U4WE) + U4WE = 0 } } @@ -160,7 +157,6 @@ } - // EHCI Controller 0:1d.7 Device (EHC1) -- To view, visit https://review.coreboot.org/c/coreboot/+/45275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Gerrit-Change-Number: 45275 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45281 ) Change subject: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax ...................................................................... mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/d945gclf/acpi/platform.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45281/1 diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 30e4d2c..cf73fc1 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -20,12 +20,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } -- To view, visit https://review.coreboot.org/c/coreboot/+/45281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Gerrit-Change-Number: 45281 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: libpayload: Add support for link time optimization
by Jacob Garber (Code Review) 03 Nov '20

03 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38291 ) Change subject: libpayload: Add support for link time optimization ...................................................................... libpayload: Add support for link time optimization Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 149K 11.49s LTO 125K 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38291/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e3..9312f19 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,6 +80,13 @@ endchoice +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1b7986c..ecf7937 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -65,6 +65,10 @@ CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Gerrit-Change-Number: 38291 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init: Add support for x86_64
by Patrick Rudolph (Code Review) 03 Nov '20

03 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44675 ) Change subject: cpu/x86/mp_init: Add support for x86_64 ...................................................................... cpu/x86/mp_init: Add support for x86_64 Fix compilation on x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44675/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..da0002f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -113,7 +113,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -339,16 +339,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/44675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Gerrit-Change-Number: 44675 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/amd/picasso: pass verstage timestamps to x86
by Kangheui Won (Code Review) 03 Nov '20

03 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45059 ) Change subject: soc/amd/picasso: pass verstage timestamps to x86 ...................................................................... soc/amd/picasso: pass verstage timestamps to x86 Remove stubs for psp_verstage and initialize timestamp table with data from psp_verstage on bootblock. We need to convert numbers since timestamps on verstage uses microseconds granularity and x86 uses TSC. BUG=b:154142138, b:159220781 BRANCH=zork TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are included in the result. Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Signed-off-by: Kangheui Won <khwon(a)chromium.org> --- M src/include/bootblock_common.h M src/lib/Makefile.inc M src/lib/bootblock.c M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/psp_verstage/Makefile.inc M src/soc/amd/picasso/psp_verstage/psp_verstage.c D src/soc/amd/picasso/psp_verstage/timestamp.c 7 files changed, 43 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45059/1 diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96..da627d2 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -29,6 +29,8 @@ asmlinkage void ap_bootblock_c_entry(void); void bootblock_main_with_basetime(uint64_t base_timestamp); +void bootblock_main_with_timestamp(uint64_t base_timestamp, + struct timestamp_entry *timestamps, size_t num_timestamps); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4ce133a..5a960e9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -68,10 +68,7 @@ verstage-y += memcmp.c verstage-y += string.c -# TODO: Remove this when PSP bootblock timestamps are implemented. -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 1c433d0..3e2ef06 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,7 +25,7 @@ * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ -static void bootblock_main_with_timestamp(uint64_t base_timestamp, +void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4700027..2ba6be9 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> +#include <timestamp.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -119,7 +120,44 @@ write_resume_eip(); enable_pci_mmconf(); +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) + struct transfer_info_struct *info = (struct transfer_info_struct *) + CONFIG_PSP_SHAREDMEM_BASE; + + if (info->magic_val == TRANSFER_MAGIC_VAL && + info->timestamp_offset != 0) { + int i; + uint32_t tick_freq_mhz = timestamp_tick_freq_mhz(); + struct timestamp_table *psp_ts_table = (struct timestamp_table *) + (CONFIG_PSP_SHAREDMEM_BASE + info->timestamp_offset); + + /* if we're unable to determine timestamp tick, leave it as raw number */ + if (tick_freq_mhz == 0) { + tick_freq_mhz = 1; + } + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * Since bootblock_main_with_timestamp calls timestamp_add and + * timestamp_add subtracts base_time, we need to add base_time here. + * Also values are in us so multiply it by tick_freq_mhz + */ + uint64_t abs_stamp = psp_ts_table->base_time + tse->entry_stamp; + tse->entry_stamp = abs_stamp * tick_freq_mhz; + } + + base_timestamp = psp_ts_table->base_time * tick_freq_mhz; + bootblock_main_with_timestamp(base_timestamp, + psp_ts_table->entries, psp_ts_table->num_entries); + + } else { + bootblock_main_with_basetime(base_timestamp); + } +#else bootblock_main_with_basetime(base_timestamp); +#endif + } void bootblock_soc_early_init(void) diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 905613e..4f1642b 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -15,7 +15,6 @@ verstage-y += reset.c verstage-y += svc.c verstage-y += timer.c -verstage-y += timestamp.c verstage-y += vboot_crypto.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index ef4884f..b429ef3 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -16,6 +16,7 @@ #include <arch/stages.h> #include <stdarg.h> #include <stdio.h> +#include <timestamp.h> extern char _bss_start, _bss_end; static struct mem_region_device boot_dev = @@ -207,6 +208,7 @@ * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() */ + timestamp_init(timestamp_get()); svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); diff --git a/src/soc/amd/picasso/psp_verstage/timestamp.c b/src/soc/amd/picasso/psp_verstage/timestamp.c deleted file mode 100644 index b3b8f75..0000000 --- a/src/soc/amd/picasso/psp_verstage/timestamp.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <timestamp.h> - -/* Stubs */ -void timestamp_add_now(enum timestamp_id id) -{ -} - -void timestamp_add(enum timestamp_id id, uint64_t ts) -{ -} - -uint64_t timestamp_get(void) -{ - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Gerrit-Change-Number: 45059 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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