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Change in coreboot[master]: soc/intel/broadwell: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37014 ) Change subject: soc/intel/broadwell: Use common SMM save state ops ...................................................................... soc/intel/broadwell: Use common SMM save state ops Change-Id: I07f576b586622cfff73dea39af0fbb0cfbab04b4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/smihandler.c 1 file changed, 49 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37014/1 diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ca99487..74bb5a8 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -260,62 +259,71 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); /* Emulate B2 register as the FADT / Linux expects it */ @@ -341,13 +349,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/37014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f576b586622cfff73dea39af0fbb0cfbab04b4 Gerrit-Change-Number: 37014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37013 ) Change subject: soc/intel/baytrail: Use common SMM save state ops ...................................................................... soc/intel/baytrail: Use common SMM save state ops Change-Id: Ia74a9956a22d550b5d864b38632add3d4d48b83d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c 1 file changed, 50 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37013/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 16e2d95..e19f9c6 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <elog.h> #include <halt.h> @@ -177,57 +176,65 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + u32 ret, param; + u8 sub_command; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg);} static void finalize(void) { @@ -301,8 +308,8 @@ static void southbridge_smi_apmc(void) { + const struct smm_save_state_ops *ops = get_save_state_ops(); uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -336,13 +343,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/37013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia74a9956a22d550b5d864b38632add3d4d48b83d Gerrit-Change-Number: 37013 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/haswell: Use common smm save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37012 ) Change subject: sb/intel/haswell: Use common smm save state ops ...................................................................... sb/intel/haswell: Use common smm save state ops Change-Id: I6db0a63a0c55ee1c8e67948fd4f4024f886597e6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/lynxpoint/smihandler.c 1 file changed, 49 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37012/1 diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 61f86fb..a863fc8 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -22,7 +22,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> @@ -214,62 +213,71 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -317,13 +325,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case 0xca: usb_xhci_route_all(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6db0a63a0c55ee1c8e67948fd4f4024f886597e6 Gerrit-Change-Number: 37012 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/common: Use common save_state ops to fetch apmc args
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37011 ) Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ...................................................................... sb/intel/common: Use common save_state ops to fetch apmc args Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 89 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f292b6f..a9942f3 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -38,6 +37,11 @@ return gnvs; } +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} + int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -162,18 +166,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 6af8805..8959613 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -18,7 +18,6 @@ #define INTEL_COMMON_PMUTIL_H #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -142,10 +141,10 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); +void set_gnvs(void *gnvs_ptr); uint8_t get_gnvs_smif(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +int smi_apmc_find_state_save_node(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 46fe28a..80f4380 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <inttypes.h> #include <types.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -22,7 +23,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> @@ -214,76 +214,108 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; + void *param; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = (void *)(uint32_t)reg; /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; + ret = smmstore_exec(sub_command, param); + ops->set_reg(node, RAX, ret); +} + +static void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +{ + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); + uint64_t rbx; + uintptr_t gnvs_ptr; + if (ops->get_reg(node, RBX, &rbx)) + return; + + gnvs_ptr = rbx; + + set_gnvs((void *)gnvs_ptr); + *smm_done = 1; + + printk(BIOS_DEBUG, "SMI#: Setting GNVS to " PRIxPTR"\n", gnvs_ptr); } static int mainboard_finalized = 0; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 1aacbca..b215cc6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -36,17 +36,15 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs(void *gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - *smm_done = 1; + gnvs = gnvs_ptr; } int southbridge_io_trap_handler(int smif) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 96a9e2a..2c56fe6 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -28,9 +28,12 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; + +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} int southbridge_io_trap_handler(int smif) { @@ -49,14 +52,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6ed5edd..eb193fa 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -26,18 +26,12 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; +static global_nvs_t *gnvs; -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} int southbridge_io_trap_handler(int smif) { @@ -56,14 +50,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..ac45c15 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Gerrit-Change-Number: 37011 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: sb/intel/common/smihandler: Use a common IO TRAP handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37010 ) Change subject: sb/intel/common/smihandler: Use a common IO TRAP handler ...................................................................... sb/intel/common/smihandler: Use a common IO TRAP handler This adds the get_gnvs_smif callback to get smif from the sb dependent gnvs struct. Change-Id: I85ff060012f68087edce6946b05181ee6b84a135 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c 6 files changed, 64 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37010/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index ceac598..f292b6f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -151,58 +151,9 @@ } } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_smm_xhci_sleep(u8 slp_type) diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index cea5c82..6af8805 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -144,7 +144,7 @@ void southbridge_gate_memory_reset(void); void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); -void southbridge_smi_monitor(void); +uint8_t get_gnvs_smif(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7f376fd..46fe28a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -30,6 +30,7 @@ #include <smmstore.h> #include "pmutil.h" +#include "rcba.h" static int smm_initialized = 0; @@ -455,6 +456,60 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } +static void southbridge_smi_monitor(void) +{ +#define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; + u32 data, mask = 0; + int i; + + trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register + RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR + + trap_cycle = RCBA32(0x1e10); + for (i=16; i<20; i++) { + if (trap_cycle & (1 << i)) + mask |= (0xff << ((i - 16) << 2)); + } + + + /* IOTRAP(3) SMI function call */ + if (IOTRAP(3)) { + io_trap_handler(get_gnvs_smif()); + return; + } + + /* IOTRAP(2) currently unused + * IOTRAP(1) currently unused */ + + /* IOTRAP(0) SMIC */ + if (IOTRAP(0)) { + if (!(trap_cycle & (1 << 24))) { // It's a write + printk(BIOS_DEBUG, "SMI1 command\n"); + data = RCBA32(0x1e18); + data &= mask; + // if (smi1) + // southbridge_smi_command(data); + // return; + } + // Fall through to debug + } + + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + + if (!(trap_cycle & (1 << 24))) { + /* Write Cycle */ + data = RCBA32(0x1e18); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + } +#undef IOTRAP +} + + typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13..1aacbca 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -66,49 +66,9 @@ return 0; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i = 16; i < 20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC: currently unused */ - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i = 0; i < 4; i++) - if (IOTRAP(i)) - printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8090a09..96a9e2a 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -57,58 +57,9 @@ *smm_done = 1; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 3)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a853..6ed5edd 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -64,58 +64,9 @@ *smm_done = 1; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 3)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ff060012f68087edce6946b05181ee6b84a135 Gerrit-Change-Number: 37010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: cpu/x86/smm/smihandler.c: Clean up unused save state handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37009 ) Change subject: cpu/x86/smm/smihandler.c: Clean up unused save state handler ...................................................................... cpu/x86/smm/smihandler.c: Clean up unused save state handler This was only used to print out the save state which is now done by the common save state handler. Change-Id: I98b17ab370ff58e0444cda1f8bfc05ea38ec6b71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c 1 file changed, 0 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37009/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 0adf591..da1cd7b 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -17,32 +17,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> -#include <cpu/amd/amd64_save_state.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/x86/legacy_save_state.h> #if CONFIG(SPI_FLASH_SMM) #include <spi-generic.h> #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -126,12 +105,6 @@ outl(pci_orig, 0xcf8); } -static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) -{ - base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); - return (void *)base; -} - uint8_t *smm_get_save_state_top(int cpu) { const uint32_t smm_base = 0xa0000; @@ -148,8 +121,6 @@ void smi_handler(u32 smm_revision) { unsigned int node; - smm_state_save_area_t state_save; - u32 smm_base = 0xa0000; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -177,42 +148,6 @@ smm_save_state_ops_init(); - switch (smm_revision) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); - /* Don't release lock, so no further SMI will happen, - * if we don't handle it anyways. - */ - return; - } - /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { #if CONFIG(SPI_FLASH_SMM) -- To view, visit https://review.coreboot.org/c/coreboot/+/37009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b17ab370ff58e0444cda1f8bfc05ea38ec6b71 Gerrit-Change-Number: 37009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [RFC]cpu/x86/smm: Add a unified way of handling save_states
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36661 ) Change subject: [RFC]cpu/x86/smm: Add a unified way of handling save_states ...................................................................... [RFC]cpu/x86/smm: Add a unified way of handling save_states This adds common code to handle SMM save states based on the SMM revision. example: SMM code needing access to eax from save state would do the following struct smm_save_state_ops ops = get_save_state_ops(); uint64_t rax; int node; for (node = 0; node < CONFIG_MAX_CPUS; node++) { if (ops.get_reg(node, RAX, &rax)) error... rax &= MAX_UINT32; do_stuff... } UNTESTED. Change-Id: Ide7ccc44dbcc864e70463ef318dc1858b51183dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/smm_save_state.c M src/include/cpu/x86/smm.h 3 files changed, 311 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36661/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..6c74c88 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,6 +47,7 @@ smmstub-y += smm_stub.S smm-y += smm_module_handler.c +smm-y += smm_save_state.c ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual diff --git a/src/cpu/x86/smm/smm_save_state.c b/src/cpu/x86/smm/smm_save_state.c new file mode 100644 index 0000000..8a7f347 --- /dev/null +++ b/src/cpu/x86/smm/smm_save_state.c @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/legacy_save_state.h> + +static const struct smm_runtime *smm_runtime; +static const struct smm_save_state_ops *ops; + +static void *smm_get_save_state_top(int cpu) +{ + char *base; + + /* This function assumes all save states start at top of default + * SMRAM size space and are staggered down by save state size. */ + base = (void *)smm_runtime->smbase; + base += SMM_DEFAULT_SIZE; + base -= cpu * smm_runtime->save_state_size; + + return base; +} + +static uint32_t smm_get_revision(uint32_t base) +{ + uint8_t *top = (uint8_t *)smm_get_save_state_top(0); + /* SMM revision offset from top */ + return *(uint32_t *)(top - (0x8000 - 0x7efc)); +} + +const struct smm_save_state_ops *get_save_state_ops(void) +{ + return ops; +} + +/* We only have 32bit registers so we'll fake 64bit registers with 0 + in the upper part. */ +static void *legacy_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + legacy_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(legacy_smm_state_save_area_t); + state = (legacy_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->eax; + case RBX: + return &state->ebx; + case RCX: + return &state->ecx; + case RDX: + return &state->edx; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *em64t100_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + em64t100_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL;; + base = smm_get_save_state_top(cpu); + base -= sizeof(em64t100_smm_state_save_area_t); + state = (em64t100_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case IO_MISC_INFO: + return &state->io_misc_info; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *em64t101_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + em64t101_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(em64t101_smm_state_save_area_t); + state = (em64t101_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case IO_MISC_INFO: + return &state->io_misc_info; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *amd64_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + amd64_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(amd64_smm_state_save_area_t); + state = (amd64_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case SMM_IO_TRAP_OFFSET: + return &state->smm_io_trap_offset; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static int ss_get_helper(unsigned int cpu, enum smm_reg reg, void *val, size_t val_size, + void *(*get_reg_ptr_fn)(unsigned int, enum smm_reg)) +{ + void *ss_entry = get_reg_ptr_fn(cpu, reg); + if (!ss_entry) + return -1; + memcpy(val, ss_entry, val_size); + return 0; +} + +static int ss_set_helper(unsigned int cpu, enum smm_reg reg, void *val, size_t val_size, + void *(*get_reg_ptr_fn)(unsigned int, enum smm_reg)) +{ + void *ss_entry = get_reg_ptr_fn(cpu, reg); + if (!ss_entry) + return -1; + memcpy(ss_entry, val, val_size); + return 0; +} + +static int legacy_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(uint32_t), legacy_get_reg_ptr); +} + +static int legacy_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(uint32_t), legacy_get_reg_ptr); +} + +static int em64t100_get_io_misc_info(unsigned int cpu, uint32_t *misc_info) +{ + return ss_get_helper(cpu, IO_MISC_INFO, misc_info, sizeof(*misc_info), em64t100_get_reg_ptr); +} + +static int em64t100_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), em64t100_get_reg_ptr); +} + +static int em64t100_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), em64t100_get_reg_ptr); +} + +static int em64t101_get_io_misc_info(unsigned int cpu, uint32_t *misc_info) +{ + return ss_get_helper(cpu, IO_MISC_INFO, misc_info, sizeof(*misc_info), em64t101_get_reg_ptr); +} + +static int em64t101_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), em64t101_get_reg_ptr); +} + +static int em64t101_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), em64t101_get_reg_ptr); +} + +static int amd64_get_io_trap(unsigned int cpu, uint32_t *io_trap) +{ + return ss_get_helper(cpu, SMM_IO_TRAP_OFFSET, io_trap, sizeof(*io_trap), amd64_get_reg_ptr); +} + +static int amd64_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), amd64_get_reg_ptr); +} + +static int amd64_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), amd64_get_reg_ptr); +} + +static const struct smm_save_state_ops legacy_save_state_ops = { + .get_reg = legacy_get_reg, + .set_reg = legacy_set_reg, +}; + +static const struct smm_save_state_ops em64t100_save_state_ops = { + .get_io_misc_info = em64t100_get_io_misc_info, + .get_reg = em64t100_get_reg, + .set_reg = em64t100_set_reg, +}; + +static const struct smm_save_state_ops em64t101_save_state_ops = { + .get_io_misc_info = em64t101_get_io_misc_info, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, +}; + +static const struct smm_save_state_ops amd64_save_state_ops = { + .get_io_trap = amd64_get_io_trap, + .get_reg = amd64_get_reg, + .set_reg = amd64_set_reg, +}; + +int smm_save_state_ops_init(const struct smm_runtime *runtime) +{ + uint32_t smm_revision = smm_get_revision(runtime->smbase); + smm_runtime = runtime; + + switch (smm_revision) { + case 0x00030002: + case 0x00030007: + ops = &legacy_save_state_ops; + return 0; + break; + case 0x00030100: + ops = &em64t100_save_state_ops; + return 0; + break; + case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ + ops = &em64t101_save_state_ops; + return 0; + case 0x00020064: + case 0x00030064: + ops = &amd64_save_state_ops; + return 0; + default: + printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); + printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + return 1; + } +} + diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..b389e77 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -95,6 +95,33 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); + +enum smm_reg { + RAX, + RBX, + RCX, + RDX, + IO_MISC_INFO, + SMM_IO_TRAP_OFFSET, +}; + +/* SMM save state ops. + WARNING1: This does not take into account CPUs which are configured to not + save their state to RAM. Returns -1 on failure, 0 on succes. */ +struct smm_save_state_ops { + /* Intel 64: misc info */ + int (*get_io_misc_info)(unsigned int cpu, uint32_t *misc_info); + /* AMD64: smm_io_trap */ + int (*get_io_trap)(unsigned int cpu, uint32_t *misc_info); + /* return value of the requested register from + * SMM Save State Area. + */ + int (*get_reg)(unsigned int cpu, enum smm_reg reg, uint64_t *val); + int (*set_reg)(unsigned int cpu, enum smm_reg reg, uint64_t val); +}; + +const struct smm_save_state_ops *get_save_state_ops(void); +int smm_save_state_ops_init(const struct smm_runtime *runtime); #endif /* __SMM__ */ /* SMM Module Loading API */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7ccc44dbcc864e70463ef318dc1858b51183dc Gerrit-Change-Number: 36661 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/common: Rename save state accessors
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37110 ) Change subject: soc/intel/common: Rename save state accessors ...................................................................... soc/intel/common: Rename save state accessors This avoids name collision with follow-up code that intends to reuse these names and replace this code. Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 8 files changed, 71 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37110/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..f26d8ba 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -29,7 +29,7 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t100_smm_ops; } diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..1d57c7e 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -32,7 +32,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f1..afe8505 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -25,32 +25,32 @@ /* * The register value is used with get_reg and set_reg */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, +enum intel_smm_reg { + SMM_RAX, + SMM_RBX, + SMM_RCX, + SMM_RDX, }; -struct smm_save_state_ops { +struct intel_smm_save_state_ops { /* return io_misc_info from SMM Save State Area */ uint32_t (*get_io_misc_info)(void *state); /* return value of the requested register from * SMM Save State Area */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); + uint64_t (*get_reg)(void *state, enum intel_smm_reg reg); - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); + void (*set_reg)(void *state, enum intel_smm_reg reg, uint64_t val); }; -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); +typedef void (*smi_handler_t)(const struct intel_smm_save_state_ops *save_state_ops); /* * SOC SMI Handler has to provide this structure which has methods to access * the SOC specific SMM Save State Area */ -const struct smm_save_state_ops *get_smm_save_state_ops(void); +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void); /* * southbridge_smi should be defined inside SOC specific code and should have @@ -67,7 +67,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -75,7 +75,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -83,7 +83,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -91,7 +91,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -99,7 +99,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -107,14 +107,14 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -122,7 +122,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -130,7 +130,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -138,7 +138,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * Returns gnvs pointer within SMM context @@ -173,7 +173,7 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); -extern const struct smm_save_state_ops em64t100_smm_ops; +extern const struct intel_smm_save_state_ops em64t100_smm_ops; -extern const struct smm_save_state_ops em64t101_smm_ops; +extern const struct intel_smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0581d23..d76fb0a 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -87,7 +87,7 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, +static void *find_save_state(const struct intel_smm_save_state_ops *save_state_ops, int cmd) { int node; @@ -111,7 +111,7 @@ if (((io_misc_info >> 16) & 0xff) != APM_CNT) continue; /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); + reg_al = save_state_ops->get_reg(state, SMM_RAX); if (reg_al != cmd) continue; break; @@ -179,7 +179,7 @@ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; uint8_t slp_typ; @@ -275,7 +275,7 @@ } static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi = NULL; @@ -285,19 +285,19 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/elog/gsmi.c */ ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi; @@ -307,14 +307,14 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void finalize(void) @@ -336,7 +336,7 @@ } void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint8_t reg8; void *state = NULL; @@ -379,7 +379,7 @@ state = find_save_state(save_state_ops, reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); + uint32_t reg_ebx = save_state_ops->get_reg(state, SMM_RBX); gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); @@ -402,7 +402,7 @@ } void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -420,13 +420,13 @@ } void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { pmc_clear_all_gpe_status(); } void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -443,7 +443,7 @@ } void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; @@ -456,7 +456,7 @@ } void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { struct gpi_status smi_sts; @@ -468,7 +468,7 @@ } void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { mainboard_smi_espi_handler(); } @@ -477,7 +477,7 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; + const struct intel_smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -519,22 +519,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t100_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -543,21 +543,21 @@ return value; } -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t100_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -571,22 +571,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t101_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -595,21 +595,21 @@ return value; } -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t101_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -617,13 +617,13 @@ } } -const struct smm_save_state_ops em64t100_smm_ops = { +const struct intel_smm_save_state_ops em64t100_smm_ops = { .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, .get_reg = em64t100_smm_save_state_get_reg, .set_reg = em64t100_smm_save_state_set_reg, }; -const struct smm_save_state_ops em64t101_smm_ops = { +const struct intel_smm_save_state_ops em64t101_smm_ops = { .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, .get_reg = em64t101_smm_save_state_get_reg, .set_reg = em64t101_smm_save_state_set_reg, diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 974c489..b7e25e4 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -56,7 +56,7 @@ } void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -68,7 +68,7 @@ } void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..039900e 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..50a82f9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -20,7 +20,7 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..25bdacc 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Gerrit-Change-Number: 37110 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: cpu/x86/smm: Add a helper function returning top of save state
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37008 ) Change subject: cpu/x86/smm: Add a helper function returning top of save state ...................................................................... cpu/x86/smm: Add a helper function returning top of save state Some entries like smm base and smm revision have a fixed location in the save w.r.t. the save state top. Change-Id: I82dadcb966ee686c1652c7a1298dcb9938ae888c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37008/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 20417d1..79a3936 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -132,6 +132,13 @@ return (void *)base; } +uint8_t *smm_get_save_state_top(int cpu) +{ + const uint32_t smm_base = 0xa0000; + + return (uint8_t *)smm_base + SMM_ENTRY_OFFSET * 2 - (cpu * 0x400); +} + /** * @brief Interrupt handler for SMI# * diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c..80bff9f 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -114,6 +114,19 @@ return base; } +uint8_t *smm_get_save_state_top(int cpu) +{ + uint8_t *base; + + /* This function assumes all save states start at top of default + * SMRAM size space and are staggered down by save state size. */ + base = (void *)smm_runtime->smbase; + base += SMM_DEFAULT_SIZE; + base -= cpu * smm_runtime->save_state_size; + + return base; +} + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..0ade970 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -94,6 +94,7 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); +uint8_t *smm_get_save_state_top(int cpu); /* SMM Module Loading API */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82dadcb966ee686c1652c7a1298dcb9938ae888c Gerrit-Change-Number: 37008 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Documentation/releases: Add ASan to 4.13 relnotes
by Harshit Sharma (Code Review) 11 Nov '20

11 Nov '20

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45118 ) Change subject: Documentation/releases: Add ASan to 4.13 relnotes ...................................................................... Documentation/releases: Add ASan to 4.13 relnotes Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45118/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index dcc8bf4..388d291 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -49,4 +49,13 @@ CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. +### Address Sanitizer + +coreboot now has an in-built Address Sanitizer, a runtime memory debugger +designed to find out-of-bounds access and use-after-scope bugs. It is made +available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo +Lake, and Haswell in romstage. Further, it can be enabled in romstage on other +x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for +more info. + ### Add significant changes here -- To view, visit https://review.coreboot.org/c/coreboot/+/45118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Gerrit-Change-Number: 45118 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

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