coreboot-gerrit September 2020

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Change in coreboot[master]: APCI S3: Split arch-agnostic parts
by Kyösti Mälkki (Code Review) 20 Nov '20

20 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42614 ) Change subject: APCI S3: Split arch-agnostic parts ...................................................................... APCI S3: Split arch-agnostic parts Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Makefile.inc A src/acpi/acpi_pm.c M src/arch/x86/Makefile.inc M src/arch/x86/acpi_s3.c 4 files changed, 48 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42614/1 diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 7e37e1a..108f427 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dsm.c ramstage-y += acpigen_ps2_keybd.c @@ -12,6 +13,8 @@ ramstage-y += sata.c ramstage-y += soundwire.c +postcar-y += acpi_pm.c + ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c endif diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c new file mode 100644 index 0000000..b88b761 --- /dev/null +++ b/src/acpi/acpi_pm.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <romstage_handoff.h> + +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1; + +static void acpi_handoff_wakeup(void) +{ + if (acpi_slp_type < 0) { + if (romstage_handoff_is_resume()) { + printk(BIOS_DEBUG, "S3 Resume\n"); + acpi_slp_type = ACPI_S3; + } else { + printk(BIOS_DEBUG, "Normal boot\n"); + acpi_slp_type = ACPI_S0; + } + } +} + +int acpi_is_wakeup(void) +{ + acpi_handoff_wakeup(); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); +} + +int acpi_is_wakeup_s3(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S3); +} + +int acpi_is_wakeup_s4(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S4); +} + +void __weak mainboard_suspend_resume(void) +{ +} diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6297384..6773b270 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -157,7 +157,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-y += boot.c romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C @@ -198,7 +197,6 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ -postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += post.c postcar-y += gdt_init.S @@ -235,7 +233,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +ramstage-y += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += post.c diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 814719a..8017dff 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -9,45 +9,6 @@ #include <cpu/x86/smm.h> #include <fallback.h> #include <timestamp.h> -#include <romstage_handoff.h> - -#if ENV_RAMSTAGE || ENV_POSTCAR - -/* This is filled with acpi_is_wakeup() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_is_wakeup(void) -{ - acpi_handoff_wakeup(); - /* Both resume from S2 and resume from S3 restart at CPU reset */ - return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); -} - -int acpi_is_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - -int acpi_is_wakeup_s4(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S4); -} -#endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 @@ -56,10 +17,6 @@ extern unsigned char __wakeup; extern unsigned int __wakeup_size; -void __weak mainboard_suspend_resume(void) -{ -} - void __noreturn acpi_resume(void *wake_vec) { if (CONFIG(HAVE_SMI_HANDLER)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Gerrit-Change-Number: 42614 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp-car: Halt on improperly configured coreboot
by Arthur Heymans (Code Review) 19 Nov '20

19 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37280 ) Change subject: soc/intel/fsp-car: Halt on improperly configured coreboot ...................................................................... soc/intel/fsp-car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37280/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4174f36..bde3849 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -86,6 +86,11 @@ cmp $0, %eax jnz .halt_forever + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup bootblock stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Gerrit-Change-Number: 37280 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot
by Arthur Heymans (Code Review) 19 Nov '20

19 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37281 ) Change subject: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot ...................................................................... drivers/intel/fsp1.1/car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37281/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fb39884..748c267 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,6 +143,11 @@ cmp $0, %eax jne halt2 + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup BSP stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Gerrit-Change-Number: 37281 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: Makefile.inc: Ignore unknown IASL method when SMBus ACPI is used
by Maxim Polyakov (Code Review) 19 Nov '20

19 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44866 ) Change subject: Makefile.inc: Ignore unknown IASL method when SMBus ACPI is used ...................................................................... Makefile.inc: Ignore unknown IASL method when SMBus ACPI is used Methods _SBI, _SBR, _SBW from the "SMBus Control Methods Interface Specification" (Ver 1.0, 1999) are needed to control the SMBus, but they are not included in the last ACPI specification version 6.3 [1]. Therefore, building the image fails: dsdt.asl 1088: Method (_SBI, 0, NotSerialized) Warning 3133 - ^ Unknown reserved name (_SBI) dsdt.asl 1101: Method (_SBR, 3, NotSerialized) Warning 3133 - ^ Unknown reserved name (_SBR) dsdt.asl 1105: Method (_SBW, 5, NotSerialized) Warning 3133 - ^ Unknown reserved name (_SBW) This patch adds warning 3133 to the ignored list to allow build image with these ACPI methods. TEST = Build image for the Kontron mAL10 COMe (Apollo Lake) [2] with SMBus ACPI code [3]. [1] https://bugs.acpica.org/show_bug.cgi?id=1530 [2] https://review.coreboot.org/c/coreboot/+/39133 [3] https://review.coreboot.org/c/coreboot/+/44475 Change-Id: Ibb4a6e472445ab08bf333ff16d7a7fac220ac96d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44866/1 diff --git a/Makefile.inc b/Makefile.inc index b650957..df37c22 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -265,6 +265,8 @@ # See cb:38803 & cb:38802 # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 +# Ignore the warning about "Unknown reserved name". +UNKNOWN_RESERVED_NAME_TYPES_WARNING = 3133 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK) @@ -272,6 +274,13 @@ IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING) endif +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER),y) +# Methods _SBI, _SBR, _SBW from the "SMBus Control Methods Interface Specification" +# (Ver 1.0, 1999) are needed to control the SMBus, but they are not included in the +# last ACPI specification version 6.3 (https://bugs.acpica.org/show_bug.cgi?id=1530) +IASL_WARNINGS_LIST += $(UNKNOWN_RESERVED_NAME_TYPES_WARNING) +endif + IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST)) define asl_template -- To view, visit https://review.coreboot.org/c/coreboot/+/44866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb4a6e472445ab08bf333ff16d7a7fac220ac96d Gerrit-Change-Number: 44866 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: ACPI S3: Minor cleanup
by Kyösti Mälkki (Code Review) 19 Nov '20

19 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42613 ) Change subject: ACPI S3: Minor cleanup ...................................................................... ACPI S3: Minor cleanup Drop extra function in the middle and adjust the post_code() to happen wright before jump to wakeup vector. Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_s3.c 1 file changed, 8 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42613/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index fef04ac..814719a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -56,18 +56,6 @@ extern unsigned char __wakeup; extern unsigned int __wakeup_size; -static void acpi_jump_to_wakeup(void *vector) -{ - /* Copy wakeup trampoline in place. */ - memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); - - set_boot_successful(); - - timestamp_add_now(TS_ACPI_WAKE_JUMP); - - acpi_do_wakeup((uintptr_t)vector); -} - void __weak mainboard_suspend_resume(void) { } @@ -88,8 +76,15 @@ /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); + /* Copy wakeup trampoline in place. */ + memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + + set_boot_successful(); + + timestamp_add_now(TS_ACPI_WAKE_JUMP); + post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); + acpi_do_wakeup((uintptr_t)wake_vec); die("Failed the jump to wakeup vector\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20 Gerrit-Change-Number: 42613 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/mediatek/mt8192: add pmic MT6315 driver
by CK HU (Code Review) 18 Nov '20

18 Nov '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45400 to review the following change. Change subject: soc/mediatek/mt8192: add pmic MT6315 driver ...................................................................... soc/mediatek/mt8192: add pmic MT6315 driver Add pmic MT6315 driver. BUG=None TEST=boot asurada. BRANCH=None Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/include/soc/mt6315.h A src/soc/mediatek/mt8192/mt6315.c 4 files changed, 415 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45400/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 0f54c10..9e3f884 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += mt6315.c bootblock-y += mt6359p.c verstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index d9cb684..7987b1c 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pll.h> #include <soc/pmif.h> @@ -14,4 +15,5 @@ mt_pll_init(); mtk_pmif_init(); mt6359p_init(); + mt6315_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/mt6315.h b/src/soc/mediatek/mt8192/include/soc/mt6315.h new file mode 100644 index 0000000..51b719f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6315.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6315_H__ +#define __SOC_MEDIATEK_MT6315_H__ + +#include <types.h> + +enum { + PMIC_HWCID_L = 0x0008, + PMIC_HWCID_H = 0x0009, + PMIC_SWCID_L = 0x000A, + PMIC_SWCID_H = 0x000B, +}; + +struct mt6315_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +#define MT6315_SWCID_H_CODE 0x15 +#define MT6315_SWCID_L_E1_CODE 0x10 +#define MT6315_SWCID_L_E2_CODE 0x20 +#define MT6315_SWCID_L_E3_CODE 0x30 + +enum spmi_slave { + SPMI_SLAVE_0 = 0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15 +}; + +enum { + MT6315_CPU = SPMI_SLAVE_6, + MT6315_GPU = SPMI_SLAVE_7, + MT6315_MAX, +}; + +enum { + MT6315_BUCK_1 = 0, + MT6315_BUCK_2, + MT6315_BUCK_3, + MT6315_BUCK_4, + MT6315_BUCK_max, +}; + +enum { + MT6315_BUCK_TOP_ELR0 = 0x1449, + MT6315_BUCK_TOP_ELR3 = 0x144d, + MT6315_BUCK_VBUCK1_DBG0 = 0x1499, + MT6315_BUCK_VBUCK1_DBG3 = 0x1599, +}; + +void mt6315_init(void); +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uV); +unsigned int mt6315_buck_get_voltage(u32 slvid, u32 buck_id); +#endif /* __SOC_MEDIATEK_MT6315_H__ */ diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c new file mode 100644 index 0000000..5702bc4 --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6315.c @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/pmif.h> +#include <soc/mt6315.h> + +static struct pmif *pmif_arb = NULL; + +static struct mt6315_setting init_setting_A[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* clear boot status */ + {0x12A, 0x3, 0xFF, 0}, + {0xD, 1, 0x1, 0}, + {0xD, 0, 0x1, 0}, + {0x1416, 0xF, 0xF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x7, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x1, 0x1F, 0}, + {0x9A1, 0x1, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x1, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x2, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x2, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x2, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x20, 0x70, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0x80, 0xC1, 0}, + {0x169E, 0xF8, 0xF8, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xDB, 0xFF, 0}, + {0x16A3, 0xA1, 0xFF, 0}, + {0x16A4, 0x1, 0xF, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static struct mt6315_setting init_setting_B[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3a2, 0x2A, 0xFF, 0}, + {0x3a1, 0x7C, 0xFF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x2F, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0xB, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x4, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x4, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x4, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0x7F, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x13, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */ + {0x1440, 0x0, 0x4, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static int mt6315_read(u32 slvid, u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + return pmif_arb->read_cmd(pmif_arb, slvid, addr, rdata); +} + +static int mt6315_write(u32 slvid, u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + return pmif_arb->write_cmd(pmif_arb, slvid, addr, wdata); +} + +static unsigned int mt6315_read_field(u32 slvid, u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + mt6315_read(slvid, reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +static void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + mt6315_read(slvid, reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + mt6315_write(slvid, reg, new); +} + +static void mt6315_wdt_enable(u32 slvid) +{ + mt6315_write_field(slvid, 0x3A9, 0x63, 0xFF, 0); + mt6315_write_field(slvid, 0x3A8, 0x15, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x2, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x1, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x8, 0xFF, 0); + udelay(50); + mt6315_write_field(slvid, 0x128, 0x8, 0xFF, 0); + mt6315_write_field(slvid, 0x3A9, 0, 0xFF, 0); + mt6315_write_field(slvid, 0x3A8, 0, 0xFF, 0); +} + +static void mt6315_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting_A); i++) + mt6315_write_field(MT6315_CPU, + init_setting_A[i].addr, init_setting_A[i].val, + init_setting_A[i].mask, init_setting_A[i].shift); + + for (size_t i = 0; i < ARRAY_SIZE(init_setting_B); i++) + mt6315_write_field(MT6315_GPU, + init_setting_B[i].addr, init_setting_B[i].val, + init_setting_B[i].mask, init_setting_B[i].shift); +} + +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uV) +{ + unsigned int vol_reg, vol_val; + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_TOP_ELR0; + break; + + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_TOP_ELR3; + break; + + default: + assert(0); + return; + }; + + vol_val = buck_uV / 6250; + mt6315_write_field(slvid, vol_reg, vol_val, 0xFF, 0); + + return; +} + +unsigned int mt6315_buck_get_voltage(u32 slvid, u32 buck_id) +{ + u32 vol_reg, vol; + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_VBUCK1_DBG0; + break; + + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_VBUCK1_DBG3; + break; + + default: + assert(0); + return 0; + }; + + vol = mt6315_read_field(slvid, vol_reg, 0xFF, 0); + return vol * 6250; +} + +void mt6315_init(void) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi!"); + + mt6315_wdt_enable(MT6315_CPU); + mt6315_wdt_enable(MT6315_GPU); + mt6315_init_setting(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636 Gerrit-Change-Number: 45400 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: soc/mediatek/mt8192: add pmic MT6359P driver
by CK HU (Code Review) 18 Nov '20

18 Nov '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45399 to review the following change. Change subject: soc/mediatek/mt8192: add pmic MT6359P driver ...................................................................... soc/mediatek/mt8192: add pmic MT6359P driver Add pmic MT6359P driver. TEST=Boots correctly on MT8192EVB. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I62f69490165539847b8b7260942644533b15285b --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/include/soc/mt6359p.h A src/soc/mediatek/mt8192/mt6359p.c 4 files changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45399/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 0fc47c4..0f54c10 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += mt6359p.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 0852f0e..d9cb684 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/mt6359p.h> #include <soc/pll.h> #include <soc/pmif.h> #include <soc/wdt.h> @@ -12,4 +13,5 @@ mtk_wdt_init(); mt_pll_init(); mtk_pmif_init(); + mt6359p_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h new file mode 100644 index 0000000..e1465c8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6359P_H__ +#define __SOC_MEDIATEK_MT6359P_H__ + +#include <types.h> + +enum { + PMIC_HWCID = 0x0008, + PMIC_SWCID = 0x000a, + PMIC_TOP_RST_MISC_SET = 0x014c, + PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_PWRHOLD = 0x0a08, + PMIC_VGPU11_DBG0 = 0x15a6, + PMIC_VGPU11_ELR0 = 0x15b4, + PMIC_VS2_VOTER = 0x18aa, + PMIC_VS2_VOTER_CFG = 0x18b0, + PMIC_VS2_ELR0 = 0x18b4, + PMIC_VSRAM_PROC1_ELR = 0x1b44, + PMIC_VSRAM_PROC2_ELR = 0x1b46, + PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90, + PMIC_VSRAM_PROC2_VOSEL1 = 0x1eb0, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6359P_GPU11 = 0, + MT6359P_SRAM_PROC1, + MT6359P_SRAM_PROC2, + MT6359P_MAX, +}; + +void mt6359p_init(void); +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uV); +unsigned int mt6359p_buck_get_voltage(u32 buck_id); +#endif /* __SOC_MEDIATEK_MT6359P_H__ */ diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c new file mode 100644 index 0000000..5426421 --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -0,0 +1,450 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/pmif.h> +#include <soc/mt6359p.h> + +static struct pmic_setting init_setting[] = { + {0x20, 0xA, 0xA, 0}, + {0x24, 0x1F00, 0x1F00, 0}, + {0x30, 0x1, 0x1, 0}, + {0x32, 0x1, 0x1, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x10, 0x10, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x14A, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x1B2, 0x3, 0x3, 0}, + {0x3B0, 0x0, 0x300, 0}, + {0x790, 0x3, 0x3, 0}, + {0x7A6, 0xF800, 0xFC00, 0}, + {0x7A8, 0x0, 0x280, 0}, + {0x98A, 0x80, 0x80, 0}, + {0x992, 0xF00, 0xF00, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA0C, 0x300, 0x300, 0}, + {0xA10, 0x0, 0x4000, 0}, + {0xA12, 0x1E0, 0x1E0, 0}, + {0xA24, 0xFFFF, 0xFFFF, 0}, + {0xA26, 0xFFE0, 0xFFE0, 0}, + {0xA2C, 0xC0DF, 0xC0DF, 0}, + {0xA2E, 0xEBE0, 0xEBE0, 0}, + {0xA34, 0x8000, 0x8000, 0}, + {0xA3C, 0x1C00, 0x1F00, 0}, + {0xA3E, 0x341, 0x7FFF, 0}, + {0xA40, 0x1042, 0x7FFF, 0}, + {0xA42, 0xC05, 0x7FFF, 0}, + {0xA44, 0x20E5, 0x7FFF, 0}, + {0xA46, 0x2652, 0x7FFF, 0}, + {0xA48, 0x716A, 0x7FFF, 0}, + {0xA4A, 0x62EC, 0x7FFF, 0}, + {0xA4C, 0x5676, 0x7FFF, 0}, + {0xA4E, 0x6F34, 0x7FFF, 0}, + {0xA50, 0xC0, 0x7FFF, 0}, + {0xA9C, 0x4000, 0x4000, 0}, + {0xA9E, 0x2E11, 0xFF11, 0}, + {0xF8C, 0x115, 0x115, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x1198, 0x13, 0x3FF, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11D4, 0x0, 0x2, 0}, + {0x1212, 0x0, 0x2, 0}, + {0x1224, 0x0, 0x2, 0}, + {0x1238, 0x0, 0x2, 0}, + {0x124A, 0x0, 0x2, 0}, + {0x125C, 0x0, 0x2, 0}, + {0x125E, 0x0, 0x8000, 0}, + {0x1260, 0x1, 0xFFF, 0}, + {0x1262, 0x4, 0x4, 0}, + {0x1412, 0x8, 0x8, 0}, + {0x148E, 0x18, 0x7F, 0}, + {0x1492, 0x505, 0x7F7F, 0}, + {0x1514, 0x2, 0x2, 0}, + {0x1520, 0x0, 0x2, 0}, + {0x152C, 0x7F, 0x7F, 0}, + {0x158E, 0x18, 0x7F, 0}, + {0x1592, 0xC00, 0x7F00, 0}, + {0x160E, 0x18, 0x7F, 0}, + {0x1694, 0x2, 0x2, 0}, + {0x16A0, 0x0, 0x2, 0}, + {0x16AE, 0x50, 0x7F, 0}, + {0x170E, 0x18, 0x7F, 0}, + {0x178E, 0x18, 0x7F, 0}, + {0x198A, 0x5004, 0x502C, 0}, + {0x198C, 0x11, 0x3F, 0}, + {0x198E, 0x1E0, 0x1E0, 0}, + {0x1990, 0xFD, 0xFF, 0}, + {0x1994, 0x10, 0x38, 0}, + {0x1996, 0x2004, 0xA02C, 0}, + {0x1998, 0x11, 0x3F, 0}, + {0x199A, 0xFB78, 0xFF78, 0}, + {0x199E, 0x2, 0x7, 0}, + {0x19A0, 0x1050, 0x10F1, 0}, + {0x19A2, 0x18, 0x38, 0}, + {0x19A4, 0xF, 0xF, 0}, + {0x19A6, 0x30, 0xFF, 0}, + {0x19AC, 0x4200, 0x4680, 0}, + {0x19AE, 0x6E, 0x7E, 0}, + {0x19B0, 0x3C00, 0x3C00, 0}, + {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x1A08, 0x4200, 0x4680, 0}, + {0x1A0A, 0x6E, 0x7E, 0}, + {0x1A0C, 0x3C00, 0x3C00, 0}, + {0x1A10, 0x20FD, 0xFFFF, 0}, + {0x1A14, 0x4208, 0x4698, 0}, + {0x1A16, 0x46, 0x7E, 0}, + {0x1A18, 0x3C00, 0x3C00, 0}, + {0x1A1C, 0x30FF, 0xFFFF, 0}, + {0x1A1E, 0x0, 0x200, 0}, + {0x1A20, 0x4208, 0x4698, 0}, + {0x1A22, 0x4A, 0x7E, 0}, + {0x1A24, 0x3C00, 0x3C00, 0}, + {0x1A28, 0x3000, 0xFF00, 0}, + {0x1A2C, 0x20, 0x74, 0}, + {0x1A2E, 0x1E, 0x1E, 0}, + {0x1A30, 0x42, 0xFF, 0}, + {0x1A32, 0x480, 0x7E0, 0}, + {0x1A34, 0x20, 0x74, 0}, + {0x1A36, 0x1E, 0x1E, 0}, + {0x1A38, 0x42, 0xFF, 0}, + {0x1A3A, 0x480, 0x7E0, 0}, + {0x1A3C, 0x14C, 0x3CC, 0}, + {0x1A3E, 0x23C, 0x3FC, 0}, + {0x1A40, 0xC400, 0xFF00, 0}, + {0x1A42, 0x80, 0xFF, 0}, + {0x1A44, 0x702C, 0xFF2C, 0}, + {0x1B0E, 0xF, 0xF, 0}, + {0x1B10, 0x1, 0x1, 0}, + {0x1B14, 0xFFFF, 0xFFFF, 0}, + {0x1B1A, 0x3FFF, 0x3FFF, 0}, + {0x1B32, 0x8, 0x8, 0}, + {0x1B8A, 0x30, 0x8030, 0}, + {0x1B9C, 0x10, 0x8010, 0}, + {0x1BA0, 0x4000, 0x4000, 0}, + {0x1BAE, 0x1410, 0x9C10, 0}, + {0x1BB2, 0x2, 0x2, 0}, + {0x1BC0, 0x10, 0x8010, 0}, + {0x1BD2, 0x13, 0x8013, 0}, + {0x1BE4, 0x10, 0x8010, 0}, + {0x1C0A, 0x10, 0x8010, 0}, + {0x1C1E, 0x10, 0x8010, 0}, + {0x1C30, 0x10, 0x8010, 0}, + {0x1C42, 0x10, 0x8010, 0}, + {0x1C54, 0x32, 0x8033, 0}, + {0x1C66, 0x10, 0x8010, 0}, + {0x1C8A, 0x10, 0x8010, 0}, + {0x1C8E, 0x4000, 0x4000, 0}, + {0x1C9C, 0x10, 0x8010, 0}, + {0x1CAE, 0x10, 0x8010, 0}, + {0x1CC0, 0x10, 0x8010, 0}, + {0x1CD2, 0x33, 0x8033, 0}, + {0x1CE4, 0x33, 0x8033, 0}, + {0x1D0A, 0x10, 0x8010, 0}, + {0x1D1E, 0x10, 0x8010, 0}, + {0x1D22, 0x4000, 0x4000, 0}, + {0x1D30, 0x10, 0x8010, 0}, + {0x1D34, 0x4000, 0x4000, 0}, + {0x1D42, 0x30, 0x8030, 0}, + {0x1D46, 0x4000, 0x4000, 0}, + {0x1D54, 0x30, 0x8030, 0}, + {0x1D66, 0x32, 0x8033, 0}, + {0x1D8A, 0x10, 0x8010, 0}, + {0x1D9C, 0x10, 0x8010, 0}, + {0x1E8A, 0x10, 0x8010, 0}, + {0x1E92, 0xC12, 0x7F7F, 0}, + {0x1EAA, 0x10, 0x8010, 0}, + {0x1EB2, 0xC1F, 0x7F7F, 0}, + {0x1F0A, 0x10, 0x8010, 0}, + {0x1F12, 0xC1F, 0x7F7F, 0}, + {0x1F30, 0x10, 0x8010, 0}, + {0x1F38, 0xF1F, 0x7F7F, 0}, + {0x200A, 0x8, 0xC, 0}, + {0x202C, 0x8, 0xC, 0}, + {0x208C, 0x100, 0xF00, 0}, + {0x209C, 0x80, 0x1E0, 0}, +}; + +static struct pmic_setting lp_setting[] = { + /* Suspend */ + {0x1520, 0x0, 0x1, 0x1}, + {0x1514, 0x1, 0x1, 0x1}, + {0x151a, 0x0, 0x1, 0x1}, + {0x14a0, 0x1, 0x1, 0x1}, + {0x1494, 0x1, 0x1, 0x1}, + {0x149a, 0x1, 0x1, 0x1}, + {0x1714, 0x1, 0x1, 0xf}, + {0x1794, 0x1, 0x1, 0xf}, + {0x15a0, 0x1, 0x1, 0x0}, + {0x1594, 0x1, 0x1, 0x0}, + {0x159a, 0x1, 0x1, 0x0}, + {0x1614, 0x1, 0x1, 0xf}, + {0x16a0, 0x0, 0x1, 0x1}, + {0x1694, 0x1, 0x1, 0x1}, + {0x169a, 0x0, 0x1, 0x1}, + {0x1820, 0x1, 0x1, 0x0}, + {0x1814, 0x1, 0x1, 0x0}, + {0x181a, 0x1, 0x1, 0x0}, + {0x18a0, 0x1, 0x1, 0x0}, + {0x1894, 0x1, 0x1, 0x0}, + {0x189a, 0x1, 0x1, 0x0}, + {0x1e96, 0x1, 0x1, 0xf}, + {0x1eb6, 0x1, 0x1, 0xf}, + {0x1f16, 0x1, 0x1, 0xf}, + {0x1f3c, 0x1, 0x1, 0xf}, + {0x1c58, 0x1, 0x1, 0xf}, + {0x1d8e, 0x1, 0x1, 0xf}, + {0x1c34, 0x1, 0x1, 0xf}, + {0x1c22, 0x1, 0x1, 0xf}, + {0x1bae, 0x0, 0x1, 0xb}, + {0x1bb2, 0x1, 0x1, 0x1}, + {0x1bb8, 0x0, 0x1, 0x1}, + {0x1cb2, 0x1, 0x1, 0xf}, + {0x1bd6, 0x1, 0x1, 0xf}, + {0x1bc0, 0x1, 0x1, 0xa}, + {0x1bc4, 0x1, 0x1, 0x0}, + {0x1bca, 0x1, 0x1, 0x0}, + {0x1d22, 0x1, 0x1, 0xe}, + {0x1d28, 0x0, 0x1, 0xe}, + {0x1c66, 0x1, 0x1, 0xa}, + {0x1c6a, 0x1, 0x1, 0x0}, + {0x1c70, 0x1, 0x1, 0x0}, + {0x1c42, 0x1, 0x1, 0xb}, + {0x1c46, 0x1, 0x1, 0x1}, + {0x1c4c, 0x1, 0x1, 0x1}, + {0x1d34, 0x1, 0x1, 0xe}, + {0x1d3a, 0x0, 0x1, 0xe}, + {0x1b8a, 0x0, 0x1, 0xb}, + {0x1b8e, 0x1, 0x1, 0x1}, + {0x1b94, 0x0, 0x1, 0x1}, + {0x1d42, 0x1, 0x1, 0xa}, + {0x1d46, 0x1, 0x1, 0x0}, + {0x1d4c, 0x0, 0x1, 0x0}, + {0x1ca0, 0x1, 0x1, 0xf}, + {0x1c8a, 0x1, 0x1, 0xa}, + {0x1c8e, 0x1, 0x1, 0x0}, + {0x1c94, 0x1, 0x1, 0x0}, + {0x1b9c, 0x1, 0x1, 0xa}, + {0x1ba0, 0x1, 0x1, 0x0}, + {0x1ba6, 0x1, 0x1, 0x0}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xa}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1cc4, 0x1, 0x1, 0xf}, + {0x1d6a, 0x1, 0x1, 0xf}, + {0x1cd6, 0x1, 0x1, 0xf}, + {0x1ce8, 0x1, 0x1, 0xf}, + {0x1da0, 0x1, 0x1, 0xf}, + {0x1d58, 0x1, 0x1, 0xf}, + + /* Deepidle */ + {0x15a0, 0x1, 0x1, 0x2}, + {0x1594, 0x1, 0x1, 0x2}, + {0x159a, 0x1, 0x1, 0x2}, + {0x1820, 0x1, 0x1, 0x2}, + {0x1814, 0x1, 0x1, 0x2}, + {0x181a, 0x1, 0x1, 0x2}, + {0x18a0, 0x1, 0x1, 0x2}, + {0x1894, 0x1, 0x1, 0x2}, + {0x189a, 0x1, 0x1, 0x2}, + {0x1bc0, 0x1, 0x1, 0xc}, + {0x1bc4, 0x1, 0x1, 0x2}, + {0x1bca, 0x1, 0x1, 0x2}, + {0x1c66, 0x1, 0x1, 0xc}, + {0x1c6a, 0x1, 0x1, 0x2}, + {0x1c70, 0x1, 0x1, 0x2}, + {0x1d42, 0x1, 0x1, 0xc}, + {0x1d46, 0x1, 0x1, 0x2}, + {0x1d4c, 0x0, 0x1, 0x2}, + {0x1c8a, 0x1, 0x1, 0xc}, + {0x1c8e, 0x1, 0x1, 0x2}, + {0x1c94, 0x1, 0x1, 0x2}, + {0x1b9c, 0x1, 0x1, 0xc}, + {0x1ba0, 0x1, 0x1, 0x2}, + {0x1ba6, 0x1, 0x1, 0x2}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xc}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, +}; + +static struct pmif *pmif_arb = NULL; +static s32 mt6359p_read(u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + return pmif_arb->read_cmd(pmif_arb, 0, addr, rdata); +} + +static s32 mt6359p_write(u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + return pmif_arb->write_cmd(pmif_arb, 0, addr, wdata); +} + +static u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + mt6359p_read(reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +static void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + mt6359p_read(reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + mt6359p_write(reg, new); +} + +static void pmic_set_power_hold(void) +{ + mt6359p_write_field(PMIC_PWRHOLD, 1, 0x1, 0); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x20, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6359p_write_field(PMIC_TOP_RST_MISC_CLR, 0x02, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); +} + +static void pmic_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6359p_write_field( + init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +static void pmic_lp_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) + mt6359p_write_field( + lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +static void pmic_wk_vs2_voter_setting(void) +{ + /* + * 1. Set VS2_VOTER_VOSEL = 1.35V + * 2. Clear VS2_VOTER + * 3. Set VS2_VOSEL = 1.4V + **/ + mt6359p_write_field(PMIC_VS2_VOTER_CFG, 0x2C, 0x7F, 0); + mt6359p_write_field(PMIC_VS2_VOTER, 0, 0xFFF, 0); + mt6359p_write_field(PMIC_VS2_ELR0, 0x30, 0x7F, 0); +} + +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uV) +{ + u32 vol_offset, vol_reg, vol; + + switch (buck_id) { + case MT6359P_GPU11: + vol_offset = 400000; + vol_reg = PMIC_VGPU11_ELR0; + break; + + case MT6359P_SRAM_PROC1: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_ELR; + break; + + case MT6359P_SRAM_PROC2: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_ELR; + break; + + default: + /* assert(0); */ + return; + }; + + vol = (buck_uV - vol_offset) / 6250; + mt6359p_write_field(vol_reg, vol, 0x7F, 0); +} + +unsigned int mt6359p_buck_get_voltage(u32 buck_id) +{ + u32 vol_shift, vol_offset, vol_reg, vol; + + switch (buck_id) { + case MT6359P_GPU11: + vol_shift = 0; + vol_offset = 400000; + vol_reg = PMIC_VGPU11_DBG0; + break; + + case MT6359P_SRAM_PROC1: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_VOSEL1; + break; + + case MT6359P_SRAM_PROC2: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_VOSEL1; + break; + + default: + assert(0); + return 0; + }; + + vol = mt6359p_read_field(vol_reg, 0x7F, vol_shift); + return vol_offset + vol * 6250; +} + + +void mt6359p_init(void) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi!"); + + printk(BIOS_ERR, "[%s] SWCID(0x%x), HWCID(0x%x)\n", __func__, + mt6359p_read_field(PMIC_SWCID, 0xFFFF, 0), + mt6359p_read_field(PMIC_HWCID, 0xFFFF, 0)); + + pmic_set_power_hold(); + pmic_wdt_set(); + pmic_init_setting(); + pmic_lp_setting(); + pmic_wk_vs2_voter_setting(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62f69490165539847b8b7260942644533b15285b Gerrit-Change-Number: 45399 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

6 21

Change in coreboot[master]: mainboard/volteer: enable early tcss chrome ec related code in mainboard
by Brandon Breitenstein (Code Review) 18 Nov '20

18 Nov '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45742 ) Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ...................................................................... mainboard/volteer: enable early tcss chrome ec related code in mainboard Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard. BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 23c3e92..80a04d0 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -5,9 +5,11 @@ #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> +#include <ec/google/chromeec/ec.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> +#include <soc/early_tcss.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -65,6 +67,78 @@ } } +void mainboard_early_tcss_enable(void) +{ + uint8_t dp_mode; + unsigned int num_ports; + int ret, i; + bool ufp, acc; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) { + printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); + return; + } + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); + continue; + } + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_port_info failed\n", i); + continue; + } + + mux_data.usb2_port = port_map & USB_2_PORT_MASK; + mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4; + + //Add check for connected maybe? + + ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: pd_control failed\n", i); + continue; + } + + mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_data.ufp = !!ufp; + mux_data.acc = !!acc; + mux_data.dp_mode = dp_mode; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "DP Mode = %x\n" + "dp = %d\n" + "usb = %d\n" + "cable = %d\n" + "polarity = %d\n" + "hpd_lvl = %d\n" + "hpd_irq = %d\n" + "ufp = %d\n" + "dbg_acc = %d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.dp_mode, mux_data.dp, + mux_data.usb, mux_data.cable, mux_data.polarity, + mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp, + mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 43ba255..179aeb0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -59,6 +59,8 @@ register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" + register "RMT" = "1" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/45742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Gerrit-Change-Number: 45742 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

4 28

Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45540 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "Die()" needs <console/console.h>. Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/poppy/variants/nami/memory.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_i2c.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45540/1 diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 3e482a9..6faca2b 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <gpio.h> #include <variant/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 46499f4..bea9cd8 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <console/console.h> #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 3dbe3e6..9614b4e 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> +#include <console/console.h> #include <string.h> #include <soc/qupv3_config.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index b80c3df..c9adba4 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/i2c_simple.h> #include <gpio.h> #include <inttypes.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Gerrit-Change-Number: 45540 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45539 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/aspeed/common/ast_post.c M src/lib/asan.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/hatch/romstage_spd_smbus.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/volteer/romstage.c M src/security/vboot/vboot_logic.c M src/soc/amd/picasso/reset.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/intel/ibexpeak/early_pch.c 19 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45539/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index b5f794b..bf974ff 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -2,6 +2,8 @@ /* * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ + +#include <console/console.h> #include <edid.h> #include <device/pci_def.h> diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index c909182..68ecca8 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -2,6 +2,7 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 +#include <console/console.h> #include <delay.h> #include "ast_drv.h" diff --git a/src/lib/asan.c b/src/lib/asan.c index 6de0de1..cf91111 100644 --- a/src/lib/asan.c +++ b/src/lib/asan.c @@ -8,6 +8,7 @@ * */ +#include <console/console.h> #include <symbols.h> #include <assert.h> #include <arch/symbols.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index fcf50a9..1af2e02 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <boot/coreboot_tables.h> +#include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> #include "../qemu-i440fx/fw_cfg.h" diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index d21e867..e697379 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 3b247e9..d641405 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <chip.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci_ids.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 564c18c..cf9344e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 57f3a3b..54d8b0d 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootmode.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8893785..375bb0c 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <fsp/soc_binding.h> #include <fw_config.h> diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c4c3b4b..43405bc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -2,6 +2,7 @@ #include <arch/exception.h> #include <assert.h> +#include <console/console.h> #include <bootmode.h> #include <fmap.h> #include <security/tpm/tspi/crtm.h> diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 902538ff..7a0074c 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <console/console.h> #include <reset.h> #include <soc/pci_devs.h> #include <soc/reset.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 15874c0..f3e47e5 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/sort.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f..16f7856 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <device/pci.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb..0316e1e 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <assert.h> +#include <console/console.h> #include <post.h> #include <device/pci.h> #include <soc/acpi.h> diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 62aa4d1..e9665c3 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -3,6 +3,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <console/console.h> #include <device/pci_def.h> #include <hob_iiouds.h> diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 919735d..8763a9d 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index cac590c..6750c3e 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/qcom_qup_se.h> struct qup qup[12] = { diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index d086a27..23914bb 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <lib.h> #include <soc/clock.h> #include <soc/gpio.h> diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac009..122c8e4 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Gerrit-Change-Number: 45539 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020